| 1 | /* |
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| 2 | Copyright (c) 2015, Synopsys, Inc. All rights reserved. |
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| 3 | |
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| 4 | Redistribution and use in source and binary forms, with or without |
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| 5 | modification, are permitted provided that the following conditions are met: |
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| 6 | |
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| 7 | 1) Redistributions of source code must retain the above copyright notice, |
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| 8 | this list of conditions and the following disclaimer. |
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| 9 | |
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| 10 | 2) Redistributions in binary form must reproduce the above copyright notice, |
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| 11 | this list of conditions and the following disclaimer in the documentation |
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| 12 | and/or other materials provided with the distribution. |
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| 13 | |
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| 14 | 3) Neither the name of the Synopsys, Inc., nor the names of its contributors |
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| 15 | may be used to endorse or promote products derived from this software |
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| 16 | without specific prior written permission. |
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| 17 | |
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| 18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 19 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 20 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 21 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE |
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| 22 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 23 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 24 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 25 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 26 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 27 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 28 | POSSIBILITY OF SUCH DAMAGE. |
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| 29 | */ |
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| 30 | |
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| 31 | /* This implementation is optimized for performance. For code size a generic |
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| 32 | implementation of this function from newlib/libc/string/memcmp.c will be |
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| 33 | used. */ |
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| 34 | #if !defined (__OPTIMIZE_SIZE__) && !defined (PREFER_SIZE_OVER_SPEED) |
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| 35 | |
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| 36 | #include "asm.h" |
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| 37 | |
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| 38 | #if !defined (__ARC601__) && defined (__ARC_NORM__) \ |
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| 39 | && defined (__ARC_BARREL_SHIFTER__) |
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| 40 | |
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| 41 | #ifdef __LITTLE_ENDIAN__ |
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| 42 | #define WORD2 r2 |
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| 43 | #define SHIFT r3 |
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| 44 | #else /* BIG ENDIAN */ |
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| 45 | #define WORD2 r3 |
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| 46 | #define SHIFT r2 |
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| 47 | #endif |
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| 48 | |
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| 49 | ENTRY (memcmp) |
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| 50 | or r12,r0,r1 |
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| 51 | asl_s r12,r12,30 |
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| 52 | #if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__) |
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| 53 | sub_l r3,r2,1 |
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| 54 | brls r2,r12,.Lbytewise |
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| 55 | #else |
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| 56 | brls.d r2,r12,.Lbytewise |
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| 57 | sub_s r3,r2,1 |
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| 58 | #endif |
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| 59 | ld r4,[r0,0] |
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| 60 | ld r5,[r1,0] |
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| 61 | lsr.f lp_count,r3,3 |
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| 62 | #ifdef __ARCEM__ |
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| 63 | /* A branch can't be the last instruction in a zero overhead loop. |
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| 64 | So we move the branch to the start of the loop, duplicate it |
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| 65 | after the end, and set up r12 so that the branch isn't taken |
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| 66 | initially. */ |
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| 67 | mov_s r12,WORD2 |
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| 68 | lpne .Loop_end |
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| 69 | brne WORD2,r12,.Lodd |
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| 70 | ld WORD2,[r0,4] |
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| 71 | #else |
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| 72 | lpne .Loop_end |
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| 73 | ld_s WORD2,[r0,4] |
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| 74 | #endif |
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| 75 | ld_s r12,[r1,4] |
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| 76 | brne r4,r5,.Leven |
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| 77 | ld.a r4,[r0,8] |
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| 78 | ld.a r5,[r1,8] |
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| 79 | #ifdef __ARCEM__ |
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| 80 | .Loop_end: |
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| 81 | brne WORD2,r12,.Lodd |
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| 82 | #else |
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| 83 | brne WORD2,r12,.Lodd |
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| 84 | #ifdef __ARCHS__ |
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| 85 | nop |
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| 86 | #endif |
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| 87 | .Loop_end: |
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| 88 | #endif |
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| 89 | asl_s SHIFT,SHIFT,3 |
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| 90 | bcc_s .Last_cmp |
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| 91 | brne r4,r5,.Leven |
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| 92 | ld r4,[r0,4] |
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| 93 | ld r5,[r1,4] |
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| 94 | #ifdef __LITTLE_ENDIAN__ |
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| 95 | #if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__) |
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| 96 | nop_s |
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| 97 | ; one more load latency cycle |
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| 98 | .Last_cmp: |
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| 99 | xor r0,r4,r5 |
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| 100 | bset r0,r0,SHIFT |
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| 101 | sub_s r1,r0,1 |
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| 102 | bic_s r1,r1,r0 |
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| 103 | norm r1,r1 |
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| 104 | b.d .Leven_cmp |
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| 105 | and r1,r1,24 |
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| 106 | .Leven: |
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| 107 | xor r0,r4,r5 |
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| 108 | sub_s r1,r0,1 |
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| 109 | bic_s r1,r1,r0 |
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| 110 | norm r1,r1 |
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| 111 | ; slow track insn |
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| 112 | and r1,r1,24 |
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| 113 | .Leven_cmp: |
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| 114 | asl r2,r4,r1 |
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| 115 | asl r12,r5,r1 |
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| 116 | lsr_s r2,r2,1 |
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| 117 | lsr_s r12,r12,1 |
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| 118 | j_s.d [blink] |
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| 119 | sub r0,r2,r12 |
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| 120 | .balign 4 |
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| 121 | .Lodd: |
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| 122 | xor r0,WORD2,r12 |
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| 123 | sub_s r1,r0,1 |
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| 124 | bic_s r1,r1,r0 |
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| 125 | norm r1,r1 |
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| 126 | ; slow track insn |
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| 127 | and r1,r1,24 |
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| 128 | asl_s r2,r2,r1 |
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| 129 | asl_s r12,r12,r1 |
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| 130 | lsr_s r2,r2,1 |
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| 131 | lsr_s r12,r12,1 |
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| 132 | j_s.d [blink] |
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| 133 | sub r0,r2,r12 |
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| 134 | #else /* !__ARC700__ */ |
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| 135 | .balign 4 |
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| 136 | .Last_cmp: |
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| 137 | xor r0,r4,r5 |
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| 138 | b.d .Leven_cmp |
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| 139 | bset r0,r0,SHIFT |
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| 140 | .Lodd: |
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| 141 | mov_s r4,WORD2 |
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| 142 | mov_s r5,r12 |
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| 143 | .Leven: |
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| 144 | xor r0,r4,r5 |
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| 145 | .Leven_cmp: |
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| 146 | mov_s r1,0x80808080 |
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| 147 | ; uses long immediate |
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| 148 | sub_s r12,r0,1 |
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| 149 | bic_s r0,r0,r12 |
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| 150 | sub r0,r1,r0 |
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| 151 | xor_s r0,r0,r1 |
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| 152 | and r1,r5,r0 |
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| 153 | and r0,r4,r0 |
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| 154 | xor.f 0,r0,r1 |
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| 155 | sub_s r0,r0,r1 |
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| 156 | j_s.d [blink] |
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| 157 | mov.mi r0,r1 |
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| 158 | #endif /* !__ARC700__ */ |
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| 159 | #else /* BIG ENDIAN */ |
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| 160 | .Last_cmp: |
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| 161 | neg_s SHIFT,SHIFT |
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| 162 | lsr r4,r4,SHIFT |
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| 163 | lsr r5,r5,SHIFT |
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| 164 | ; slow track insn |
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| 165 | .Leven: |
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| 166 | sub.f r0,r4,r5 |
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| 167 | mov.ne r0,1 |
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| 168 | j_s.d [blink] |
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| 169 | bset.cs r0,r0,31 |
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| 170 | .Lodd: |
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| 171 | cmp_s WORD2,r12 |
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| 172 | #if defined (__ARC700__) || defined (__ARCEM__) || defined (__ARCHS__) |
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| 173 | mov_s r0,1 |
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| 174 | j_s.d [blink] |
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| 175 | bset.cs r0,r0,31 |
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| 176 | #else |
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| 177 | j_s.d [blink] |
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| 178 | rrc r0,2 |
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| 179 | #endif /* __ARC700__ || __ARCEM__ || __ARCHS__ */ |
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| 180 | #endif /* ENDIAN */ |
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| 181 | .balign 4 |
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| 182 | .Lbytewise: |
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| 183 | breq r2,0,.Lnil |
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| 184 | ldb r4,[r0,0] |
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| 185 | ldb r5,[r1,0] |
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| 186 | lsr.f lp_count,r3 |
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| 187 | #ifdef __ARCEM__ |
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| 188 | mov r12,r3 |
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| 189 | lpne .Lbyte_end |
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| 190 | brne r3,r12,.Lbyte_odd |
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| 191 | #else |
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| 192 | lpne .Lbyte_end |
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| 193 | #endif |
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| 194 | ldb_s r3,[r0,1] |
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| 195 | ldb_l r12,[r1,1] |
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| 196 | brne r4,r5,.Lbyte_even |
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| 197 | ldb.a r4,[r0,2] |
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| 198 | ldb.a r5,[r1,2] |
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| 199 | #ifdef __ARCEM__ |
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| 200 | .Lbyte_end: |
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| 201 | brne r3,r12,.Lbyte_odd |
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| 202 | #else |
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| 203 | brne r3,r12,.Lbyte_odd |
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| 204 | #ifdef __ARCHS__ |
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| 205 | nop |
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| 206 | #endif |
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| 207 | .Lbyte_end: |
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| 208 | #endif |
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| 209 | bcc_l .Lbyte_even |
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| 210 | brne r4,r5,.Lbyte_even |
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| 211 | ldb_s r3,[r0,1] |
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| 212 | ldb_s r12,[r1,1] |
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| 213 | .Lbyte_odd: |
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| 214 | j_s.d [blink] |
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| 215 | sub r0,r3,r12 |
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| 216 | .Lbyte_even: |
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| 217 | j_s.d [blink] |
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| 218 | sub r0,r4,r5 |
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| 219 | .Lnil: |
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| 220 | j_s.d [blink] |
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| 221 | mov_l r0,0 |
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| 222 | ENDFUNC (memcmp) |
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| 223 | #endif /* !__ARC601__ && __ARC_NORM__ && __ARC_BARREL_SHIFTER__ */ |
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| 224 | |
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| 225 | #endif /* !__OPTIMIZE_SIZE__ && !PREFER_SIZE_OVER_SPEED */ |
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