1 | /* |
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2 | * Copyright (c) 2014 ARM Ltd |
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3 | * All rights reserved. |
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4 | * |
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5 | * Redistribution and use in source and binary forms, with or without |
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6 | * modification, are permitted provided that the following conditions |
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7 | * are met: |
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8 | * 1. Redistributions of source code must retain the above copyright |
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9 | * notice, this list of conditions and the following disclaimer. |
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10 | * 2. Redistributions in binary form must reproduce the above copyright |
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11 | * notice, this list of conditions and the following disclaimer in the |
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12 | * documentation and/or other materials provided with the distribution. |
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13 | * 3. The name of the company may not be used to endorse or promote |
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14 | * products derived from this software without specific prior written |
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15 | * permission. |
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16 | * |
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17 | * THIS SOFTWARE IS PROVIDED BY ARM LTD ``AS IS'' AND ANY EXPRESS OR IMPLIED |
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18 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF |
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19 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. |
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20 | * IN NO EVENT SHALL ARM LTD BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, |
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21 | * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED |
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22 | * TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR |
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23 | * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF |
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24 | * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING |
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25 | * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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26 | * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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27 | */ |
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28 | |
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29 | /* Implementation of strcmp for ARMv6m. This version is only used in |
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30 | ARMv6-M when we want an efficient implementation. Otherwize if the |
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31 | code size is preferred, strcmp-armv4t.S will be used. */ |
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32 | |
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33 | .thumb_func |
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34 | .syntax unified |
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35 | .arch armv6-m |
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36 | |
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37 | .macro DoSub n, label |
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38 | subs r0, r0, r1 |
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39 | #ifdef __ARM_BIG_ENDIAN |
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40 | lsrs r1, r4, \n |
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41 | #else |
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42 | lsls r1, r4, \n |
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43 | #endif |
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44 | orrs r1, r0 |
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45 | bne \label |
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46 | .endm |
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47 | |
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48 | .macro Byte_Test n, label |
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49 | lsrs r0, r2, \n |
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50 | lsrs r1, r3, \n |
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51 | DoSub \n, \label |
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52 | .endm |
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53 | |
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54 | .text |
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55 | def_fn strcmp |
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56 | .cfi_sections .debug_frame |
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57 | .cfi_startproc |
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58 | mov r2, r0 |
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59 | push {r4, r5, r6, lr} |
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60 | orrs r2, r1 |
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61 | lsls r2, r2, #30 |
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62 | bne 6f |
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63 | ldr r5, =0x01010101 |
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64 | lsls r6, r5, #7 |
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65 | 1: |
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66 | ldmia r0!, {r2} |
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67 | ldmia r1!, {r3} |
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68 | subs r4, r2, r5 |
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69 | bics r4, r2 |
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70 | ands r4, r6 |
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71 | beq 3f |
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72 | |
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73 | #ifdef __ARM_BIG_ENDIAN |
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74 | Byte_Test #24, 4f |
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75 | Byte_Test #16, 4f |
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76 | Byte_Test #8, 4f |
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77 | |
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78 | b 7f |
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79 | 3: |
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80 | cmp r2, r3 |
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81 | beq 1b |
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82 | cmp r2, r3 |
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83 | #else |
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84 | uxtb r0, r2 |
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85 | uxtb r1, r3 |
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86 | DoSub #24, 2f |
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87 | |
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88 | uxth r0, r2 |
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89 | uxth r1, r3 |
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90 | DoSub #16, 2f |
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91 | |
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92 | lsls r0, r2, #8 |
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93 | lsls r1, r3, #8 |
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94 | lsrs r0, r0, #8 |
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95 | lsrs r1, r1, #8 |
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96 | DoSub #8, 2f |
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97 | |
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98 | lsrs r0, r2, #24 |
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99 | lsrs r1, r3, #24 |
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100 | subs r0, r0, r1 |
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101 | 2: |
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102 | pop {r4, r5, r6, pc} |
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103 | |
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104 | 3: |
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105 | cmp r2, r3 |
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106 | beq 1b |
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107 | rev r0, r2 |
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108 | rev r1, r3 |
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109 | cmp r0, r1 |
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110 | #endif |
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111 | |
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112 | bls 5f |
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113 | movs r0, #1 |
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114 | 4: |
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115 | pop {r4, r5, r6, pc} |
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116 | 5: |
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117 | movs r0, #0 |
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118 | mvns r0, r0 |
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119 | pop {r4, r5, r6, pc} |
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120 | 6: |
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121 | ldrb r2, [r0, #0] |
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122 | ldrb r3, [r1, #0] |
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123 | adds r0, #1 |
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124 | adds r1, #1 |
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125 | cmp r2, #0 |
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126 | beq 7f |
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127 | cmp r2, r3 |
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128 | bne 7f |
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129 | ldrb r2, [r0, #0] |
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130 | ldrb r3, [r1, #0] |
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131 | adds r0, #1 |
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132 | adds r1, #1 |
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133 | cmp r2, #0 |
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134 | beq 7f |
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135 | cmp r2, r3 |
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136 | beq 6b |
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137 | 7: |
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138 | subs r0, r2, r3 |
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139 | pop {r4, r5, r6, pc} |
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140 | .cfi_endproc |
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141 | .size strcmp, . - strcmp |
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