| 1 | /* |
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| 2 | * longjmp for the Blackfin processor |
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| 3 | * |
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| 4 | * Copyright (C) 2006 Analog Devices, Inc. |
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| 5 | * |
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| 6 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 7 | * and license this software and its documentation for any purpose, provided |
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| 8 | * that existing copyright notices are retained in all copies and that this |
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| 9 | * notice is included verbatim in any distributions. No written agreement, |
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| 10 | * license, or royalty fee is required for any of the authorized uses. |
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| 11 | * Modifications to this software may be copyrighted by their authors |
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| 12 | * and need not follow the licensing terms described here, provided that |
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| 13 | * the new terms are clearly indicated on the first page of each file where |
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| 14 | * they apply. |
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| 15 | */ |
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| 16 | |
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| 17 | #define _ASM |
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| 18 | #define _SETJMP_H |
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| 19 | |
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| 20 | |
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| 21 | .text; |
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| 22 | .align 4; |
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| 23 | .globl _longjmp; |
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| 24 | .type _longjmp, STT_FUNC; |
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| 25 | _longjmp: |
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| 26 | P0 = R0; |
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| 27 | R0 = [P0 + 0x00]; |
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| 28 | [--SP] = R0; /* Put P0 on the stack */ |
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| 29 | |
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| 30 | P1 = [P0 + 0x04]; |
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| 31 | P2 = [P0 + 0x08]; |
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| 32 | P3 = [P0 + 0x0C]; |
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| 33 | P4 = [P0 + 0x10]; |
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| 34 | P5 = [P0 + 0x14]; |
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| 35 | |
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| 36 | FP = [P0 + 0x18]; |
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| 37 | R0 = [SP++]; /* Grab P0 from old stack */ |
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| 38 | SP = [P0 + 0x1C]; /* Update Stack Pointer */ |
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| 39 | [--SP] = R0; /* Put P0 on new stack */ |
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| 40 | [--SP] = R1; /* Put VAL arg on new stack */ |
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| 41 | |
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| 42 | R0 = [P0 + 0x20]; /* Data Registers */ |
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| 43 | R1 = [P0 + 0x24]; |
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| 44 | R2 = [P0 + 0x28]; |
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| 45 | R3 = [P0 + 0x2C]; |
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| 46 | R4 = [P0 + 0x30]; |
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| 47 | R5 = [P0 + 0x34]; |
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| 48 | R6 = [P0 + 0x38]; |
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| 49 | R7 = [P0 + 0x3C]; |
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| 50 | |
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| 51 | R0 = [P0 + 0x40]; |
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| 52 | ASTAT = R0; |
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| 53 | |
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| 54 | R0 = [P0 + 0x44]; /* Loop Counters */ |
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| 55 | LC0 = R0; |
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| 56 | R0 = [P0 + 0x48]; |
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| 57 | LC1 = R0; |
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| 58 | |
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| 59 | R0 = [P0 + 0x4C]; /* Accumulators */ |
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| 60 | A0.W = R0; |
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| 61 | R0 = [P0 + 0x50]; |
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| 62 | A0.X = R0; |
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| 63 | R0 = [P0 + 0x54]; |
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| 64 | A1.W = R0; |
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| 65 | R0 = [P0 + 0x58]; |
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| 66 | A1.X = R0; |
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| 67 | |
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| 68 | R0 = [P0 + 0x5C]; /* Index Registers */ |
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| 69 | I0 = R0; |
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| 70 | R0 = [P0 + 0x60]; |
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| 71 | I1 = R0; |
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| 72 | R0 = [P0 + 0x64]; |
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| 73 | I2 = R0; |
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| 74 | R0 = [P0 + 0x68]; |
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| 75 | I3 = R0; |
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| 76 | |
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| 77 | R0 = [P0 + 0x6C]; /* Modifier Registers */ |
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| 78 | M0 = R0; |
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| 79 | R0 = [P0 + 0x70]; |
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| 80 | M1 = R0; |
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| 81 | R0 = [P0 + 0x74]; |
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| 82 | M2 = R0; |
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| 83 | R0 = [P0 + 0x78]; |
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| 84 | M3 = R0; |
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| 85 | |
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| 86 | R0 = [P0 + 0x7C]; /* Length Registers */ |
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| 87 | L0 = R0; |
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| 88 | R0 = [P0 + 0x80]; |
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| 89 | L1 = R0; |
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| 90 | R0 = [P0 + 0x84]; |
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| 91 | L2 = R0; |
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| 92 | R0 = [P0 + 0x88]; |
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| 93 | L3 = R0; |
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| 94 | |
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| 95 | R0 = [P0 + 0x8C]; /* Base Registers */ |
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| 96 | B0 = R0; |
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| 97 | R0 = [P0 + 0x90]; |
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| 98 | B1 = R0; |
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| 99 | R0 = [P0 + 0x94]; |
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| 100 | B2 = R0; |
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| 101 | R0 = [P0 + 0x98]; |
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| 102 | B3 = R0; |
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| 103 | |
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| 104 | R0 = [P0 + 0x9C]; /* Return Address (PC) */ |
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| 105 | RETS = R0; |
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| 106 | |
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| 107 | R0 = [SP++]; |
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| 108 | P0 = [SP++]; |
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| 109 | |
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| 110 | CC = R0 == 0; |
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| 111 | IF !CC JUMP 1f; |
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| 112 | R0 = 1; |
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| 113 | 1: |
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| 114 | RTS; |
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| 115 | .size _longjmp, .-_longjmp; |
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