| 1 | /* |
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| 2 | * setjmp for the Blackfin processor |
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| 3 | * |
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| 4 | * Copyright (C) 2006 Analog Devices, Inc. |
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| 5 | * |
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| 6 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 7 | * and license this software and its documentation for any purpose, provided |
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| 8 | * that existing copyright notices are retained in all copies and that this |
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| 9 | * notice is included verbatim in any distributions. No written agreement, |
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| 10 | * license, or royalty fee is required for any of the authorized uses. |
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| 11 | * Modifications to this software may be copyrighted by their authors |
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| 12 | * and need not follow the licensing terms described here, provided that |
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| 13 | * the new terms are clearly indicated on the first page of each file where |
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| 14 | * they apply. |
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| 15 | */ |
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| 16 | |
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| 17 | |
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| 18 | #define _ASM |
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| 19 | #define _SETJMP_H |
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| 20 | |
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| 21 | .text; |
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| 22 | .align 4; |
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| 23 | .globl _setjmp; |
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| 24 | .type _setjmp, STT_FUNC; |
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| 25 | |
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| 26 | _setjmp: |
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| 27 | [--SP] = P0; /* Save P0 */ |
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| 28 | P0 = R0; |
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| 29 | R0 = [SP++]; |
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| 30 | [P0 + 0x00] = R0; /* Save saved P0 */ |
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| 31 | [P0 + 0x04] = P1; |
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| 32 | [P0 + 0x08] = P2; |
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| 33 | [P0 + 0x0C] = P3; |
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| 34 | [P0 + 0x10] = P4; |
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| 35 | [P0 + 0x14] = P5; |
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| 36 | |
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| 37 | [P0 + 0x18] = FP; /* Frame Pointer */ |
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| 38 | [P0 + 0x1C] = SP; /* Stack Pointer */ |
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| 39 | |
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| 40 | [P0 + 0x20] = P0; /* Data Registers */ |
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| 41 | [P0 + 0x24] = R1; |
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| 42 | [P0 + 0x28] = R2; |
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| 43 | [P0 + 0x2C] = R3; |
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| 44 | [P0 + 0x30] = R4; |
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| 45 | [P0 + 0x34] = R5; |
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| 46 | [P0 + 0x38] = R6; |
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| 47 | [P0 + 0x3C] = R7; |
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| 48 | |
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| 49 | R0 = ASTAT; |
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| 50 | [P0 + 0x40] = R0; |
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| 51 | |
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| 52 | R0 = LC0; /* Loop Counters */ |
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| 53 | [P0 + 0x44] = R0; |
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| 54 | R0 = LC1; |
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| 55 | [P0 + 0x48] = R0; |
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| 56 | |
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| 57 | R0 = A0.W; /* Accumulators */ |
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| 58 | [P0 + 0x4C] = R0; |
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| 59 | R0 = A0.X; |
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| 60 | [P0 + 0x50] = R0; |
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| 61 | R0 = A1.W; |
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| 62 | [P0 + 0x54] = R0; |
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| 63 | R0 = A1.X; |
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| 64 | [P0 + 0x58] = R0; |
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| 65 | |
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| 66 | R0 = I0; /* Index Registers */ |
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| 67 | [P0 + 0x5C] = R0; |
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| 68 | R0 = I1; |
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| 69 | [P0 + 0x60] = R0; |
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| 70 | R0 = I2; |
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| 71 | [P0 + 0x64] = R0; |
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| 72 | R0 = I3; |
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| 73 | [P0 + 0x68] = R0; |
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| 74 | |
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| 75 | R0 = M0; /* Modifier Registers */ |
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| 76 | [P0 + 0x6C] = R0; |
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| 77 | R0 = M1; |
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| 78 | [P0 + 0x70] = R0; |
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| 79 | R0 = M2; |
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| 80 | [P0 + 0x74] = R0; |
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| 81 | R0 = M3; |
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| 82 | [P0 + 0x78] = R0; |
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| 83 | |
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| 84 | R0 = L0; /* Length Registers */ |
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| 85 | [P0 + 0x7c] = R0; |
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| 86 | R0 = L1; |
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| 87 | [P0 + 0x80] = R0; |
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| 88 | R0 = L2; |
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| 89 | [P0 + 0x84] = R0; |
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| 90 | R0 = L3; |
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| 91 | [P0 + 0x88] = R0; |
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| 92 | |
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| 93 | R0 = B0; /* Base Registers */ |
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| 94 | [P0 + 0x8C] = R0; |
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| 95 | R0 = B1; |
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| 96 | [P0 + 0x90] = R0; |
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| 97 | R0 = B2; |
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| 98 | [P0 + 0x94] = R0; |
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| 99 | R0 = B3; |
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| 100 | [P0 + 0x98] = R0; |
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| 101 | |
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| 102 | R0 = RETS; |
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| 103 | [P0 + 0x9C] = R0; |
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| 104 | |
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| 105 | R0 = 0; |
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| 106 | |
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| 107 | RTS; |
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| 108 | .size _setjmp, .-_setjmp; |
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