| 1 | /* asm.h -- CR16 architecture intrinsic functions |
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| 2 | * |
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| 3 | * Copyright (c) 2012 National Semiconductor Corporation |
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| 4 | * |
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| 5 | * The authors hereby grant permission to use, copy, modify, distribute, |
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| 6 | * and license this software and its documentation for any purpose, provided |
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| 7 | * that existing copyright notices are retained in all copies and that this |
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| 8 | * notice is included verbatim in any distributions. No written agreement, |
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| 9 | * license, or royalty fee is required for any of the authorized uses. |
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| 10 | * Modifications to this software may be copyrighted by their authors |
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| 11 | * and need not follow the licensing terms described here, provided that |
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| 12 | * the new terms are clearly indicated on the first page of each file where |
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| 13 | * they apply. |
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| 14 | */ |
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| 15 | |
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| 16 | #ifndef _ASM |
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| 17 | #define _ASM |
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| 18 | |
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| 19 | /* Note that immediate input values are not checked for validity. It is |
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| 20 | the user's responsibility to use the intrinsic functions with appropriate |
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| 21 | immediate values. */ |
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| 22 | |
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| 23 | /* Addition Instructions */ |
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| 24 | #define _addb_(src, dest) __asm__("addb %1, %0" : "=r" (dest) : \ |
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| 25 | "ri" ((unsigned char)src), "0" (dest) : "cc") |
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| 26 | #define _addub_(src, dest) __asm__("addub %1, %0" : "=r" (dest) : \ |
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| 27 | "ri" ((unsigned char)src), "0" (dest) : "cc") |
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| 28 | #define _addw_(src, dest) __asm__("addw %1, %0" : "=r" (dest) : \ |
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| 29 | "ri" ((unsigned short)src), "0" (dest) : "cc") |
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| 30 | #define _adduw_(src, dest) __asm__("adduw %1, %0" : "=r" (dest) : \ |
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| 31 | "ri" ((unsigned short)src), "0" (dest) : "cc") |
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| 32 | #define _addd_(src, dest) __asm__("addd %1, %0" : "=r" (dest) : \ |
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| 33 | "ri" ((unsigned long)src), "0" (dest) : "cc") |
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| 34 | |
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| 35 | /* Add with Carry */ |
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| 36 | #define _addcb_(src, dest) __asm__("addcb %1, %0" : "=r" (dest) : \ |
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| 37 | "ri" ((unsigned char)src), "0" (dest) : "cc") |
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| 38 | #define _addcw_(src, dest) __asm__("addcw %1, %0" : "=r" (dest) : \ |
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| 39 | "ri" ((unsigned short)src), "0" (dest) : "cc") |
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| 40 | |
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| 41 | /* Bitwise Logical AND */ |
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| 42 | #define _andb_(src, dest) __asm__("andb %1,%0" : "=r" (dest) : \ |
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| 43 | "ri" ((unsigned char)src) , "0" (dest)) |
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| 44 | #define _andw_(src, dest) __asm__("andw %1,%0" : "=r" (dest) : \ |
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| 45 | "ri" ((unsigned short)src) , "0" (dest)) |
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| 46 | #define _andd_(src, dest) __asm__("andd %1,%0" : "=r" (dest) : \ |
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| 47 | "ri" ((unsigned long)src) , "0" (dest)) |
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| 48 | |
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| 49 | /* Arithmetic shift Instructions */ |
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| 50 | #define _ashub_(count, dest) __asm__("ashub %1,%0" : "=r" (dest) : \ |
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| 51 | "ri" ((char)count) , "0" (dest) ) |
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| 52 | #define _ashuw_(count, dest) __asm__("ashuw %1,%0" : "=r" (dest) : \ |
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| 53 | "ri" ((char)count) , "0" (dest) ) |
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| 54 | #define _ashud_(count, dest) __asm__("ashud %1,%0" : "=r" (dest) : \ |
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| 55 | "ri" ((char)count) , "0" (dest) ) |
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| 56 | |
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| 57 | /* cbit (clear bit) Instructions */ |
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| 58 | #define _cbitb_(pos, dest) __asm__("cbitb %1,%0" : "=mr" (dest) : \ |
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| 59 | "i" ((unsigned char)pos) , "0" (dest) : "cc") |
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| 60 | #define _cbitw_(pos, dest) __asm__("cbitw %1,%0" : "=mr" (dest) : \ |
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| 61 | "i" ((unsigned char)pos) , "0" (dest) : "cc") |
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| 62 | |
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| 63 | /* Compare Instructions */ |
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| 64 | #define _cmpb_(src1, src2) __asm__("cmpb %0,%1" : /* no output */ : \ |
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| 65 | "ri" ((unsigned char)src1) , "r" (src2) : "cc") |
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| 66 | #define _cmpw_(src1, src2) __asm__("cmpw %0,%1" : /* no output */ : \ |
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| 67 | "ri" ((unsigned short)src1) , "r" (src2) : "cc") |
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| 68 | #define _cmpd_(src1, src2) __asm__("cmpd %0,%1" : /* no output */ : \ |
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| 69 | "ri" ((unsigned long)src1) , "r" (src2) : "cc") |
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| 70 | |
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| 71 | /* Disable Inerrupts instructions */ |
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| 72 | #define _di_() __asm__ volatile ("di\n" : : : "cc") |
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| 73 | #define _disable_() __asm__ volatile ("di\n" : : : "cc") |
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| 74 | #define _disable_interrupt_() _di_ |
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| 75 | |
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| 76 | /* Enable Inerrupts instructions */ |
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| 77 | #define _ei_() __asm__ volatile ("ei\n" : : : "cc") |
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| 78 | #define _enable_() __asm__ volatile ("ei\n" : : : "cc") |
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| 79 | #define _enable_interrupt_() _ei_ |
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| 80 | |
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| 81 | /* Enable Inerrupts instructions and Wait */ |
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| 82 | #define _eiwait_() __asm__ volatile ("eiwait" : : : "cc") |
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| 83 | |
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| 84 | /* excp Instructions */ |
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| 85 | #define _excp_(vector) __asm__ volatile ("excp " # vector) |
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| 86 | |
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| 87 | /* lpr and lprd Instructions */ |
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| 88 | #define _lpr_(procreg, src) __asm__("lpr\t%0," procreg : \ |
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| 89 | /* no output */ : "r" (src) : "cc") |
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| 90 | #define _lprd_(procregd, src) __asm__("lprd\t%0," procregd : \ |
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| 91 | /* no output */ : "r" (src) : "cc") |
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| 92 | /* Left Shift Instructions */ |
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| 93 | #define _lshb_(count, dest) __asm__("lshb %1,%0" : "=r" (dest) : \ |
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| 94 | "ri" ((char)count) , "0" (dest) ) |
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| 95 | #define _lshw_(count, dest) __asm__("lshw %1,%0" : "=r" (dest) : \ |
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| 96 | "ri" ((char)count) , "0" (dest) ) |
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| 97 | #define _lshd_(count, dest) __asm__("lshd %1,%0" : "=r" (dest) : \ |
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| 98 | "ri" ((char)count) , "0" (dest) ) |
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| 99 | |
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| 100 | /* Load Instructions */ |
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| 101 | #define _loadb_(base, dest) __asm__("loadb %1,%0" : "=r" (dest) : \ |
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| 102 | "m" (base) , "0" (dest)) |
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| 103 | #define _loadw_(base, dest) __asm__("loadw %1,%0" : "=r" (dest) : \ |
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| 104 | "m" (base) , "0" (dest)) |
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| 105 | #define _loadd_(base, dest) __asm__("loadd %1,%0" : "=r" (dest) : \ |
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| 106 | "m" (base) , "0" (dest)) |
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| 107 | |
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| 108 | /* Load Multiple Instructions */ |
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| 109 | #define _loadm_(src, mask) __asm__("loadm %0,%1" : /* No output */ : \ |
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| 110 | "r" ((unsigned int)src) , "i" (mask)) |
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| 111 | #define _loadmp_(src, mask) __asm__("loadmp %0,%1" : /* No output */ : \ |
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| 112 | "r" ((unsigned int)src) , "i" (mask)) |
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| 113 | |
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| 114 | /* Multiply Accumulate Instrutions */ |
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| 115 | #define _macsw_(hi, lo, src1, src2) __asm__("macsw %1,%0" \ |
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| 116 | : =l (lo), =h (hi) \ |
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| 117 | : "r" ((short)src1) , "r" (src2)) |
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| 118 | #define _macuw_(hi, lo, src1, src2) __asm__("macuw %1,%0" \ |
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| 119 | : =l (lo), =h (hi) \ |
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| 120 | : "r" ((unsigned short)src1) , "r" (src2)) |
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| 121 | #define _macqw_(src1, src2) __asm__("macqw %1,%0" \ |
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| 122 | : =l (lo), =h (hi) \ |
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| 123 | :"r" ((short)src1) , "r" (src2)) |
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| 124 | |
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| 125 | /* Move Instructions */ |
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| 126 | #define _movb_(src, dest) __asm__("movb %1,%0" : "=r" (dest) : \ |
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| 127 | "ri" ((unsigned char)src) , "0" (dest)) |
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| 128 | #define _movw_(src, dest) __asm__("movw %1,%0" : "=r" (dest) : \ |
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| 129 | "ri" ((unsigned short)src) , "0" (dest)) |
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| 130 | #define _movd_(src, dest) __asm__("movd %1,%0" : "=r" (dest) : \ |
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| 131 | "ri" ((unsigned int)src) , "0" (dest)) |
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| 132 | #define _movxb_(src, dest) __asm__("movxb %1,%0" : "=r" (dest) : \ |
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| 133 | "r" (src), "0" (dest) ) |
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| 134 | #define _movzb_(src, dest) __asm__("movzb %1,%0" : "=r" (dest) : \ |
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| 135 | "r" (src), "0" (dest) ) |
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| 136 | #define _movxw_(src, dest) __asm__("movxw %1,%0" : "=r" (dest) : \ |
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| 137 | "r" (src), "0" (dest) ) |
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| 138 | #define _movzw_(src, dest) __asm__("movzw %1,%0" : "=r" (dest) : \ |
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| 139 | "r" (src), "0" (dest) ) |
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| 140 | |
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| 141 | /* Multiplication Instructions */ |
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| 142 | #define _mulb_(src, dest) __asm__("mulb %1,%0" : "=r" (dest) : \ |
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| 143 | "ri" ((char)src) , "0" (dest)) |
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| 144 | #define _mulw_(src, dest) __asm__("mulw %1,%0" : "=r" (dest) : \ |
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| 145 | "ri" ((short)src) , "0" (dest)) |
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| 146 | #define _mulsb_(src, dest) __asm__("mulsb %1,%0" : "=r" (dest) : \ |
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| 147 | "r" ((char)src) , "0" (dest)) |
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| 148 | #define _mulsw_(src, dest) __asm__("mulsw %1,%0" : "=r" (dest) : \ |
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| 149 | "r" ((short)src) , "0" (dest)) |
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| 150 | #define _muluw_(src, dest) __asm__("muluw %1,%0" : "=r" (dest) : \ |
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| 151 | "r" ((unsigned short)src) , "0" (dest)) |
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| 152 | |
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| 153 | /* nop Instruction */ |
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| 154 | #define _nop_() __asm__("nop") |
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| 155 | |
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| 156 | /* or Instructions */ |
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| 157 | #define _orb_(src, dest) __asm__("orb %1,%0" : "=r" (dest) : \ |
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| 158 | "ri" ((unsigned char)src) , "0" (dest)) |
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| 159 | #define _orw_(src, dest) __asm__("orw %1,%0" : "=r" (dest) : \ |
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| 160 | "ri" ((unsigned short)src) , "0" (dest)) |
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| 161 | #define _ord_(src, dest) __asm__("ord %1,%0" : "=r" (dest) : \ |
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| 162 | "ri" ((unsigned int)src) , "0" (dest)) |
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| 163 | |
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| 164 | /* retx Instruction */ |
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| 165 | #define _retx_() __asm__("retx") |
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| 166 | |
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| 167 | /* Set Bit Instructions */ |
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| 168 | #define _sbitb_(pos, dest) __asm__("sbitb %1,%0" : "=mr" (dest) : \ |
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| 169 | "i" ((unsigned char)pos) , "0" (dest) : "cc") |
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| 170 | #define _sbitw_(pos, dest) __asm__("sbitw %1,%0" : "=mr" (dest) : \ |
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| 171 | "i" ((unsigned char)pos) , "0" (dest) : "cc") |
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| 172 | |
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| 173 | /* spr and sprd Instructions */ |
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| 174 | #define _spr_(procreg, dest) __asm__("spr\t" procreg ",%0" : \ |
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| 175 | "=r" (dest) : /* no input */ "0" (dest) : "cc") |
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| 176 | #define _sprd_(procregd, dest) __asm__("sprd\t" procregd ",%0" : \ |
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| 177 | "=r" (dest) : /* no input */ "0" (dest) : "cc") |
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| 178 | |
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| 179 | /* Store Instructions */ |
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| 180 | #define _storb_(src, address) __asm__("storb %1,%0" : "=m" (address) : \ |
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| 181 | "ri" ((unsigned int)src)) |
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| 182 | #define _storw_(src, address) __asm__("storw %1,%0" : "=m" (address) : \ |
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| 183 | "ri" ((unsigned int)src)) |
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| 184 | #define _stord_(src, address) __asm__("stord %1,%0" : "=m" (address) : \ |
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| 185 | "ri" ((unsigned int)src)) |
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| 186 | |
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| 187 | /* Store Multiple Instructions */ |
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| 188 | #define _storm_(mask, src) __asm__("storm %1,%0" : /* No output here */ : \ |
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| 189 | "i" (mask) , "r" ((unsigned int)src)) |
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| 190 | #define _stormp_(mask, src) __asm__("stormp %1,%0" : /* No output here */ : \ |
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| 191 | "i" (mask) , "r" ((unsigned int)src)) |
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| 192 | |
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| 193 | /* Substruct Instructions */ |
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| 194 | #define _subb_(src, dest) __asm__("subb %1, %0" : "=r" (dest) : \ |
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| 195 | "ri" ((unsigned char)src), "0" (dest) : "cc") |
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| 196 | #define _subw_(src, dest) __asm__("subw %1, %0" : "=r" (dest) : \ |
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| 197 | "ri" ((unsigned short)src), "0" (dest) : "cc") |
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| 198 | #define _subd_(src, dest) __asm__("subd %1, %0" : "=r" (dest) : \ |
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| 199 | "ri" ((unsigned long)src), "0" (dest) : "cc") |
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| 200 | |
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| 201 | /* Substruct with Carry Instructions */ |
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| 202 | #define _subcb_(src, dest) __asm__("subcb %1, %0" : "=r" (dest) : \ |
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| 203 | "ri" ((unsigned char)src), "0" (dest) : "cc") |
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| 204 | #define _subcw_(src, dest) __asm__("subcw %1, %0" : "=r" (dest) : \ |
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| 205 | "ri" ((unsigned short)src), "0" (dest) : "cc") |
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| 206 | |
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| 207 | /* Test Bit Instructions */ |
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| 208 | #define _tbit_(offset, base) __asm__("tbit %0,%1" : /* no output */ : \ |
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| 209 | "ri" ((unsigned char)offset) , "r" (base) : "cc") |
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| 210 | #define _tbitb_(pos, dest) __asm__("tbitb %0,%1" : /* No output */ : \ |
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| 211 | "i" ((unsigned char)pos) , "m" (dest) : "cc") |
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| 212 | #define _tbitw_(pos, dest) __asm__("tbitw %0,%1" : /* No output */ : \ |
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| 213 | "i" ((unsigned char)pos) , "m" (dest) : "cc") |
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| 214 | |
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| 215 | /* wait Instruction*/ |
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| 216 | #define _wait_() __asm__ volatile ("wait" : : : "cc") |
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| 217 | |
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| 218 | /* xor Instructions */ |
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| 219 | #define _xorb_(src, dest) __asm__("xorb %1,%0" : "=r" (dest) : \ |
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| 220 | "ri" ((unsigned char)src) , "0" (dest)) |
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| 221 | #define _xorw_(src, dest) __asm__("xorw %1,%0" : "=r" (dest) : \ |
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| 222 | "ri" ((unsigned short)src) , "0" (dest)) |
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| 223 | #define _xord_(src, dest) __asm__("xord %1,%0" : "=r" (dest) : \ |
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| 224 | "ri" ((unsigned long)src) , "0" (dest)) |
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| 225 | |
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| 226 | #if !defined (__CR16C__) |
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| 227 | #define _di_() __asm__ volatile ("di\n" : : : "cc") |
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| 228 | #else |
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| 229 | /* In CR16C architecture the "nop" instruction is required after the di instruction |
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| 230 | in order to be sure the interrupts are indeed disabled. |
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| 231 | For details, refer the the CR16C Programmers Reference Manual. */ |
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| 232 | #define _di_() __asm__ volatile ("di\n\tnop" : : : "cc") |
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| 233 | #endif |
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| 234 | |
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| 235 | /* mtgpr Instruction */ |
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| 236 | #define _mtgpr_(src, gpr) \ |
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| 237 | __asm__ volatile ("movd\t%[_src], " gpr : /* no output */ \ |
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| 238 | : [_src] "ri" (src) \ |
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| 239 | : gpr ) |
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| 240 | |
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| 241 | /* mfgpr Instruction */ |
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| 242 | #define _mfgpr_(gpr, dest) \ |
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| 243 | __asm__ volatile ("movd\t" gpr ", %[_dest]" : [_dest] "=r" (dest) \ |
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| 244 | : /* no inputs */ ) |
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| 245 | |
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| 246 | /* set_i_bit Operation Definition */ |
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| 247 | #define set_i_bit() \ |
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| 248 | do \ |
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| 249 | { \ |
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| 250 | unsigned short tpsr; \ |
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| 251 | _spr_("psr", tpsr); \ |
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| 252 | tpsr |= 0x0800; \ |
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| 253 | _lpr_("psr",tpsr); \ |
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| 254 | } while(0) |
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| 255 | |
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| 256 | /* set_i_bit Macro Definition */ |
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| 257 | #define _enable_global_interrupt_ set_i_bit |
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| 258 | |
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| 259 | /* clear_i_bit Operation Definition */ |
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| 260 | #define clear_i_bit() \ |
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| 261 | do \ |
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| 262 | { \ |
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| 263 | unsigned short tpsr; \ |
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| 264 | _spr_("psr", tpsr); \ |
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| 265 | tpsr &= 0xf7ff; \ |
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| 266 | _lpr_("psr",tpsr); \ |
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| 267 | } while(0) |
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| 268 | |
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| 269 | /* clear_i_bit Macro Definition */ |
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| 270 | #define _disbale_global_interrupt_ clear_i_bit |
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| 271 | |
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| 272 | #define _save_asm_(x) \ |
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| 273 | __asm__ volatile (x ::: "memory","cc", \ |
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| 274 | "r0","r1","r2","r3","r4","r5","r6","r7", \ |
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| 275 | "r8","r9","r10","r11","r12","r13") |
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| 276 | |
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| 277 | #endif /* _ASM */ |
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| 278 | |
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| 279 | |
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| 280 | |
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