| 1 | /* A setjmp.c for CRIS |
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| 2 | Copyright (C) 1993-2005 Axis Communications. |
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| 3 | All rights reserved. |
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| 4 | |
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| 5 | Redistribution and use in source and binary forms, with or without |
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| 6 | modification, are permitted provided that the following conditions |
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| 7 | are met: |
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| 8 | |
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| 9 | 1. Redistributions of source code must retain the above copyright |
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| 10 | notice, this list of conditions and the following disclaimer. |
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| 11 | |
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| 12 | 2. Neither the name of Axis Communications nor the names of its |
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| 13 | contributors may be used to endorse or promote products derived |
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| 14 | from this software without specific prior written permission. |
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| 15 | |
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| 16 | THIS SOFTWARE IS PROVIDED BY AXIS COMMUNICATIONS AND ITS CONTRIBUTORS |
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| 17 | ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT |
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| 18 | LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR |
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| 19 | A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL AXIS |
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| 20 | COMMUNICATIONS OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT, |
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| 21 | INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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| 22 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR |
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| 23 | SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) |
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| 24 | HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, |
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| 25 | STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING |
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| 26 | IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 27 | POSSIBILITY OF SUCH DAMAGE. */ |
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| 28 | |
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| 29 | /* For benefit of CRIS v0..v3, we save and restore CCR to be able to |
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| 30 | correctly handle DI/EI; otherwise there would be no reason to save it. |
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| 31 | Note also that the "move x,ccr" does NOT affect |
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| 32 | the DMA enable bits (E and D) of v0..v3. |
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| 33 | |
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| 34 | We do not save mof; it is call-clobbered. It also does not exist in |
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| 35 | v0..v8; it should be safe to read or write to it there, but better not. |
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| 36 | |
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| 37 | jmp_buf[0] - PC |
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| 38 | jmp_buf[1] - SP (R14) |
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| 39 | jmp_buf[2] - R13 |
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| 40 | jmp_buf[3] - R12 |
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| 41 | jmp_buf[4] - R11 |
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| 42 | jmp_buf[5] - R10 |
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| 43 | jmp_buf[6] - R9 |
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| 44 | jmp_buf[7] - R8 |
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| 45 | jmp_buf[8] - R7 |
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| 46 | jmp_buf[9] - R6 |
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| 47 | jmp_buf[10] - R5 |
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| 48 | jmp_buf[11] - R4 |
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| 49 | jmp_buf[12] - R3 |
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| 50 | jmp_buf[13] - R2 |
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| 51 | jmp_buf[14] - R1 |
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| 52 | jmp_buf[15] - R0 |
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| 53 | jmp_buf[16] - SRP |
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| 54 | jmp_buf[17] - CCR |
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| 55 | */ |
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| 56 | |
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| 57 | #include <setjmp.h> |
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| 58 | |
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| 59 | int |
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| 60 | setjmp (jmp_buf buf) |
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| 61 | { |
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| 62 | int ret; |
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| 63 | #if defined (__arch_common_v10_v32) || defined (__arch_v32) |
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| 64 | /* No offsets in the compatibility mode. Also, movem saves in |
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| 65 | different order on v10 than on v32, so we use single move |
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| 66 | instructions instead, this not being a speed-prioritized operation. |
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| 67 | And we don't save CCR or CCS; since long unuseful. */ |
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| 68 | __asm__ __volatile__ |
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| 69 | ("move.d %1,$r13 \n\ |
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| 70 | move 0f,$mof \n\ |
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| 71 | move $mof,[$r13+] \n\ |
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| 72 | move.d $sp,[$r13+] \n\ |
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| 73 | clear.d [$r13+] \n\ |
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| 74 | move.d $r12,[$r13+] \n\ |
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| 75 | move.d $r11,[$r13+] \n\ |
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| 76 | move.d $r10,[$r13+] \n\ |
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| 77 | moveq 1,$r9 \n\ |
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| 78 | move.d $r9,[$r13+] \n\ |
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| 79 | move.d $r8,[$r13+] \n\ |
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| 80 | move.d $r7,[$r13+] \n\ |
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| 81 | move.d $r6,[$r13+] \n\ |
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| 82 | move.d $r5,[$r13+] \n\ |
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| 83 | move.d $r4,[$r13+] \n\ |
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| 84 | move.d $r3,[$r13+] \n\ |
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| 85 | move.d $r2,[$r13+] \n\ |
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| 86 | move.d $r1,[$r13+] \n\ |
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| 87 | move.d $r0,[$r13+] \n\ |
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| 88 | move $srp,[$r13+] \n\ |
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| 89 | clear.d [$r13+] \n\ |
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| 90 | clear.d $r9 \n\ |
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| 91 | 0: \n\ |
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| 92 | move.d $r9,%0" |
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| 93 | |
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| 94 | /* Output. */ |
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| 95 | : "=&r" (ret) |
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| 96 | |
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| 97 | /* Input. */ |
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| 98 | : "r" (buf) |
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| 99 | |
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| 100 | /* Clobber. */ |
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| 101 | : "r9", "r13", "memory"); |
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| 102 | #else /* not __arch_common_v10_v32 or __arch_v32 */ |
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| 103 | #ifdef __PIC__ |
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| 104 | __asm__ __volatile__ |
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| 105 | ("moveq 1,$r9 \n\ |
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| 106 | movem $sp,[%1+1*4] \n\ |
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| 107 | move.d $pc,$r9 \n\ |
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| 108 | addq 0f-.,$r9 \n\ |
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| 109 | move.d $r9,[%1] \n\ |
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| 110 | move $srp,[%1+16*4] \n\ |
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| 111 | move $ccr,[%1+17*4] \n\ |
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| 112 | clear.d $r9 \n\ |
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| 113 | 0: \n\ |
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| 114 | move.d $r9,%0" |
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| 115 | |
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| 116 | /* Output. */ |
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| 117 | : "=&r" (ret) |
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| 118 | |
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| 119 | /* Input. */ |
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| 120 | : "r" (buf) |
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| 121 | |
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| 122 | /* Clobber. */ |
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| 123 | : "r9", "memory"); |
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| 124 | #else /* not PIC */ |
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| 125 | __asm__ __volatile__ |
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| 126 | ("moveq 1,$r9 \n\ |
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| 127 | movem $sp,[%1+1*4] \n\ |
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| 128 | move.d 0f,$r9 \n\ |
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| 129 | move.d $r9,[%1] \n\ |
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| 130 | move $srp,[%1+16*4] \n\ |
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| 131 | move $ccr,[%1+17*4] \n\ |
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| 132 | clear.d $r9 \n\ |
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| 133 | 0: \n\ |
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| 134 | move.d $r9,%0" |
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| 135 | |
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| 136 | /* Output. */ |
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| 137 | : "=&r" (ret) |
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| 138 | |
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| 139 | /* Input. */ |
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| 140 | : "r" (buf) |
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| 141 | |
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| 142 | /* Clobber. */ |
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| 143 | : "r9"); |
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| 144 | #endif /* not PIC */ |
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| 145 | #endif /* not __arch_common_v10_v32 or __arch_v32 */ |
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| 146 | return ret; |
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| 147 | } |
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| 148 | |
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| 149 | void |
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| 150 | longjmp(jmp_buf buf, int val) |
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| 151 | { |
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| 152 | #if defined (__arch_common_v10_v32) || defined (__arch_v32) |
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| 153 | __asm__ __volatile__ |
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| 154 | ("cmpq 0,%1 \n\ |
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| 155 | beq 0f \n\ |
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| 156 | move.d %0,$r13 ; In delay-slot. \n\ |
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| 157 | addq 6*4,$r13 \n\ |
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| 158 | move.d %1,[$r13] \n\ |
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| 159 | subq 6*4,$r13 \n\ |
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| 160 | 0:\n" |
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| 161 | #ifdef __arch_common_v10_v32 |
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| 162 | /* Cater to branch offset difference between v32 and v10. We |
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| 163 | assume the branch above is 8-bit. */ |
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| 164 | " setf\n" |
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| 165 | #endif |
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| 166 | " move [$r13+],$mof \n\ |
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| 167 | move.d [$r13+],$sp \n\ |
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| 168 | addq 4,$r13 \n\ |
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| 169 | move.d [$r13+],$r12 \n\ |
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| 170 | move.d [$r13+],$r11 \n\ |
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| 171 | move.d [$r13+],$r10 \n\ |
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| 172 | move.d [$r13+],$r9 \n\ |
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| 173 | move.d [$r13+],$r8 \n\ |
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| 174 | move.d [$r13+],$r7 \n\ |
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| 175 | move.d [$r13+],$r6 \n\ |
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| 176 | move.d [$r13+],$r5 \n\ |
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| 177 | move.d [$r13+],$r4 \n\ |
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| 178 | move.d [$r13+],$r3 \n\ |
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| 179 | move.d [$r13+],$r2 \n\ |
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| 180 | move.d [$r13+],$r1 \n\ |
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| 181 | move.d [$r13+],$r0 \n\ |
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| 182 | move [$r13+],$srp \n\ |
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| 183 | move $mof,$r13 \n\ |
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| 184 | jump $r13 \n\ |
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| 185 | setf" |
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| 186 | |
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| 187 | /* No outputs. */ |
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| 188 | : |
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| 189 | |
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| 190 | /* Inputs. */ |
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| 191 | : "r" (buf), "r" (val) |
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| 192 | : "r13", "memory"); |
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| 193 | |
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| 194 | #else /* not __arch_common_v10_v32 or __arch_v32 */ |
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| 195 | __asm__ __volatile__ |
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| 196 | ("move [%0+17*4],$ccr \n\ |
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| 197 | move [%0+16*4],$srp \n\ |
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| 198 | test.d %1 \n\ |
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| 199 | beq 0f \n\ |
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| 200 | nop \n\ |
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| 201 | move.d %1,[%0+6*4] ; Offset for r9. \n\ |
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| 202 | 0: \n\ |
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| 203 | movem [%0],$pc" |
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| 204 | |
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| 205 | /* No outputs. */ |
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| 206 | : |
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| 207 | |
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| 208 | /* Inputs. */ |
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| 209 | : "r" (buf), "r" (val) |
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| 210 | : "memory"); |
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| 211 | #endif /* not __arch_common_v10_v32 or __arch_v32 */ |
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| 212 | } |
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