1 | /* asm.h -- CRX architecture intrinsic functions |
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2 | * |
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3 | * Copyright (c) 2004 National Semiconductor Corporation |
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4 | * |
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5 | * The authors hereby grant permission to use, copy, modify, distribute, |
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6 | * and license this software and its documentation for any purpose, provided |
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7 | * that existing copyright notices are retained in all copies and that this |
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8 | * notice is included verbatim in any distributions. No written agreement, |
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9 | * license, or royalty fee is required for any of the authorized uses. |
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10 | * Modifications to this software may be copyrighted by their authors |
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11 | * and need not follow the licensing terms described here, provided that |
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12 | * the new terms are clearly indicated on the first page of each file where |
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13 | * they apply. |
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14 | */ |
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15 | |
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16 | #ifndef _ASM |
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17 | #define _ASM |
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18 | |
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19 | /* Note that immediate input values are not checked for validity. It is |
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20 | the user's responsibility to use the intrinsic functions with appropriate |
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21 | immediate values. */ |
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22 | |
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23 | /* Absolute Instructions */ |
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24 | #define _absb_(src, dest) __asm__("absb %1, %0" : "=r" (dest) : \ |
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25 | "r" ((char)src) , "0" (dest)) |
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26 | #define _absw_(src, dest) __asm__("absw %1,%0" : "=r" (dest) : \ |
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27 | "r" ((short)src) , "0" (dest)) |
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28 | #define _absd_(src, dest) __asm__("absd %1, %0" : "=r" (dest) : \ |
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29 | "r" ((int)src) , "0" (dest)) |
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30 | |
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31 | /* Addition Instructions */ |
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32 | #define _addb_(src, dest) __asm__("addb %1, %0" : "=r" (dest) : \ |
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33 | "ri" ((unsigned char)src), "0" (dest) : "cc") |
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34 | #define _addub_(src, dest) __asm__("addub %1, %0" : "=r" (dest) : \ |
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35 | "ri" ((unsigned char)src), "0" (dest) : "cc") |
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36 | #define _addw_(src, dest) __asm__("addw %1, %0" : "=r" (dest) : \ |
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37 | "ri" ((unsigned short)src), "0" (dest) : "cc") |
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38 | #define _adduw_(src, dest) __asm__("adduw %1, %0" : "=r" (dest) : \ |
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39 | "ri" ((unsigned short)src), "0" (dest) : "cc") |
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40 | #define _addd_(src, dest) __asm__("addd %1, %0" : "=r" (dest) : \ |
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41 | "ri" ((unsigned int)src), "0" (dest) : "cc") |
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42 | #define _addud_(src, dest) __asm__("addud %1, %0" : "=r" (dest) : \ |
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43 | "ri" ((unsigned int)src), "0" (dest) : "cc") |
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44 | /* Add with Carry */ |
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45 | #define _addcb_(src, dest) __asm__("addcb %1, %0" : "=r" (dest) : \ |
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46 | "ri" ((unsigned char)src), "0" (dest) : "cc") |
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47 | #define _addcw_(src, dest) __asm__("addcw %1, %0" : "=r" (dest) : \ |
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48 | "ri" ((unsigned short)src), "0" (dest) : "cc") |
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49 | #define _addcd_(src, dest) __asm__("addcd %1, %0" : "=r" (dest) : \ |
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50 | "ri" ((unsigned int)src), "0" (dest) : "cc") |
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51 | /* Q-format Add */ |
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52 | #define _addqb_(src, dest) __asm__("addqb %1, %0" : "=r" (dest) : \ |
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53 | "r" ((unsigned char)src), "0" (dest) : "cc") |
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54 | #define _addqw_(src, dest) __asm__("addqw %1, %0" : "=r" (dest) : \ |
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55 | "r" ((unsigned short)src), "0" (dest) : "cc") |
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56 | #define _addqd_(src, dest) __asm__("addqd %1, %0" : "=r" (dest) : \ |
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57 | "r" ((unsigned int)src), "0" (dest) : "cc") |
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58 | |
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59 | /* Bitwise Logical AND */ |
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60 | |
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61 | #define _andb_(src, dest) __asm__("andb %1,%0" : "=r" (dest) : \ |
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62 | "ri" ((unsigned char)src) , "0" (dest)) |
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63 | #define _andw_(src, dest) __asm__("andw %1,%0" : "=r" (dest) : \ |
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64 | "ri" ((unsigned short)src) , "0" (dest)) |
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65 | #define _andd_(src, dest) __asm__("andd %1,%0" : "=r" (dest) : \ |
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66 | "ri" ((unsigned int)src) , "0" (dest)) |
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67 | |
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68 | /* bswap Instruction */ |
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69 | #define _bswap_(src, dest) __asm__("bswap %1,%0" : "=r" (dest) : \ |
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70 | "r" ((unsigned int)src) , "0" (dest)) |
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71 | /* cbit (clear bit) Instructions */ |
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72 | #define _cbitb_(pos, dest) __asm__("cbitb %1,%0" : "=mr" (dest) : \ |
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73 | "i" ((unsigned char)pos) , "0" (dest) : "cc") |
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74 | #define _cbitw_(pos, dest) __asm__("cbitw %1,%0" : "=mr" (dest) : \ |
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75 | "i" ((unsigned char)pos) , "0" (dest) : "cc") |
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76 | #define _cbitd_(pos, dest) __asm__("cbitd %1,%0" : "=r" (dest) : \ |
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77 | "i" ((unsigned char)pos) , "0" (dest) : "cc") |
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78 | |
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79 | /* Compare Instructions */ |
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80 | #define _cmpb_(src1, src2) __asm__("cmpb %0,%1" : /* no output */ : \ |
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81 | "ri" ((unsigned char)src1) , "r" (src2) : "cc") |
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82 | #define _cmpw_(src1,src2) __asm__("cmpw %0,%1" : /* no output */ \ |
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83 | : "ri" ((unsigned short)src1) , "r" (src2) : "cc") |
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84 | #define _cmpd_(src1,src2) __asm__("cmpd %0,%1" : /* no output */ \ |
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85 | : "ri" ((unsigned int)src1) , "r" (src2) : "cc") |
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86 | |
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87 | /* cntl Count Leading Ones Instructions */ |
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88 | #define _cntl1b_(src, dest) __asm__("cntl1b %1,%0" : "=r" (dest) : \ |
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89 | "r" ((char)src) , "0" (dest)) |
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90 | #define _cntl1w_(src, dest) __asm__("cntl1w %1,%0" : "=r" (dest) : \ |
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91 | "r" ((short)src) , "0" (dest)) |
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92 | #define _cntl1d_(src, dest) __asm__("cntl1d %1,%0" : "=r" (dest) : \ |
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93 | "r" ((int)src) , "0" (dest)) |
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94 | |
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95 | /* cntl Count Leading Zeros Instructions */ |
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96 | #define _cntl0b_(src, dest) __asm__("cntl0b %1,%0" : "=r" (dest) : \ |
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97 | "r" ((char)src) , "0" (dest)) |
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98 | #define _cntl0w_(src, dest) __asm__("cntl0w %1,%0" : "=r" (dest) : \ |
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99 | "r" ((short)src) , "0" (dest)) |
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100 | #define _cntl0d_(src, dest) __asm__("cntl0d %1,%0" : "=r" (dest) : \ |
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101 | "r" ((int)src) , "0" (dest)) |
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102 | |
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103 | /* cntl Count Leading Signs Instructions */ |
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104 | #define _cntlsb_(src, dest) __asm__("cntlsb %1,%0" : "=r" (dest) : \ |
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105 | "r" ((char)src) , "0" (dest)) |
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106 | #define _cntlsw_(src, dest) __asm__("cntlsw %1,%0" : "=r" (dest) : \ |
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107 | "r" ((short)src) , "0" (dest)) |
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108 | #define _cntlsd_(src, dest) __asm__("cntlsd %1,%0" : "=r" (dest) : \ |
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109 | "r" ((int)src) , "0" (dest)) |
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110 | |
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111 | /* Disable Inerrupts instructions */ |
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112 | #define _di_() __asm__ volatile ("di\n" : : : "cc") |
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113 | #define _disable_() __asm__ volatile ("di\n" : : : "cc") |
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114 | |
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115 | /* Enable Inerrupts instructions */ |
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116 | #define _ei_() __asm__ volatile ("ei\n" : : : "cc") |
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117 | #define _enable_() __asm__ volatile ("ei\n" : : : "cc") |
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118 | |
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119 | /* Enable Inerrupts instructions and Wait */ |
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120 | #define _eiwait_() __asm__ volatile ("eiwait" : : : "cc") |
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121 | |
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122 | /* excp Instructions */ |
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123 | #define _excp_(vector) __asm__ volatile ("excp " # vector) |
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124 | |
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125 | /* getpid Instruction */ |
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126 | #define _getrfid_(dest) __asm__("getrfid %0" : "=r" (dest) : \ |
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127 | /* No input */ : "cc") |
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128 | |
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129 | /* Load Instructions */ |
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130 | #define _loadb_(base,dest) __asm__("loadb %1,%0" : "=r" (dest) : \ |
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131 | "m" (base) , "0" (dest)) |
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132 | #define _loadw_(base,dest) __asm__("loadw %1,%0" : "=r" (dest) : \ |
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133 | "m" (base) , "0" (dest)) |
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134 | #define _loadd_(base,dest) __asm__("loadd %1,%0" : "=r" (dest) : \ |
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135 | "m" (base) , "0" (dest)) |
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136 | |
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137 | /* Load Multiple Instructions */ |
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138 | #define _loadm_(src, mask) __asm__("loadm %0,%1" : /* No output */ : \ |
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139 | "r" ((unsigned int)src) , "i" (mask)) |
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140 | #define _loadmp_(src, mask) __asm__("loadmp %0,%1" : /* No output */ : \ |
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141 | "r" ((unsigned int)src) , "i" (mask)) |
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142 | |
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143 | /* Multiply Accumulate Instrutions */ |
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144 | #define _macsb_(hi, lo, src1, src2) __asm__("macsb %1,%0" \ |
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145 | : =l (lo), =h (hi) \ |
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146 | : "r" ((char)src1) , "r" (src2)) |
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147 | #define _macsw_(hi, lo, src1, src2) __asm__("macsw %1,%0" \ |
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148 | : =l (lo), =h (hi) \ |
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149 | : "r" ((short)src1) , "r" (src2)) |
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150 | #define _macsd_(hi, lo, src1, src2) __asm__("macsd %1,%0" \ |
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151 | : =l (lo), =h (hi) \ |
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152 | : "r" ((int)src1) , "r" (src2)) |
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153 | #define _macub_(hi, lo, src1, src2) __asm__("macub %1,%0" \ |
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154 | : =l (lo), =h (hi) \ |
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155 | :"r" ((unsigned char)src1) , "r" (src2)) |
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156 | #define _macuw_(hi, lo, src1, src2) __asm__("macuw %1,%0" \ |
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157 | : =l (lo), =h (hi) \ |
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158 | : "r" ((unsigned short)src1) , "r" (src2)) |
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159 | #define _macud_(hi, lo, src1, src2) __asm__("macud %1,%0" \ |
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160 | : =l (lo), =h (hi) \ |
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161 | : "r" ((unsigned int)src1) , "r" (src2)) |
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162 | |
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163 | /* Q-Format Multiply Accumulate Instrutions */ |
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164 | #define _macqb_(src1, src2) __asm__("macqb %1,%0" \ |
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165 | : =l (lo), =h (hi) \ |
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166 | :"r" ((char)src1) , "r" (src2)) |
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167 | #define _macqw_(src1, src2) __asm__("macqw %1,%0" \ |
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168 | : =l (lo), =h (hi) \ |
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169 | :"r" ((short)src1) , "r" (src2)) |
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170 | #define _macqd_(src1, src2) __asm__("macqd %1,%0" \ |
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171 | : =l (lo), =h (hi) \ |
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172 | :"r" ((int)src1) , "r" (src2)) |
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173 | |
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174 | /* Maximum Instructions */ |
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175 | #define _maxsb_(src, dest) __asm__("maxsb %1,%0" : "=r" (dest) : \ |
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176 | "r" ((char)src) , "0" (dest)) |
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177 | #define _maxsw_(src, dest) __asm__("maxsw %1,%0" : "=r" (dest) : \ |
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178 | "r" ((short)src) , "0" (dest)) |
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179 | #define _maxsd_(src, dest) __asm__("maxsd %1,%0" : "=r" (dest) : \ |
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180 | "r" ((int)src) , "0" (dest)) |
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181 | #define _maxub_(src, dest) __asm__("maxub %1,%0" : "=r" (dest) : \ |
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182 | "r" ((unsigned char)src) , "0" (dest)) |
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183 | #define _maxuw_(src, dest) __asm__("maxuw %1,%0" : "=r" (dest) : \ |
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184 | "r" ((unsigned short)src) , "0" (dest)) |
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185 | #define _maxud_(src, dest) __asm__("maxud %1,%0" : "=r" (dest) : \ |
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186 | "r" ((unsigned int)src) , "0" (dest)) |
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187 | |
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188 | /* Minimum Instructions */ |
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189 | #define _minsb_(src, dest) __asm__("minsb %1,%0" : "=r" (dest) : \ |
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190 | "r" ((char)src) , "0" (dest)) |
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191 | #define _minsw_(src, dest) __asm__("minsw %1,%0" : "=r" (dest) : \ |
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192 | "r" ((short)src) , "0" (dest)) |
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193 | #define _minsd_(src, dest) __asm__("minsd %1,%0" : "=r" (dest) : \ |
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194 | "r" ((int)src) , "0" (dest)) |
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195 | #define _minub_(src, dest) __asm__("minub %1,%0" : "=r" (dest) : \ |
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196 | "r" ((unsigned char)src) , "0" (dest)) |
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197 | #define _minuw_(src, dest) __asm__("minuw %1,%0" : "=r" (dest) : \ |
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198 | "r" ((unsigned short)src) , "0" (dest)) |
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199 | #define _minud_(src, dest) __asm__("minud %1,%0" : "=r" (dest) : \ |
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200 | "r" ((unsigned int)src) , "0" (dest)) |
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201 | |
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202 | /* Move Instructions */ |
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203 | #define _movb_(src, dest) __asm__("movb %1,%0" : "=r" (dest) : \ |
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204 | "ri" ((unsigned char)src) , "0" (dest)) |
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205 | #define _movw_(src, dest) __asm__("movw %1,%0" : "=r" (dest) : \ |
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206 | "ri" ((unsigned short)src) , "0" (dest)) |
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207 | #define _movd_(src, dest) __asm__("movd %1,%0" : "=r" (dest) : \ |
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208 | "ri" ((unsigned int)src) , "0" (dest)) |
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209 | |
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210 | /* mtpr and mfpr Insturctions */ |
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211 | #define _mtpr_(procregd, src) __asm__("mtpr\t%0," procregd : /* no output */ : \ |
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212 | "r" (src) : "cc") |
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213 | #define _mfpr_(procregd, dest) __asm__("mfpr\t" procregd ",%0" : "=r" (dest) : \ |
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214 | /* no input */ "0" (dest) : "cc") |
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215 | |
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216 | /* Multiplication Instructions */ |
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217 | #define _mulsbw_(src, dest) __asm__("mulsbw %1,%0" : "=r" (dest) : \ |
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218 | "r" ((char)src) , "0" (dest)) |
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219 | #define _mulubw_(src, dest) __asm__("mulubw %1,%0" : "=r" (dest) : \ |
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220 | "r" ((unsigned char)src) , "0" (dest)) |
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221 | #define _mulswd_(src, dest) __asm__("mulswd %1,%0" : "=r" (dest) : \ |
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222 | "r" ((short)src) , "0" (dest)) |
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223 | #define _muluwd_(src, dest) __asm__("muluwd %1,%0" : "=r" (dest) : \ |
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224 | "r" ((unsigned short)src) , "0" (dest)) |
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225 | #define _mulb_(src, dest) __asm__("mulb %1,%0" : "=r" (dest) : \ |
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226 | "ri" ((char)src) , "0" (dest)) |
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227 | #define _mulw_(src, dest) __asm__("mulw %1,%0" : "=r" (dest) : \ |
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228 | "ri" ((short)src) , "0" (dest)) |
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229 | #define _muld_(src, dest) __asm__("muld %1,%0" : "=r" (dest) : \ |
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230 | "ri" ((int)src) , "0" (dest)) |
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231 | #define _mullsd_(hi, lo, src1, src2) __asm__("mullsd %2,%3" \ |
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232 | : =l (lo), =h (hi) \ |
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233 | : "r" ((unsigned int)src1) , "r" ((unsigned int)src2)) |
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234 | #define _mullud_(hi, lo, src1, src2) __asm__("mullud %2,%3" \ |
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235 | : =l (lo), =h (hi) \ |
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236 | : "r" ((int)src1) , "r" ((int)src2)) |
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237 | |
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238 | /* Q-Format Multiplication Instructions */ |
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239 | #define _mulqb_(src, dest) __asm__("mulqb %1,%0" : "=r" (dest) : \ |
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240 | "r" ((char)src) , "0" (dest)) |
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241 | #define _mulqw_(src, dest) __asm__("mulqw %1,%0" : "=r" (dest) : \ |
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242 | "r" ((short)src) , "0" (dest)) |
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243 | |
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244 | /* nop Instruction */ |
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245 | #define _nop_() __asm__("nop") |
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246 | |
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247 | /* Negate Instructions */ |
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248 | #define _negb_(src, dest) __asm__("negb %1,%0" : "=r" (dest) : \ |
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249 | "r" ((char)src) , "0" (dest)) |
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250 | #define _negw_(src, dest) __asm__("negw %1,%0" : "=r" (dest) : \ |
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251 | "r" ((short)src) , "0" (dest)) |
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252 | #define _negd_(src, dest) __asm__("negd %1,%0" : "=r" (dest) : \ |
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253 | "r" ((int)src) , "0" (dest)) |
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254 | |
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255 | /* or Instructions */ |
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256 | #define _orb_(src, dest) __asm__("orb %1,%0" : "=r" (dest) : \ |
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257 | "ri" ((unsigned char)src) , "0" (dest)) |
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258 | #define _orw_(src, dest) __asm__("orw %1,%0" : "=r" (dest) : \ |
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259 | "ri" ((unsigned short)src) , "0" (dest)) |
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260 | #define _ord_(src, dest) __asm__("ord %1,%0" : "=r" (dest) : \ |
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261 | "ri" ((unsigned int)src) , "0" (dest)) |
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262 | |
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263 | /* Pop 1's Count Instructions */ |
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264 | #define _popcntb_(src, dest) __asm__("popcntb %1,%0" : "=r" (dest) : \ |
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265 | "r" ((char)src) , "0" (dest)) |
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266 | #define _popcntw_(src, dest) __asm__("popcntw %1,%0" : "=r" (dest) : \ |
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267 | "r" ((short)src) , "0" (dest)) |
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268 | #define _popcntd_(src, dest) __asm__("popcntd %1,%0" : "=r" (dest) : \ |
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269 | "r" ((int)src) , "0" (dest)) |
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270 | |
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271 | /* Rotate and Mask Instructions */ |
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272 | #define _ram_(shift, end, begin, dest, src) __asm__("ram %1, %2, %3, %0, %4" : \ |
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273 | "=r" (dest) : \ |
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274 | "i" ((unsigned char) shift), \ |
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275 | "i" (end), "i" (begin), \ |
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276 | "r" (src), "0" (dest)) |
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277 | #define _rim_(shift, end, begin, dest, src) __asm__("rim %1, %2, %3, %0, %4" : \ |
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278 | "=r" (dest) : \ |
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279 | "i" ((unsigned char) shift), \ |
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280 | "i" (end), "i" (begin), \ |
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281 | "r" (src), "0" (dest)) |
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282 | |
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283 | /* retx Instruction */ |
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284 | #define _retx_() __asm__("retx") |
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285 | |
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286 | /* Rotate Instructions */ |
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287 | #define _rotb_(shift, dest) __asm__("rotb %1,%0" : "=r" (dest) : \ |
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288 | "i" ((unsigned char)shift) , "0" (dest)) |
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289 | #define _rotw_(shift, dest) __asm__("rotw %1,%0" : "=r" (dest) : \ |
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290 | "i" ((unsigned char)shift) , "0" (dest)) |
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291 | #define _rotd_(shift, dest) __asm__("rotd %1,%0" : "=r" (dest) : \ |
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292 | "i" ((unsigned char)shift) , "0" (dest)) |
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293 | #define _rotlb_(shift, dest) __asm__("rotlb %1,%0" : "=r" (dest) : \ |
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294 | "r" ((unsigned char)shift) , "0" (dest)) |
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295 | #define _rotlw_(shift, dest) __asm__("rotlw %1,%0" : "=r" (dest) : \ |
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296 | "r" ((unsigned char)shift) , "0" (dest)) |
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297 | #define _rotld_(shift, dest) __asm__("rotld %1,%0" : "=r" (dest) : \ |
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298 | "r" ((unsigned char)shift) , "0" (dest)) |
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299 | #define _rotrb_(shift, dest) __asm__("rotrb %1,%0" : "=r" (dest) : \ |
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300 | "r" ((unsigned char)shift) , "0" (dest)) |
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301 | #define _rotrw_(shift, dest) __asm__("rotrw %1,%0" : "=r" (dest) : \ |
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302 | "r" ((unsigned char)shift) , "0" (dest)) |
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303 | #define _rotrd_(shift, dest) __asm__("rotrd %1,%0" : "=r" (dest) : \ |
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304 | "r" ((unsigned char)shift) , "0" (dest)) |
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305 | |
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306 | /* Set Bit Instructions */ |
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307 | #define _sbitb_(pos,dest) __asm__("sbitb %1,%0" : "=mr" (dest) : \ |
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308 | "i" ((unsigned char)pos) , "0" (dest) : "cc") |
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309 | #define _sbitw_(pos,dest) __asm__("sbitw %1,%0" : "=mr" (dest) : \ |
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310 | "i" ((unsigned char)pos) , "0" (dest) : "cc") |
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311 | #define _sbitd_(pos,dest) __asm__("sbitd %1,%0" : "=mr" (dest) : \ |
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312 | "i" ((unsigned char)pos) , "0" (dest) : "cc") |
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313 | |
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314 | /* setrfid Instruction */ |
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315 | #define _setrfid_(src) __asm__("setrfid %0" : /* No output */ : \ |
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316 | "r" (src) : "cc") |
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317 | |
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318 | /* Sign Extend Instructions */ |
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319 | #define _sextbw_(src, dest) __asm__("sextbw %1,%0" : "=r" (dest) : \ |
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320 | "r" ((char)src) , "0" (dest) ) |
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321 | #define _sextbd_(src, dest) __asm__("sextbd %1,%0" : "=r" (dest) : \ |
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322 | "r" ((char)src) , "0" (dest) ) |
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323 | #define _sextwd_(src, dest) __asm__("sextwd %1,%0" : "=r" (dest) : \ |
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324 | "r" ((short)src) , "0" (dest) ) |
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325 | |
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326 | /* Shift Left Logical Instructions */ |
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327 | #define _sllb_(src, dest) __asm__("sllb %1,%0" : "=r" (dest) : \ |
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328 | "ri" ((unsigned char)src) , "0" (dest)) |
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329 | #define _sllw_(src, dest) __asm__("sllw %1,%0" : "=r" (dest) : \ |
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330 | "ri" ((unsigned char)src) , "0" (dest)) |
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331 | #define _slld_(src, dest) __asm__("slld %1,%0" : "=r" (dest) : \ |
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332 | "ri" ((unsigned char)src) , "0" (dest)) |
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333 | /* Shift Right Arithmetic Instructions */ |
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334 | #define _srab_(src, dest) __asm__("srab %1,%0" : "=r" (dest) : \ |
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335 | "ri" ((unsigned char)src) , "0" (dest)) |
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336 | #define _sraw_(src, dest) __asm__("sraw %1,%0" : "=r" (dest) : \ |
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337 | "ri" ((unsigned char)src) , "0" (dest)) |
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338 | #define _srad_(src, dest) __asm__("srad %1,%0" : "=r" (dest) : \ |
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339 | "ri" ((unsigned char)src) , "0" (dest)) |
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340 | |
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341 | /* Shift Right Logical Instructions */ |
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342 | #define _srlb_(src, dest) __asm__("srlb %1,%0" : "=r" (dest) : \ |
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343 | "ri" ((unsigned char)src) , "0" (dest)) |
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344 | #define _srlw_(src, dest) __asm__("srlw %1,%0" : "=r" (dest) : \ |
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345 | "ri" ((unsigned char)src) , "0" (dest)) |
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346 | #define _srld_(src, dest) __asm__("srld %1,%0" : "=r" (dest) : \ |
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347 | "ri" ((unsigned char)src) , "0" (dest)) |
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348 | |
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349 | /* Store Instructions */ |
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350 | #define _storb_(src,address) __asm__("storb %1,%0" : "=m" (address) : \ |
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351 | "ri" ((unsigned int)src)) |
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352 | #define _storw_(src,address) __asm__("storw %1,%0" : "=m" (address) : \ |
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353 | "ri" ((unsigned int)src)) |
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354 | #define _stord_(src,address) __asm__("stord %1,%0" : "=m" (address) : \ |
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355 | "ri" ((unsigned int)src)) |
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356 | |
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357 | /* Store Multiple Instructions */ |
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358 | #define _storm_(mask, src) __asm__("storm %1,%0" : /* No output here */ : \ |
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359 | "i" (mask) , "r" ((unsigned int)src)) |
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360 | #define _stormp_(mask, src) __asm__("stormp %1,%0" : /* No output here */ : \ |
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361 | "i" (mask) , "r" ((unsigned int)src)) |
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362 | |
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363 | /* Substruct Instructions */ |
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364 | #define _subb_(src, dest) __asm__("subb %1, %0" : "=r" (dest) : \ |
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365 | "ri" ((unsigned char)src), "0" (dest) : "cc") |
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366 | #define _subw_(src, dest) __asm__("subw %1, %0" : "=r" (dest) : \ |
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367 | "ri" ((unsigned short)src), "0" (dest) : "cc") |
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368 | #define _subd_(src, dest) __asm__("subd %1, %0" : "=r" (dest) : \ |
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369 | "ri" ((unsigned int)src), "0" (dest) : "cc") |
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370 | |
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371 | /* Substruct with Carry Instructions */ |
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372 | #define _subcb_(src, dest) __asm__("subcb %1, %0" : "=r" (dest) : \ |
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373 | "ri" ((unsigned char)src), "0" (dest) : "cc") |
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374 | #define _subcw_(src, dest) __asm__("subcw %1, %0" : "=r" (dest) : \ |
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375 | "ri" ((unsigned short)src), "0" (dest) : "cc") |
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376 | #define _subcd_(src, dest) __asm__("subcd %1, %0" : "=r" (dest) : \ |
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377 | "ri" ((unsigned int)src), "0" (dest) : "cc") |
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378 | |
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379 | /* Q-Format Substruct Instructions */ |
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380 | #define _subqb_(src, dest) __asm__("subqw %1,%0" : "=r" (dest) : \ |
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381 | "r" ((char)src) , "0" (dest)) |
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382 | #define _subqw_(src, dest) __asm__("subqw %1,%0" : "=r" (dest) : \ |
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383 | "r" ((short)src) , "0" (dest)) |
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384 | #define _subqd_(src, dest) __asm__("subqd %1,%0" : "=r" (dest) : \ |
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385 | "r" ((short)src) , "0" (dest)) |
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386 | |
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387 | /* Test Bit Instructions */ |
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388 | #define _tbitb_(pos,dest) __asm__("tbitb %0,%1" : /* No output */ : \ |
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389 | "i" ((unsigned char)pos) , "rm" (dest) : "cc") |
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390 | #define _tbitw_(pos,dest) __asm__("tbitw %0,%1" : /* No output */ : \ |
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391 | "i" ((unsigned char)pos) , "rm" (dest) : "cc") |
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392 | #define _tbitd_(pos,dest) __asm__("tbitd %0,%1" : /* No output */ : \ |
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393 | "i" ((unsigned char)pos) , "rm" (dest) : "cc") |
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394 | |
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395 | /* wait Instruction*/ |
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396 | #define _wait_() __asm__ volatile ("wait" : : : "cc") |
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397 | |
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398 | /* xor Instructions */ |
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399 | #define _xorb_(src, dest) __asm__("xorb %1,%0" : "=r" (dest) : \ |
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400 | "ri" ((unsigned char)src) , "0" (dest)) |
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401 | #define _xorw_(src, dest) __asm__("xorw %1,%0" : "=r" (dest) : \ |
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402 | "ri" ((unsigned short)src) , "0" (dest)) |
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403 | #define _xord_(src, dest) __asm__("xord %1,%0" : "=r" (dest) : \ |
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404 | "ri" ((unsigned int)src) , "0" (dest)) |
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405 | |
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406 | /* Zero Extend Instructions */ |
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407 | #define _zextbw_(src, dest) __asm__("zextbw %1,%0" : "=r" (dest) : \ |
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408 | "r" ((unsigned char)src) , "0" (dest)) |
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409 | #define _zextbd_(src, dest) __asm__("zextbd %1,%0" : "=r" (dest) : \ |
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410 | "r" ((unsigned char)src) , "0" (dest)) |
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411 | #define _zextwd_(src, dest) __asm__("zextwd %1,%0" : "=r" (dest) : \ |
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412 | "r" ((unsigned short)src) , "0" (dest)) |
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413 | |
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414 | #define _save_asm_(x) \ |
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415 | __asm__ volatile (x ::: "memory","cc", \ |
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416 | "r0","r1","r2","r3","r4","r5","r6","r7", \ |
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417 | "r8","r9","r10","r11","r12","r13") |
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418 | |
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419 | #endif /* _ASM */ |
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420 | |
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421 | |
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