1 | /* |
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2 | Copyright (c) 2013 Andes Technology Corporation. |
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3 | All rights reserved. |
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4 | |
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5 | Redistribution and use in source and binary forms, with or without |
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6 | modification, are permitted provided that the following conditions are met: |
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7 | |
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8 | Redistributions of source code must retain the above copyright |
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9 | notice, this list of conditions and the following disclaimer. |
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10 | |
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11 | Redistributions in binary form must reproduce the above copyright |
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12 | notice, this list of conditions and the following disclaimer in the |
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13 | documentation and/or other materials provided with the distribution. |
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14 | |
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15 | The name of the company may not be used to endorse or promote |
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16 | products derived from this software without specific prior written |
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17 | permission. |
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18 | |
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19 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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20 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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21 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE |
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22 | DISCLAIMED. IN NO EVENT SHALL RED HAT INCORPORATED BE LIABLE FOR ANY |
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23 | DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES |
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24 | (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; |
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25 | LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND |
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26 | ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT |
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27 | (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS |
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28 | SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. |
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29 | |
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30 | |
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31 | The setjmp/longjmp for nds32. |
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32 | The usage of thirty-two 32-bit General Purpose Registers (GPR): |
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33 | $r28 : $fp |
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34 | $r29 : $gp |
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35 | $r30 : $lp |
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36 | $r31 : $sp |
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37 | |
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38 | caller-save registers: $r0 ~ $r5, $r16 ~ $r23 |
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39 | callee-save registers: $r6 ~ $r10, $r11 ~ $r14 |
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40 | reserved for assembler : $r15 |
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41 | reserved for other use : $r24, $r25, $r26, $r27 |
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42 | |
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43 | Save all callee-save registers and $fp, $gp, $lp and $sp is enough in theory. |
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44 | For debugging issue, the layout of jum_buf in here should be in sync with GDB. |
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45 | The $r16 ~ $r19 are used to store D0/D1, keep them for backward-compatible. |
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46 | */ |
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47 | |
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48 | /* int setjmp(jmp_buf env); */ |
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49 | .text |
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50 | .align 2 |
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51 | .global setjmp |
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52 | .type setjmp, @function |
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53 | setjmp: |
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54 | #if __NDS32_REDUCED_REGS__ |
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55 | smw.bim $r6, [$r0], $r10, #0b0000 |
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56 | addi $r0, $r0, #32 /* Leave room to keep jum_buf all the same. */ |
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57 | smw.bim $r31, [$r0], $r31, #0b1111 |
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58 | #else |
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59 | smw.bim $r6, [$r0], $r14, #0b0000 |
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60 | smw.bim $r16, [$r0], $r19, #0b1111 |
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61 | #endif |
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62 | |
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63 | #if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__ |
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64 | |
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65 | /* Extract $fpcfg.freg (b[3:2]), then save into jmp_buf. */ |
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66 | fmfcfg $r2 |
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67 | slli $r2, $r2, #28 |
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68 | srli $r2, $r2, #30 |
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69 | swi.bi $r2, [$r0], #4 |
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70 | |
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71 | /* Make sure $r0 is double-word-aligned. */ |
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72 | addi $r0, $r0, #7 |
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73 | bitci $r0, $r0, #7 |
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74 | |
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75 | /* Case switch according to $fpcfg.freg */ |
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76 | beqz $r2, .LCFG0_save /* Branch if $fpcfg.freg = 0b00. */ |
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77 | xori $r15, $r2, #0b10 |
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78 | beqz $r15, .LCFG2_save /* Branch $fpcfg.freg = 0b10. */ |
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79 | srli $r2, $r2, #0b01 |
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80 | beqz $r2, .LCFG1_save /* Branch if $fpcfg.freg = 0b01. */ |
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81 | /* Fall-through if $fpcfg.freg = 0b11. */ |
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82 | .LCFG3_save: |
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83 | fsdi.bi $fd31, [$r0], #8 |
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84 | fsdi.bi $fd29, [$r0], #8 |
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85 | fsdi.bi $fd27, [$r0], #8 |
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86 | fsdi.bi $fd25, [$r0], #8 |
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87 | fsdi.bi $fd23, [$r0], #8 |
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88 | fsdi.bi $fd21, [$r0], #8 |
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89 | fsdi.bi $fd19, [$r0], #8 |
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90 | fsdi.bi $fd17, [$r0], #8 |
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91 | .LCFG2_save: |
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92 | fsdi.bi $fd15, [$r0], #8 |
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93 | fsdi.bi $fd13, [$r0], #8 |
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94 | fsdi.bi $fd11, [$r0], #8 |
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95 | fsdi.bi $fd9, [$r0], #8 |
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96 | .LCFG1_save: |
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97 | fsdi.bi $fd7, [$r0], #8 |
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98 | fsdi.bi $fd5, [$r0], #8 |
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99 | .LCFG0_save: |
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100 | fsdi.bi $fd3, [$r0], #8 |
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101 | #endif |
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102 | |
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103 | /* Set return value to zero. */ |
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104 | movi $r0, 0 |
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105 | ret |
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106 | .size setjmp, .-setjmp |
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107 | |
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108 | |
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109 | /* void longjmp(jmp_buf env, int val); */ |
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110 | .text |
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111 | .align 2 |
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112 | .global longjmp |
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113 | .type longjmp, @function |
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114 | longjmp: |
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115 | #if __NDS32_REDUCED_REGS__ |
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116 | lmw.bim $r6, [$r0], $r10, #0b0000 |
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117 | addi $r0, $r0, #32 |
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118 | lmw.bim $r31, [$r0], $r31, #0b1111 |
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119 | #else |
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120 | lmw.bim $r6, [$r0], $r14, #0b0000 |
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121 | lmw.bim $r16, [$r0], $r19, #0b1111 |
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122 | #endif |
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123 | |
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124 | #if __NDS32_EXT_FPU_SP__ || __NDS32_EXT_FPU_DP__ |
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125 | |
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126 | /* Restore value of $fpcfg.freg (b[3:2]). */ |
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127 | lwi.bi $r2, [$r0], #4 |
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128 | |
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129 | /* Make sure $r0 is double-word-aligned. */ |
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130 | addi $r0, $r0, #7 |
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131 | bitci $r0, $r0, #7 |
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132 | |
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133 | /* Case switch according to $fpcfg.freg */ |
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134 | beqz $r2, .LCFG0_restore /* Branch if $fpcfg.freg = 0b00. */ |
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135 | xori $r15, $r2, #0b10 |
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136 | beqz $r15, .LCFG2_restore /* Branch $fpcfg.freg = 0b10. */ |
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137 | srli $r2, $r2, #0b01 |
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138 | beqz $r2, .LCFG1_restore /* Branch if $fpcfg.freg = 0b01. */ |
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139 | /* Fall-through if $fpcfg.freg = 0b11. */ |
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140 | .LCFG3_restore: |
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141 | fldi.bi $fd31, [$r0], #8 |
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142 | fldi.bi $fd29, [$r0], #8 |
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143 | fldi.bi $fd27, [$r0], #8 |
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144 | fldi.bi $fd25, [$r0], #8 |
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145 | fldi.bi $fd23, [$r0], #8 |
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146 | fldi.bi $fd21, [$r0], #8 |
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147 | fldi.bi $fd19, [$r0], #8 |
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148 | fldi.bi $fd17, [$r0], #8 |
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149 | .LCFG2_restore: |
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150 | fldi.bi $fd15, [$r0], #8 |
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151 | fldi.bi $fd13, [$r0], #8 |
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152 | fldi.bi $fd11, [$r0], #8 |
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153 | fldi.bi $fd9, [$r0], #8 |
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154 | .LCFG1_restore: |
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155 | fldi.bi $fd7, [$r0], #8 |
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156 | fldi.bi $fd5, [$r0], #8 |
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157 | .LCFG0_restore: |
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158 | fldi.bi $fd3, [$r0], #8 |
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159 | #endif |
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160 | |
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161 | /* Set val as return value. If the value val is 0, 1 will be returned |
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162 | instead. */ |
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163 | movi $r0, 1 |
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164 | cmovn $r0, $r1, $r1 /* r0=(r1!=0)? r1: r0 */ |
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165 | ret |
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166 | .size longjmp, .-longjmp |
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