[444] | 1 | /* Copyright (c) 2017 SiFive Inc. All rights reserved. |
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| 2 | |
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| 3 | This copyrighted material is made available to anyone wishing to use, |
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| 4 | modify, copy, or redistribute it subject to the terms and conditions |
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| 5 | of the FreeBSD License. This program is distributed in the hope that |
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| 6 | it will be useful, but WITHOUT ANY WARRANTY expressed or implied, |
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| 7 | including the implied warranties of MERCHANTABILITY or FITNESS FOR |
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| 8 | A PARTICULAR PURPOSE. A copy of this license is available at |
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| 9 | http://www.opensource.org/licenses. |
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| 10 | */ |
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| 11 | |
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| 12 | #ifndef _FENV_H_ |
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| 13 | #define _FENV_H_ |
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| 14 | |
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| 15 | #include <stddef.h> |
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| 16 | |
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| 17 | /* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA: |
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| 18 | * Version 2.1", Section 8.2, "Floating-Point Control and Status |
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| 19 | * Register": |
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| 20 | * |
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| 21 | * Flag Mnemonic Flag Meaning |
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| 22 | * ------------- ----------------- |
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| 23 | * NV Invalid Operation |
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| 24 | * DZ Divide by Zero |
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| 25 | * OF Overflow |
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| 26 | * UF Underflow |
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| 27 | * NX Inexact |
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| 28 | */ |
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| 29 | |
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| 30 | #define FE_INVALID 0x00000010 |
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| 31 | #define FE_DIVBYZERO 0x00000008 |
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| 32 | #define FE_OVERFLOW 0x00000004 |
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| 33 | #define FE_UNDERFLOW 0x00000002 |
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| 34 | #define FE_INEXACT 0x00000001 |
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| 35 | |
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| 36 | #define FE_ALL_EXCEPT (FE_INVALID|FE_DIVBYZERO|FE_OVERFLOW|FE_UNDERFLOW|FE_INEXACT) |
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| 37 | |
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| 38 | /* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA: |
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| 39 | * Version 2.1", Section 8.2, "Floating-Point Control and Status |
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| 40 | * Register": |
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| 41 | * |
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| 42 | * Rounding Mode Mnemonic Meaning Meaning |
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| 43 | * ------------- ---------------- ------- |
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| 44 | * 000 RNE Round to Nearest, ties to Even |
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| 45 | * 001 RTZ Round towards Zero |
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| 46 | * 010 RDN Round Down (towards −∞) |
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| 47 | * 011 RUP Round Up (towards +∞) |
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| 48 | * 100 RMM Round to Nearest, ties to Max Magnitude |
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| 49 | * 101 Invalid. Reserved for future use. |
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| 50 | * 110 Invalid. Reserved for future use. |
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| 51 | * 111 In instruction’s rm field, selects dynamic rounding mode; |
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| 52 | * In Rounding Mode register, Invalid |
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| 53 | */ |
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| 54 | |
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| 55 | #define FE_TONEAREST_MM 0x00000004 |
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| 56 | #define FE_UPWARD 0x00000003 |
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| 57 | #define FE_DOWNWARD 0x00000002 |
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| 58 | #define FE_TOWARDZERO 0x00000001 |
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| 59 | #define FE_TONEAREST 0x00000000 |
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| 60 | |
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| 61 | #define FE_RMODE_MASK 0x7 |
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| 62 | |
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| 63 | /* Per "The RISC-V Instruction Set Manual: Volume I: User-Level ISA: |
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| 64 | * Version 2.1": |
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| 65 | * |
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| 66 | * "The F extension adds 32 floating-point registers, f0–f31, each 32 |
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| 67 | * bits wide, and a floating-point control and status register fcsr, |
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| 68 | * which contains the operating mode and exception status of the |
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| 69 | * floating-point unit." |
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| 70 | */ |
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| 71 | |
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| 72 | typedef size_t fenv_t; |
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| 73 | typedef size_t fexcept_t; |
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| 74 | extern const fenv_t fe_dfl_env; |
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| 75 | #define FE_DFL_ENV fe_dfl_env_p |
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| 76 | |
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| 77 | #endif /* _FENV_H_ */ |
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