| 1 | /* |
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| 2 | (C) Copyright IBM Corp. 2008 |
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| 3 | |
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| 4 | All rights reserved. |
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| 5 | |
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| 6 | Redistribution and use in source and binary forms, with or without |
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| 7 | modification, are permitted provided that the following conditions are met: |
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| 8 | |
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| 9 | * Redistributions of source code must retain the above copyright notice, |
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| 10 | this list of conditions and the following disclaimer. |
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| 11 | * Redistributions in binary form must reproduce the above copyright |
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| 12 | notice, this list of conditions and the following disclaimer in the |
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| 13 | documentation and/or other materials provided with the distribution. |
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| 14 | * Neither the name of IBM nor the names of its contributors may be |
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| 15 | used to endorse or promote products derived from this software without |
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| 16 | specific prior written permission. |
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| 17 | |
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| 18 | THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" |
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| 19 | AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE |
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| 20 | IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE |
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| 21 | ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE |
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| 22 | LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR |
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| 23 | CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF |
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| 24 | SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS |
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| 25 | INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN |
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| 26 | CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) |
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| 27 | ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE |
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| 28 | POSSIBILITY OF SUCH DAMAGE. |
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| 29 | */ |
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| 30 | |
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| 31 | /* First-level interrupt handler. */ |
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| 32 | |
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| 33 | /* The following two convenience macros assist in the coding of the |
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| 34 | saving and restoring the volatile register starting from register |
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| 35 | 2 up to register 79. |
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| 36 | |
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| 37 | saveregs first, last Saves registers from first to the last. |
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| 38 | restoreregs first, last Restores registers from last down to first. |
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| 39 | |
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| 40 | Note: first must be less than or equal to last. */ |
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| 41 | |
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| 42 | .macro saveregs first, last |
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| 43 | stqd $\first, -(STACK_SKIP+\first)*16($SP) |
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| 44 | .if \last-\first |
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| 45 | saveregs "(\first+1)",\last |
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| 46 | .endif |
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| 47 | .endm |
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| 48 | |
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| 49 | |
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| 50 | .macro restoreregs first, last |
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| 51 | lqd $\last, (82-\last)*16($SP) |
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| 52 | .if \last-\first |
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| 53 | restoreregs \first,"(\last-1)" |
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| 54 | .endif |
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| 55 | .endm |
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| 56 | |
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| 57 | .section .interrupt,"ax" |
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| 58 | .align 3 |
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| 59 | .type spu_flih, @function |
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| 60 | spu_flih: |
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| 61 | /* Adjust the stack pointer to skip the maximum register save area |
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| 62 | (STACK_SKIP quadword registers) in case an interrupt occurred while |
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| 63 | executing a leaf function that used the stack area without actually |
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| 64 | allocating its own stack frame. */ |
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| 65 | .set STACK_SKIP, 125 |
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| 66 | |
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| 67 | /* Save the current link register on a new stack frame for the |
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| 68 | normal spu_flih() version of this file. */ |
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| 69 | stqd $0, -(STACK_SKIP+80)*16($SP) |
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| 70 | stqd $SP, -(STACK_SKIP+82)*16($SP) /* Save back chain pointer. */ |
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| 71 | |
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| 72 | saveregs 2, 39 |
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| 73 | |
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| 74 | il $2, -(STACK_SKIP+82)*16 /* Stack frame size. */ |
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| 75 | rdch $3, $SPU_RdEventStat /* Read event status. */ |
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| 76 | |
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| 77 | rdch $6, $SPU_RdEventMask /* Read event mask. */ |
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| 78 | hbrp /* Open a slot for instruction prefetch. */ |
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| 79 | |
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| 80 | saveregs 40,59 |
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| 81 | |
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| 82 | clz $4, $3 /* Get first slih index. */ |
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| 83 | stqd $6, -(STACK_SKIP+1)*16($SP) /* Save event mask on stack. */ |
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| 84 | |
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| 85 | saveregs 60, 67 |
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| 86 | |
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| 87 | /* Do not disable/ack the decrementer event here. |
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| 88 | The timer library manages this and expects it |
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| 89 | to be enabled upon entry to the SLIH. */ |
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| 90 | il $7, 0x20 |
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| 91 | andc $5, $3, $7 |
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| 92 | andc $7, $6, $5 /* Clear event bits. */ |
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| 93 | saveregs 68, 69 |
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| 94 | |
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| 95 | wrch $SPU_WrEventAck, $3 /* Ack events(s) - include decrementer event. */ |
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| 96 | wrch $SPU_WrEventMask, $7 /* Disable event(s) - exclude decrementer event. */ |
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| 97 | |
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| 98 | saveregs 70, 79 |
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| 99 | |
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| 100 | a $SP, $SP, $2 /* Instantiate flih stack frame. */ |
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| 101 | next_event: |
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| 102 | /* Fetch and dispatch the event handler for the first non-zero event. The |
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| 103 | dispatch handler is indexed into the __spu_slih_handlers array using the |
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| 104 | count of zero off the event status as an index. */ |
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| 105 | ila $5, __spu_slih_handlers /* Slih array offset. */ |
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| 106 | |
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| 107 | shli $4, $4, 2 /* Slih entry offset. */ |
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| 108 | lqx $5, $4, $5 /* Load slih address. */ |
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| 109 | rotqby $5, $5, $4 /* Rotate to word 0. */ |
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| 110 | bisl $0, $5 /* Branch to slih. */ |
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| 111 | |
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| 112 | clz $4, $3 /* Get next slih index. */ |
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| 113 | brnz $3, next_event |
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| 114 | |
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| 115 | |
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| 116 | lqd $2, 81*16($SP) /* Read event mask from stack. */ |
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| 117 | |
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| 118 | restoreregs 40, 79 |
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| 119 | |
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| 120 | wrch $SPU_WrEventMask, $2 /* Restore event mask. */ |
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| 121 | hbrp /* Open a slot for instruction pre-fetch. */ |
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| 122 | |
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| 123 | restoreregs 2, 39 |
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| 124 | |
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| 125 | /* Restore the link register from the new stack frame for the |
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| 126 | normal spu_flih() version of this file. */ |
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| 127 | lqd $0, 2*16($SP) |
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| 128 | |
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| 129 | lqd $SP, 0*16($SP) /* restore stack pointer from back chain ptr. */ |
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| 130 | |
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| 131 | irete /* Return from interrupt and re-enable interrupts. */ |
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| 132 | .size spu_flih, .-spu_flih |
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| 133 | /* spu_slih_handlers[] |
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| 134 | Here we initialize 33 default event handlers. The first entry in this array |
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| 135 | corresponds to the event handler for the event associated with bit 0 of |
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| 136 | Channel 0 (External Event Status). The 32nd entry in this array corresponds |
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| 137 | to bit 31 of Channel 0 (DMA Tag Status Update Event). The 33rd entry in |
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| 138 | this array is a special case entry to handle "phantom events" which occur |
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| 139 | when the channel count for Channel 0 is 1, causing an asynchronous SPU |
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| 140 | interrupt, but the value returned for a read of Channel 0 is 0. The index |
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| 141 | calculated into this array by spu_flih() for this case is 32, hence the |
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| 142 | 33rd entry. */ |
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| 143 | .data |
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| 144 | .align 4 |
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| 145 | .extern __spu_default_slih |
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| 146 | .global __spu_slih_handlers |
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| 147 | .type __spu_slih_handlers, @object |
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| 148 | __spu_slih_handlers: |
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| 149 | .rept 33 |
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| 150 | .long __spu_default_slih |
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| 151 | .endr |
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| 152 | .size __spu_slih_handlers, .-__spu_slih_handlers |
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