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source: trunk/tools/arch_info/arch_classes.py @ 1

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[1]	1	#!/usr/bin/env python
	2
	3	import sys
	4
	5	##########################################################################################
	6	# File : arch_classes.py
	7	# Date : 2016
	8	# Author : Alain Greiner
	9	# Copyright (c) UPMC Sorbonne Universites
	10	#########################################################################################
	11	# This file contains the python classes required to define a generic hardware
	12	# architecture for the ALMOS-MK operating system.
	13	# It handle 4 types of objects: clusters, cores, devices and irqs.
	14	# - The number of cluster is variable (can be one).
	15	# - The cluster topology can be a 2D mesh or a simpla array.
	16	# - The number of cores per cluster is variable (can be zero).
	17	# - The number of addressable devices per cluster is variable.
	18	# - The size of the physical memory bank per cluster is variable.
	19	# An adressable device can be a physical memory bank or a peripheral.
	20	# Each cluster cover a fixed size segment in physical address space,
	21	# that is defined by (PADDR_WIDTH - X_WIDTH - Y_WIDTH)
	22	#########################################################################################
	23	# Implementation Note:
	24	# The objects used to describe an architecture are distributed in the python structure:
	25	# For example the set of cores and the set of devices are split in several subsets
	26	# (one subset of cores and one subset of devices per cluster).
	27	# In the generated C binary data structure, all objects of same type
	28	# are stored in a linear array (one single array for all cores for example).
	29	# For all objects, we compute and store in the python object a "global index"
	30	# corresponding to the index in this global array, and this index can be used as
	31	# a pseudo-pointer to identify a specific object of a given type.
	32	#########################################################################################
	33
	34	#########################################################################################
	35	# Define global parameters
	36	#########################################################################################
	37
	38	ARCHINFO_SIGNATURE = 0xBABE2016 # magic number indicating a valid C BLOB
	39	PAGE_SIZE = 0x1000 # to check peripherals alignment
	40
	41	#########################################################################################
	42	# These arrays define the supported types of peripherals.
	43	# They must be kept consistent with values defined in file arch_info.h.
	44	#########################################################################################
	45
	46	DEVICE_TYPES_STR = [
	47	'RAM', # 0
	48	'DMA', # 1
	49	'FBF', # 1
	50	'IOB', # 3
	51	'IOC_BDV', # 4
	52	'IOC_HBA', # 5
	53	'IOC_SDC', # 6
	54	'IOC_SPI', # 7
	55	'IOC_RDK', # 8
	56	'MMC', # 9
	57	'MWR_CPY', # 10
	58	'MWR_GCD', # 11
	59	'MWR_DCT', # 12
	60	'NIC', # 13
	61	'ROM', # 14
	62	'SIM', # 15
	63	'TIM', # 16
	64	'TTY', # 17
	65	'XCU', # 18
	66	'PIC', # 19
	67	'CMA', # 20
	68	]
	69
	70	DEVICE_TYPES_INT = [
	71	0x00000000, # 0
	72	0x00010000, # 1
	73	0x00020000, # 1
	74	0x00030000, # 3
	75	0x00040000, # 4
	76	0x00040001, # 5
	77	0x00040002, # 6
	78	0x00040003, # 7
	79	0x00040004, # 8
	80	0x00050000, # 9
	81	0x00060000, # 10
	82	0x00060001, # 11
	83	0x00060002, # 12
	84	0x00070000, # 13
	85	0x00080000, # 14
	86	0x00090000, # 15
	87	0x000A0000, # 16
	88	0x000B0000, # 17
	89	0x000C0000, # 18
	90	0x000D0000, # 19
	91	0x000E0000, # 20
	92	]
	93
	94	#########################################################################################
	95	class Archinfo( object ):
	96	#########################################################################################
	97	def __init__( self,
	98	name, # architecture instance name
	99	x_size, # number of clusters in a row
	100	y_size, # number of clusters in a column
	101	cores_max, # max number of cores per cluster
	102	devices_max, # max number of devices per cluster
	103	paddr_width, # number of bits in physical address
	104	x_width, # number of bits for x coordinate
	105	y_width, # number of bits for y coordinate
	106	irqs_per_core, # number or IRQs from XCU to one core
	107	io_cxy, # IO cluster identifier
	108	boot_cxy, # boot cluster identifier
	109	cache_line, # number of bytes in cache line
	110	reset_address, # Preloader physical base address
	111	p_width ): # TSAR specific : number of bits to code core lid
	112
	113	assert ( x_size <= (1<<x_width) )
	114	assert ( y_size <= (1<<y_width) )
	115
	116	self.signature = ARCHINFO_SIGNATURE
	117	self.name = name
	118	self.x_size = x_size
	119	self.y_size = y_size
	120	self.cores_max = cores_max
	121	self.devices_max = devices_max
	122	self.paddr_width = paddr_width
	123	self.x_width = x_width
	124	self.y_width = y_width
	125	self.irqs_per_core = irqs_per_core
	126	self.io_cxy = io_cxy
	127	self.boot_cxy = boot_cxy
	128	self.cache_line = cache_line
	129	self.reset_address = reset_address
	130	self.p_width = p_width
	131
	132	self.total_cores = 0
	133	self.total_devices = 0
	134	self.total_irqs = 0
	135
	136	self.clusters = []
	137
	138	for x in xrange( self.x_size ):
	139	for y in xrange( self.y_size ):
	140
	141	# call cluster constructor
	142	cxy = (x<<y_width) + y
	143	cluster = Cluster( cxy )
	144
	145	# update cluster global index
	146	cluster.index = (x * self.y_size) + y
	147
	148	# register cluster in Archinfo
	149	self.clusters.append( cluster )
	150
	151	return
	152
	153	########################## add a device in a cluster
	154	def addDevice( self,
	155	ptype, # device type
	156	base, # associated pseg base address
	157	size, # associated pseg length (bytes)
	158	channels = 1, # number of channels
	159	arg0 = 0, # optional argument (semantic depends on ptype)
	160	arg1 = 0, # optional argument (semantic depends on ptype)
	161	arg2 = 0, # optional argument (semantic depends on ptype)
	162	arg3 = 0 ): # optional argument (semantic depends on ptype)
	163
	164	# computes cluster identifier and global index from the base address
	165	cxy = base >> (self.paddr_width - self.x_width - self.y_width)
	166	x = cxy >> (self.y_width);
	167	y = cxy & ((1 << self.y_width) - 1)
	168	cluster_id = (x * self.y_size) + y
	169
	170	assert (x < self.x_size) and (y < self.y_size)
	171	assert (base & (PAGE_SIZE-1) == 0)
	172	assert (ptype in DEVICE_TYPES_STR)
	173
	174	# call device constructor
	175	device = Device( base, size, ptype, channels, arg0, arg1, arg2, arg3 )
	176
	177	# register device in cluster
	178	self.clusters[cluster_id].devices.append( device )
	179
	180	# update device global index
	181	device.index = self.total_devices
	182	self.total_devices += 1
	183
	184	return device
	185
	186	################################ add an input IRQ in a device
	187	def addIrq( self,
	188	dstdev, # destination device (PIC or XCU)
	189	port, # input IRQ port index
	190	srcdev, # source device
	191	channel = 0, # source device channel
	192	is_rx = False ): # I/O operation direction
	193
	194	assert (dstdev.ptype == 'XCU') or (dstdev.ptype == 'PIC')
	195	assert (port < dstdev.arg0)
	196
	197	# call Irq constructor
	198	irq = Irq( port , srcdev, channel , is_rx )
	199
	200	# register IRQ in destination device
	201	dstdev.irqs.append( irq )
	202
	203	# update IRQ global index
	204	irq.index = self.total_irqs
	205	self.total_irqs += 1
	206
	207	# pointer from the source to the interrupt controller device
	208	if (srcdev.irq_ctrl == None): srcdev.irq_ctrl = dstdev
	209
	210	if (srcdev.irq_ctrl != dstdev):
	211	print '[genarch error] in addIrq():'
	212	print ' two different interrupt controller for the same device'
	213	sys.exit(1)
	214
	215	return irq
	216
	217	########################## add a core in a cluster
	218	def addCore( self,
	219	gid, # global hardware identifier
	220	cxy, # cluster identifier
	221	lid ): # local index in cluster
	222
	223	assert ((cxy >> self.y_width) < self.x_size)
	224	assert ((cxy & ((1<<self.y_width)-1)) < self.y_size)
	225	assert (lid < self.cores_max)
	226
	227	# call Core contructor
	228	core = Core( gid, cxy, lid )
	229
	230	# compute cluster global index from cluster identifier
	231	x = cxy>>self.y_width
	232	y = cxy & ((1<<self.y_width)-1)
	233	cluster_id = (x * self.y_size) + y
	234
	235	# register core in cluster
	236	self.clusters[cluster_id].cores.append( core )
	237
	238	# update core global index
	239	core.index = self.total_cores
	240	self.total_cores += 1
	241
	242	return core
	243
	244	#################################
	245	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
	246
	247	byte_stream = bytearray()
	248	length = len( s )
	249	if length < (nbytes - 1):
	250	for b in s:
	251	byte_stream.append( b )
	252	for x in xrange(nbytes-length):
	253	byte_stream.append( '\0' )
	254	else:
	255	print '[genarch error] in str2bytes()'
	256	print ' string %s too long' % s
	257	sys.exit(1)
	258
	259	return byte_stream
	260
	261	###################################
	262	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
	263
	264	byte_stream = bytearray()
	265	for n in xrange( nbytes ):
	266	byte_stream.append( (val >> (n<<3)) & 0xFF )
	267
	268	return byte_stream
	269
	270	################
	271	def xml( self ): # compute string for xml file generation
	272
	273	s = '<?xml version="1.0"?>\n\n'
	274	s += '<arch_info signature = "0x%x"\n' % (self.signature)
	275	s += ' name = "%s"\n' % (self.name)
	276	s += ' x_size = "%d"\n' % (self.x_size)
	277	s += ' y_size = "%d"\n' % (self.y_size)
	278	s += ' cores = "%d"\n' % (self.cores_max)
	279	s += ' io_cxy = "%d" >\n' % (self.io_cxy)
	280	s += '\n'
	281
	282	s += ' <clusterset>\n'
	283	for x in xrange ( self.x_size ):
	284	for y in xrange ( self.y_size ):
	285	cluster_id = (x * self.y_size) + y
	286	s += self.clusters[cluster_id].xml()
	287	s += ' </clusterset>\n'
	288	s += '\n'
	289
	290	s += '</arch_info>\n'
	291	return s
	292
	293	##########################
	294	def cbin( self, verbose ): # C binary structure for "archinfo.bin" file generation
	295
	296	byte_stream = bytearray()
	297
	298	# header
	299	byte_stream += self.int2bytes(4, self.signature)
	300	byte_stream += self.int2bytes(4, self.x_size)
	301	byte_stream += self.int2bytes(4, self.y_size)
	302	byte_stream += self.int2bytes(4, self.paddr_width)
	303	byte_stream += self.int2bytes(4, self.x_width)
	304	byte_stream += self.int2bytes(4, self.y_width)
	305	byte_stream += self.int2bytes(4, self.cores_max)
	306	byte_stream += self.int2bytes(4, self.devices_max)
	307
	308	byte_stream += self.int2bytes(4, self.total_cores)
	309	byte_stream += self.int2bytes(4, self.total_devices)
	310	byte_stream += self.int2bytes(4, self.total_irqs)
	311	byte_stream += self.int2bytes(4, self.io_cxy)
	312	byte_stream += self.int2bytes(4, self.boot_cxy)
	313	byte_stream += self.int2bytes(4, self.irqs_per_core)
	314	byte_stream += self.int2bytes(4, self.cache_line)
	315	byte_stream += self.int2bytes(4, 0)
	316
	317	byte_stream += self.str2bytes(64, self.name)
	318
	319	if ( verbose ):
	320	print '\n'
	321	print 'name = %s' % self.name
	322	print 'signature = %x' % self.signature
	323	print 'x_size = %d' % self.x_size
	324	print 'y_size = %d' % self.y_size
	325	print 'total_cores = %d' % self.total_cores
	326	print 'total_devices = %d' % self.total_devices
	327	print 'total_irqs = %d' % self.total_irqs
	328	print '\n'
	329
	330	# cores array
	331	index = 0
	332	for cluster in self.clusters:
	333	for core in cluster.cores:
	334	byte_stream += core.cbin( self, verbose, index )
	335	index += 1
	336
	337	if ( verbose ): print '\n'
	338
	339	# clusters array
	340	index = 0
	341	for cluster in self.clusters:
	342	byte_stream += cluster.cbin( self, verbose, index )
	343	index += 1
	344
	345	if ( verbose ): print '\n'
	346
	347	# devices array
	348	index = 0
	349	for cluster in self.clusters:
	350	for device in cluster.devices:
	351	byte_stream += device.cbin( self, verbose, index )
	352	index += 1
	353
	354	if ( verbose ): print '\n'
	355
	356	# irqs array
	357	index = 0
	358	for cluster in self.clusters:
	359	for device in cluster.devices:
	360	for irq in device.irqs:
	361	byte_stream += irq.cbin( self, verbose, index )
	362	index += 1
	363
	364	if ( verbose ): print '\n'
	365
	366	return byte_stream
	367	# end of cbin()
	368
	369
	370	######################################################################
	371	def hard_config( self ): # compute string for hard_config.h file
	372	# required by
	373	# - top.cpp compilation
	374	# - almos-mk bootloader compilation
	375	# - tsar_preloader compilation
	376
	377	# for each device type, define default values
	378	# for pbase address, size, number of components, and channels
	379	nb_ram = 0
	380	ram_channels = 0
	381	ram_base = 0xFFFFFFFFFFFFFFFF
	382	ram_size = 0
	383
	384	nb_cma = 0
	385	cma_channels = 0
	386	cma_base = 0xFFFFFFFFFFFFFFFF
	387	cma_size = 0
	388
	389	nb_dma = 0
	390	dma_channels = 0
	391	dma_base = 0xFFFFFFFFFFFFFFFF
	392	dma_size = 0
	393
	394	nb_fbf = 0
	395	fbf_channels = 0
	396	fbf_base = 0xFFFFFFFFFFFFFFFF
	397	fbf_size = 0
	398	fbf_arg0 = 0
	399	fbf_arg1 = 0
	400
	401	nb_iob = 0
	402	iob_channels = 0
	403	iob_base = 0xFFFFFFFFFFFFFFFF
	404	iob_size = 0
	405
	406	nb_ioc = 0
	407	ioc_channels = 0
	408	ioc_base = 0xFFFFFFFFFFFFFFFF
	409	ioc_size = 0
	410	use_ioc_bdv = False
	411	use_ioc_sdc = False
	412	use_ioc_hba = False
	413	use_ioc_spi = False
	414	use_ioc_rdk = False
	415
	416	nb_mmc = 0
	417	mmc_channels = 0
	418	mmc_base = 0xFFFFFFFFFFFFFFFF
	419	mmc_size = 0
	420
	421	nb_mwr = 0
	422	mwr_channels = 0
	423	mwr_base = 0xFFFFFFFFFFFFFFFF
	424	mwr_size = 0
	425	mwr_arg0 = 0
	426	mwr_arg1 = 0
	427	mwr_arg2 = 0
	428	mwr_arg3 = 0
	429	use_mwr_gcd = False
	430	use_mwr_dct = False
	431	use_mwr_cpy = False
	432
	433	nb_nic = 0
	434	nic_channels = 0
	435	nic_base = 0xFFFFFFFFFFFFFFFF
	436	nic_size = 0
	437
	438	nb_pic = 0
	439	pic_channels = 0
	440	pic_base = 0xFFFFFFFFFFFFFFFF
	441	pic_size = 0
	442
	443	nb_rom = 0
	444	rom_channels = 0
	445	rom_base = 0xFFFFFFFFFFFFFFFF
	446	rom_size = 0
	447
	448	nb_sim = 0
	449	sim_channels = 0
	450	sim_base = 0xFFFFFFFFFFFFFFFF
	451	sim_size = 0
	452
	453	nb_tim = 0
	454	tim_channels = 0
	455	tim_base = 0xFFFFFFFFFFFFFFFF
	456	tim_size = 0
	457
	458	nb_tty = 0
	459	tty_channels = 0
	460	tty_base = 0xFFFFFFFFFFFFFFFF
	461	tty_size = 0
	462
	463	nb_xcu = 0
	464	xcu_channels = 0
	465	xcu_base = 0xFFFFFFFFFFFFFFFF
	466	xcu_size = 0
	467	xcu_arg0 = 0
	468
	469	nb_drom = 0
	470	drom_channels = 0
	471	drom_base = 0xFFFFFFFFFFFFFFFF
	472	drom_size = 0
	473
	474	# get devices attributes
	475	for cluster in self.clusters:
	476	for device in cluster.devices:
	477
	478	if ( device.ptype == 'RAM' ):
	479	ram_base = device.base
	480	ram_size = device.size
	481	ram_channels = device.channels
	482	nb_ram +=1
	483
	484	elif ( device.ptype == 'CMA' ):
	485	cma_base = device.base
	486	cma_size = device.size
	487	cma_channels = device.channels
	488	nb_cma +=1
	489
	490	elif ( device.ptype == 'DMA' ):
	491	dma_base = device.base
	492	dma_size = device.size
	493	dma_channels = device.channels
	494	nb_dma +=1
	495
	496	elif ( device.ptype == 'FBF' ):
	497	fbf_base = device.base
	498	fbf_size = device.size
	499	fbf_channels = device.channels
	500	fbf_arg0 = device.arg0
	501	fbf_arg1 = device.arg1
	502	nb_fbf +=1
	503
	504	elif ( device.ptype == 'IOB' ):
	505	iob_base = device.base
	506	iob_size = device.size
	507	iob_channels = device.channels
	508	nb_iob +=1
	509
	510	elif ( device.ptype == 'IOC_BDV' ):
	511	ioc_base = device.base
	512	ioc_size = device.size
	513	ioc_channels = device.channels
	514	use_ioc_bdv = True
	515	nb_ioc += 1
	516	elif ( device.ptype == 'IOC_HBA' ):
	517	ioc_base = device.base
	518	ioc_size = device.size
	519	ioc_channels = device.channels
	520	use_ioc_hba = True
	521	nb_ioc += 1
	522	elif ( device.ptype == 'IOC_SDC' ):
	523	ioc_base = device.base
	524	ioc_size = device.size
	525	ioc_channels = device.channels
	526	use_ioc_sdc = True
	527	nb_ioc += 1
	528	elif ( device.ptype == 'IOC_SPI' ):
	529	ioc_base = device.base
	530	ioc_size = device.size
	531	ioc_channels = device.channels
	532	use_ioc_spi = True
	533	nb_ioc += 1
	534
	535	elif ( device.ptype == 'IOC_RDK' ):
	536	ioc_base = device.base
	537	ioc_size = device.size
	538	ioc_channels = device.channels
	539	use_ioc_rdk = True
	540	nb_ioc += 1
	541
	542	elif ( device.ptype == 'MMC' ):
	543	mmc_base = device.base
	544	mmc_size = device.size
	545	mmc_channels = device.channels
	546	nb_mmc +=1
	547
	548	elif ( device.ptype == 'MWR_GCD' ):
	549	mwr_base = device.base
	550	mwr_size = device.size
	551	mwr_channels = device.channels
	552	mwr_arg0 = device.arg0
	553	mwr_arg1 = device.arg1
	554	mwr_arg2 = device.arg2
	555	mwr_arg3 = device.arg3
	556	use_mwr_gcd = True
	557	nb_mwr +=1
	558	elif ( device.ptype == 'MWR_DCT' ):
	559	mwr_base = device.base
	560	mwr_size = device.size
	561	mwr_channels = device.channels
	562	mwr_arg0 = device.arg0
	563	mwr_arg1 = device.arg1
	564	mwr_arg2 = device.arg2
	565	mwr_arg3 = device.arg3
	566	use_mwr_dct = True
	567	nb_mwr +=1
	568	elif ( device.ptype == 'MWR_CPY' ):
	569	mwr_base = device.base
	570	mwr_size = device.size
	571	mwr_channels = device.channels
	572	mwr_arg0 = device.arg0
	573	mwr_arg1 = device.arg1
	574	mwr_arg2 = device.arg2
	575	mwr_arg3 = device.arg3
	576	use_mwr_cpy = True
	577	nb_mwr +=1
	578
	579	elif ( device.ptype == 'ROM' ):
	580	rom_base = device.base
	581	rom_size = device.size
	582	rom_channels = device.channels
	583	nb_rom +=1
	584
	585	elif ( device.ptype == 'DROM' ):
	586	drom_base = device.base
	587	drom_size = device.size
	588	drom_channels = device.channels
	589	nb_drom +=1
	590
	591	elif ( device.ptype == 'SIM' ):
	592	sim_base = device.base
	593	sim_size = device.size
	594	sim_channels = device.channels
	595	nb_sim +=1
	596
	597	elif ( device.ptype == 'NIC' ):
	598	nic_base = device.base
	599	nic_size = device.size
	600	nic_channels = device.channels
	601	nb_nic +=1
	602
	603	elif ( device.ptype == 'PIC' ):
	604	pic_base = device.base
	605	pic_size = device.size
	606	pic_channels = device.channels
	607	nb_pic +=1
	608
	609	elif ( device.ptype == 'TIM' ):
	610	tim_base = device.pseg.base
	611	tim_size = device.pseg.size
	612	tim_channels = device.channels
	613	nb_tim +=1
	614
	615	elif ( device.ptype == 'TTY' ):
	616	tty_base = device.base
	617	tty_size = device.size
	618	tty_channels = device.channels
	619	nb_tty +=1
	620
	621	elif ( device.ptype == 'XCU' ):
	622	xcu_base = device.base
	623	xcu_size = device.size
	624	xcu_channels = device.channels
	625	xcu_arg0 = device.arg0
	626	xcu_arg1 = device.arg1
	627	xcu_arg2 = device.arg2
	628	nb_xcu +=1
	629
	630	# no more than two access to external devices
	631	assert ( nb_fbf <= 2 )
	632	assert ( nb_cma <= 2 )
	633	assert ( nb_ioc <= 2 )
	634	assert ( nb_nic <= 2 )
	635	assert ( nb_tim <= 2 )
	636	assert ( nb_tty <= 2 )
	637	assert ( nb_pic <= 2 )
	638
	639	# one and only one IOC controller
	640	assert ( nb_ioc == 1 )
	641
	642	# compute rdk_base and rdk_size
	643	if( use_ioc_rdk ):
	644	rdk_base = ioc_base
	645	rdk_size = ioc_size
	646	else:
	647	rdk_base = 0
	648	rdk_size = 0
	649
	650	# only one type of MWR controller
	651	nb_mwr_types = 0
	652	if use_mwr_gcd: nb_mwr_types += 1
	653	if use_mwr_dct: nb_mwr_types += 1
	654	if use_mwr_cpy: nb_mwr_types += 1
	655	if ( nb_mwr > 0 ) : assert ( nb_mwr_types == 1 )
	656
	657	# Compute total number of cores, devices and irqs
	658	nb_total_cores = self.total_cores
	659	nb_total_devices = self.total_devices
	660	nb_total_irqs = self.total_irqs
	661
	662	# boot core has (cxy == boot_cxy) and (lid == 0)
	663	for cluster in self.clusters:
	664	if( cluster.cxy == self.boot_cxy ): boot_core_gid = cluster.cores[0].gid
	665
	666	# compute mask to get local physical address (cluster independant)
	667	local_paddr_width = self.paddr_width - self.x_width - self.y_width
	668	local_physical_mask = (1<<local_paddr_width)-1
	669
	670	# build string
	671	s = '/* Generated by genarch for %s */\n' % self.name
	672	s += '\n'
	673	s += '#ifndef HARD_CONFIG_H\n'
	674	s += '#define HARD_CONFIG_H\n'
	675	s += '\n'
	676
	677	s += '/* General platform parameters */\n'
	678	s += '\n'
	679	s += '#define X_SIZE %d\n' % self.x_size
	680	s += '#define Y_SIZE %d\n' % self.y_size
	681	s += '#define PADDR_WIDTH %d\n' % self.paddr_width
	682	s += '#define X_WIDTH %d\n' % self.x_width
	683	s += '#define Y_WIDTH %d\n' % self.y_width
	684	s += '#define P_WIDTH %d\n' % self.p_width
	685	s += '#define X_IO %d\n' % (self.io_cxy >> self.y_width)
	686	s += '#define Y_IO %d\n' % (self.io_cxy & ((1<<self.y_width)-1))
	687	s += '#define NB_PROCS_MAX %d\n' % self.cores_max
	688	s += '#define NB_DEVICES_MAX %d\n' % self.devices_max
	689	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irqs_per_core
	690	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
	691	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_cores
	692	s += '#define BOOT_CORE_GID %d\n' % boot_core_gid
	693	s += '#define BOOT_CORE_CXY %d\n' % self.boot_cxy
	694	s += '#define CACHE_LINE_SIZE %d\n' % self.cache_line
	695	s += '\n'
	696
	697	s += '/* Peripherals */\n'
	698	s += '\n'
	699	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
	700	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
	701	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
	702	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
	703	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
	704	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
	705	s += '\n'
	706	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
	707	s += '#define USE_DMA %d\n' % ( nb_dma != 0 )
	708	s += '\n'
	709	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
	710	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
	711	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
	712	s += '#define USE_NIC %d\n' % ( nb_nic != 0 )
	713	s += '\n'
	714	s += '#define USE_IOC_BDV %d\n' % use_ioc_bdv
	715	s += '#define USE_IOC_SDC %d\n' % use_ioc_sdc
	716	s += '#define USE_IOC_HBA %d\n' % use_ioc_hba
	717	s += '#define USE_IOC_SPI %d\n' % use_ioc_spi
	718	s += '#define USE_IOC_RDK %d\n' % use_ioc_rdk
	719	s += '\n'
	720	s += '#define USE_MWR_GCD %d\n' % use_mwr_gcd
	721	s += '#define USE_MWR_DCT %d\n' % use_mwr_dct
	722	s += '#define USE_MWR_CPY %d\n' % use_mwr_cpy
	723	s += '\n'
	724	s += '#define FBUF_X_SIZE %d\n' % fbf_arg0
	725	s += '#define FBUF_Y_SIZE %d\n' % fbf_arg1
	726	s += '\n'
	727	s += '#define XCU_NB_HWI %d\n' % xcu_arg0
	728	s += '#define XCU_NB_PTI %d\n' % xcu_arg1
	729	s += '#define XCU_NB_WTI %d\n' % xcu_arg2
	730	s += '#define XCU_NB_OUT %d\n' % xcu_channels
	731	s += '\n'
	732	s += '#define MWR_TO_COPROC %d\n' % mwr_arg0
	733	s += '#define MWR_FROM_COPROC %d\n' % mwr_arg1
	734	s += '#define MWR_CONFIG %d\n' % mwr_arg2
	735	s += '#define MWR_STATUS %d\n' % mwr_arg3
	736	s += '\n'
	737
	738	s += '/* local physical base address and size for devices */\n'
	739	s += '\n'
	740	s += '#define SEG_RAM_BASE 0x%x\n' % (ram_base & local_physical_mask)
	741	s += '#define SEG_RAM_SIZE 0x%x\n' % ram_size
	742	s += '\n'
	743	s += '#define SEG_CMA_BASE 0x%x\n' % (cma_base & local_physical_mask)
	744	s += '#define SEG_CMA_SIZE 0x%x\n' % cma_size
	745	s += '\n'
	746	s += '#define SEG_DMA_BASE 0x%x\n' % (dma_base & local_physical_mask)
	747	s += '#define SEG_DMA_SIZE 0x%x\n' % dma_size
	748	s += '\n'
	749	s += '#define SEG_FBF_BASE 0x%x\n' % (fbf_base & local_physical_mask)
	750	s += '#define SEG_FBF_SIZE 0x%x\n' % fbf_size
	751	s += '\n'
	752	s += '#define SEG_IOB_BASE 0x%x\n' % (iob_base & local_physical_mask)
	753	s += '#define SEG_IOB_SIZE 0x%x\n' % iob_size
	754	s += '\n'
	755	s += '#define SEG_IOC_BASE 0x%x\n' % (ioc_base & local_physical_mask)
	756	s += '#define SEG_IOC_SIZE 0x%x\n' % ioc_size
	757	s += '\n'
	758	s += '#define SEG_MMC_BASE 0x%x\n' % (mmc_base & local_physical_mask)
	759	s += '#define SEG_MMC_SIZE 0x%x\n' % mmc_size
	760	s += '\n'
	761	s += '#define SEG_MWR_BASE 0x%x\n' % (mwr_base & local_physical_mask)
	762	s += '#define SEG_MWR_SIZE 0x%x\n' % mwr_size
	763	s += '\n'
	764	s += '#define SEG_ROM_BASE 0x%x\n' % (rom_base & local_physical_mask)
	765	s += '#define SEG_ROM_SIZE 0x%x\n' % rom_size
	766	s += '\n'
	767	s += '#define SEG_SIM_BASE 0x%x\n' % (sim_base & local_physical_mask)
	768	s += '#define SEG_SIM_SIZE 0x%x\n' % sim_size
	769	s += '\n'
	770	s += '#define SEG_NIC_BASE 0x%x\n' % (nic_base & local_physical_mask)
	771	s += '#define SEG_NIC_SIZE 0x%x\n' % nic_size
	772	s += '\n'
	773	s += '#define SEG_PIC_BASE 0x%x\n' % (pic_base & local_physical_mask)
	774	s += '#define SEG_PIC_SIZE 0x%x\n' % pic_size
	775	s += '\n'
	776	s += '#define SEG_TIM_BASE 0x%x\n' % (tim_base & local_physical_mask)
	777	s += '#define SEG_TIM_SIZE 0x%x\n' % tim_size
	778	s += '\n'
	779	s += '#define SEG_TTY_BASE 0x%x\n' % (tty_base & local_physical_mask)
	780	s += '#define SEG_TTY_SIZE 0x%x\n' % tty_size
	781	s += '\n'
	782	s += '#define SEG_XCU_BASE 0x%x\n' % (xcu_base & local_physical_mask)
	783	s += '#define SEG_XCU_SIZE 0x%x\n' % xcu_size
	784	s += '\n'
	785	s += '#define SEG_RDK_BASE 0x%x\n' % (rdk_base & local_physical_mask)
	786	s += '#define SEG_RDK_SIZE 0x%x\n' % rdk_size
	787	s += '\n'
	788	s += '#define SEG_DROM_BASE 0x%x\n' % (drom_base & local_physical_mask)
	789	s += '#define SEG_DROM_SIZE 0x%x\n' % drom_size
	790	s += '\n'
	791	s += '#endif\n'
	792
	793	return s
	794
	795	# end of hard_config()
	796
	797
	798
	799
	800
	801	###################################################################################
	802	class Cluster ( object ):
	803	###################################################################################
	804	def __init__( self,
	805	cxy ):
	806
	807	self.index = 0 # global index (set by Archinfo constructor)
	808	self.cxy = cxy # cluster identifier
	809	self.cores = [] # local cores (filled by addCore)
	810	self.devices = [] # local devices(filled by addDevice)
	811
	812	return
	813
	814	################
	815	def xml( self ): # xml for a cluster
	816
	817	s = ' <cluster cxy = "%x" >\n' % (self.cxy)
	818	for core in self.cores: s += core.xml()
	819	for device in self.devices: s += device.xml()
	820	s += ' </cluster>\n'
	821
	822	return s
	823
	824	#############################################
	825	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
	826
	827	if ( verbose ):
	828	print '*** cbin for cluster[%d] / identifier = %x' \
	829	% (self.index , self.cxy)
	830
	831	# check index
	832	if (self.index != expected):
	833	print '[genarch error] in Cluster.cbin()'
	834	print ' cluster global index = %d / expected = %d' \
	835	% (self.index,expected)
	836	sys.exit(1)
	837
	838	# compute global index for first core in cluster
	839	if ( len(self.cores) > 0 ):
	840	core_id = self.cores[0].index
	841	else:
	842	core_id = 0
	843
	844	# compute global index for first device in cluster
	845	if ( len(self.devices) > 0 ):
	846	device_id = self.devices[0].index
	847	else:
	848	device_id = 0
	849
	850	byte_stream = bytearray()
	851	byte_stream += mapping.int2bytes(4,self.cxy) # cxy
	852	byte_stream += mapping.int2bytes(4,len(self.cores)) # cores in cluster
	853	byte_stream += mapping.int2bytes(4,core_id ) # first core global index
	854	byte_stream += mapping.int2bytes(4,len(self.devices)) # devices in cluster
	855	byte_stream += mapping.int2bytes(4, device_id ) # first device global index
	856
	857	if ( verbose ):
	858	print 'nb_cores = %d' % len( self.cores )
	859	print 'core_id = %d' % core_id
	860	print 'nb_devices = %d' % len( self.devices )
	861	print 'device_id = %d' % device_id
	862
	863	return byte_stream
	864
	865
	866
	867
	868	##################################################################################
	869	class Core ( object ):
	870	##################################################################################
	871	def __init__( self,
	872	gid,
	873	cxy,
	874	lid ):
	875
	876	self.index = 0 # global index / set by addProc()
	877	self.gid = gid # hardware identifier
	878	self.cxy = cxy # cluster identifier
	879	self.lid = lid # local index in cluster
	880
	881	return
	882
	883	###################################
	884	def xml( self ): # xml for a core
	885	return ' <core gid="%x" lid="%d" />\n' % (self.gid, self.lid)
	886
	887	####################################################################
	888	def cbin( self, mapping, verbose, expected ): # C binary for Proc
	889
	890	if ( verbose ):
	891	print '*** cbin for core [%d] in cluster %x' \
	892	% (self.lid, self.cxy)
	893
	894	# check index
	895	if (self.index != expected):
	896	print '[genarch error] in Core.cbin()'
	897	print ' core global index = %d / expected = %d' \
	898	% (self.index,expected)
	899	sys.exit(1)
	900
	901	byte_stream = bytearray()
	902	byte_stream += mapping.int2bytes( 4 , self.gid ) # hardware identifier
	903	byte_stream += mapping.int2bytes( 2 , self.cxy ) # cluster identifier
	904	byte_stream += mapping.int2bytes( 2 , self.lid ) # local index
	905
	906	return byte_stream
	907
	908
	909
	910
	911	##################################################################################
	912	class Device ( object ):
	913	##################################################################################
	914	def __init__( self,
	915	base,
	916	size,
	917	ptype,
	918	channels = 1,
	919	arg0 = 0,
	920	arg1 = 0,
	921	arg2 = 0,
	922	arg3 = 0 ):
	923
	924	self.index = 0 # global device index ( set by addDevice() )
	925	self.base = base # associated segment base
	926	self.size = size # associated segment size (bytes)
	927	self.ptype = ptype # device type
	928	self.channels = channels # number of channels
	929	self.arg0 = arg0 # optional (semantic depends on ptype)
	930	self.arg1 = arg1 # optional (semantic depends on ptype)
	931	self.arg2 = arg2 # optional (semantic depends on ptype)
	932	self.arg3 = arg3 # optional (semantic depends on ptype)
	933	self.irqs = [] # set of input IRQs (for PIC and XCU only)
	934	self.irq_ctrl = None # interrupt controller for this device
	935	return
	936
	937	######################################
	938	def xml( self ): # xml for a device
	939
	940	s = ' <device type="%s"' % self.ptype
	941	s += ' base="%x"' % self.base
	942	s += ' size="%x"' % self.size
	943	s += ' channels="%d"' % self.channels
	944	s += ' arg0="%d"' % self.arg0
	945	s += ' arg1="%d"' % self.arg1
	946	s += ' arg2="%d"' % self.arg2
	947	s += ' arg3="%d"' % self.arg3
	948	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') ):
	949	s += ' >\n'
	950	for irq in self.irqs: s += irq.xml()
	951	s += ' </device>\n'
	952	else:
	953	s += ' />\n'
	954	return s
	955
	956	######################################################################
	957	def cbin( self, mapping, verbose, expected ): # C binary for Periph
	958
	959	if ( verbose ):
	960	print '*** cbin for device[%d] / type %s' \
	961	% (self.index , self.ptype)
	962
	963	# check index
	964	if (self.index != expected):
	965	print '[genarch error] in Periph.cbin()'
	966	print ' device global index = %d / expected = %d' \
	967	% (self.index,expected)
	968	sys.exit(1)
	969
	970	# compute first irq global index
	971	if ( len(self.irqs) > 0 ):
	972	irq_id = self.irqs[0].index
	973	else:
	974	irq_id = 0
	975
	976	# compute device type numerical value
	977	ptype_id = 0xFFFFFFFF
	978	for x in xrange( len(DEVICE_TYPES_STR) ):
	979	if ( self.ptype == DEVICE_TYPES_STR[x] ): ptype_id = DEVICE_TYPES_INT[x]
	980
	981	if ( ptype_id == 0xFFFFFFFF ):
	982	print '[genarch error] in Device.cbin()'
	983	print ' undefined device type %s' % self.ptype
	984	sys.exit(1)
	985
	986	byte_stream = bytearray()
	987	byte_stream += mapping.int2bytes(4,ptype_id) # device type
	988	byte_stream += mapping.int2bytes(8,self.base) # segment base address
	989	byte_stream += mapping.int2bytes(8,self.size) # segment size
	990	byte_stream += mapping.int2bytes(4,self.channels) # number of channels
	991	byte_stream += mapping.int2bytes(4,self.arg0) # optionnal arg0
	992	byte_stream += mapping.int2bytes(4,self.arg1) # optionnal arg1
	993	byte_stream += mapping.int2bytes(4,self.arg2) # optionnal arg2
	994	byte_stream += mapping.int2bytes(4,self.arg3) # optionnal arg3
	995	byte_stream += mapping.int2bytes(4,len(self.irqs)) # number of input irqs
	996	byte_stream += mapping.int2bytes(4 ,irq_id) # first irq global index
	997
	998	if ( verbose ):
	999	print 'ptype = %d' % ptype_id
	1000	print 'base = %x' % self.base
	1001	print 'size = %x' % self.size
	1002	print 'nb_irqs = %d' % len( self.irqs )
	1003	print 'irq_id = %d' % irq_id
	1004
	1005	return byte_stream
	1006
	1007	##################################################################################
	1008	class Irq ( object ):
	1009	##################################################################################
	1010	def __init__( self,
	1011	port,
	1012	dev,
	1013	channel,
	1014	is_rx ):
	1015
	1016	assert port < 32
	1017
	1018	self.index = 0 # global index ( set by addIrq() )
	1019	self.port = port # input IRQ port index
	1020	self.dev = dev # source device
	1021	self.channel = channel # source device channel
	1022	self.is_rx = is_rx # source device direction
	1023
	1024	return
	1025
	1026	################################
	1027	def xml( self ): # xml for Irq
	1028	s = ' <irq port="%d" devtype="%s" channel="%d" is_rx="%d" />\n' \
	1029	% ( self.port, self.dev.ptype, self.channel, self.is_rx )
	1030	return s
	1031
	1032	####################################################################
	1033	def cbin( self, mapping, verbose, expected ): # C binary for Irq
	1034
	1035	if ( verbose ):
	1036	print '*** cbin for irq[%d] / type = %s' \
	1037	% (self.index , self.isrtype)
	1038
	1039	# check index
	1040	if (self.index != expected):
	1041	print '[genarch error] in Irq.cbin()'
	1042	print ' irq global index = %d / expected = %d' \
	1043	% (self.index,expected)
	1044	sys.exit(1)
	1045
	1046	# compute source device type numerical value
	1047	dev_id = 0xFFFFFFFF
	1048	for x in xrange( len(DEVICE_TYPES_STR) ):
	1049	if ( self.dev.ptype == DEVICE_TYPES_STR[x] ): dev_id = DEVICE_TYPES_INT[x]
	1050
	1051	if ( dev_id == 0xFFFFFFFF ):
	1052	print '[genarch error] in Irq.cbin()'
	1053	print ' undefined device type %s' % self.dev.ptype
	1054	sys.exit(1)
	1055
	1056	byte_stream = bytearray()
	1057	byte_stream += mapping.int2bytes( 4, dev_id )
	1058	byte_stream += mapping.int2bytes( 1, self.channel )
	1059	byte_stream += mapping.int2bytes( 1, self.is_rx )
	1060	byte_stream += mapping.int2bytes( 1, self.port )
	1061	byte_stream += mapping.int2bytes( 1, 0 )
	1062
	1063	if ( verbose ):
	1064	print 'dev_id = %d' % dev_id
	1065	print 'channel = %d' % self.channel
	1066	print 'is_rx = %d' % self.is_rx
	1067	print 'port = %s' % self.port
	1068
	1069	return byte_stream
	1070
	1071	# Local Variables:
	1072	# tab-width: 4;
	1073	# c-basic-offset: 4;
	1074	# c-file-offsets:((innamespace . 0)(inline-open . 0));
	1075	# indent-tabs-mode: nil;
	1076	# End:
	1077	#
	1078	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
	1079

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