Changeset 137 for trunk/hal/x86_64/core


Ignore:
Timestamp:
Jul 4, 2017, 10:17:44 AM (5 years ago)
Author:
max@…
Message:

improve the APIC implementation

Location:
trunk/hal/x86_64/core
Files:
4 edited

Legend:

Unmodified
Added
Removed
  • trunk/hal/x86_64/core/hal_apic.c

    r135 r137  
    132132#define IOAPICVER       0x01
    133133#define IOAPICARB       0x02
     134
    134135#define IOREDTBL        0x10
     136#       define IOREDTBL_DEL_FIXED       0x000
     137#       define IOREDTBL_DEL_LOPRI       0x100
     138#       define IOREDTBL_DEL_SMI         0x200
     139#       define IOREDTBL_DEL_NMI         0x400
     140#       define IOREDTBL_DEL_INIT        0x500
     141#       define IOREDTBL_DEL_EXTINT      0x700
     142#       define IOREDTBL_DEM_PHYS        0x000
     143#       define IOREDTBL_DEM_LOGIC       0x800
     144#       define IOREDTBL_DES_SHIFT       56
     145#       define IOREDTBL_MSK             0x10000
    135146
    136147void hal_ioapic_write(uint8_t reg, uint32_t val)
     
    146157}
    147158
    148 void hal_ioapic_set_entry(uint8_t index, uint64_t data)
    149 {
     159void hal_ioapic_disable_entry(uint8_t index)
     160{
     161        const uint64_t data = IOREDTBL_MSK;
     162
    150163        hal_ioapic_write(IOREDTBL + index * 2, (uint32_t)(data & 0xFFFFFFFF));
    151164        hal_ioapic_write(IOREDTBL + index * 2 + 1, (uint32_t)(data >> 32));
    152165}
    153166
     167void hal_ioapic_set_entry(uint8_t index, uint8_t vec, uint8_t dest)
     168{
     169        const uint64_t data = ((uint64_t)dest << IOREDTBL_DES_SHIFT) |
     170            IOREDTBL_DEM_PHYS | IOREDTBL_DEL_FIXED | vec;
     171
     172        hal_ioapic_write(IOREDTBL + index * 2, (uint32_t)(data & 0xFFFFFFFF));
     173        hal_ioapic_write(IOREDTBL + index * 2 + 1, (uint32_t)(data >> 32));
     174}
     175
    154176static void hal_ioapic_init()
    155177{
     
    166188        /* Explicitly disable (mask) each vector */
    167189        for (i = 0; i < ioapic_pins; i++) {
    168                 hal_ioapic_set_entry(i, IOENTRY_DISABLE);
     190                hal_ioapic_disable_entry(i);
    169191        }
    170192
     
    172194
    173195        /* Now, enable the keyboard */
    174         hal_ioapic_set_entry(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR);
     196        hal_ioapic_set_entry(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR, 0);
    175197}
    176198
  • trunk/hal/x86_64/core/hal_apic.h

    r135 r137  
    2121
    2222#ifndef x86_ASM
    23 void hal_ioapic_set_entry(uint8_t index, uint64_t data);
     23void hal_ioapic_disable_entry(uint8_t index);
     24void hal_ioapic_set_entry(uint8_t index, uint8_t vec, uint8_t dest);
    2425
    2526uint32_t hal_lapic_gid();
     
    3334 */
    3435
    35 #define IOENTRY_DISABLE 0x10000
     36
    3637
    3738
  • trunk/hal/x86_64/core/hal_drivers.c

    r136 r137  
    4343    uint32_t irq_type, lid_t lid)
    4444{
    45         soclib_xcu_disable_irq(icu, 1 << irq_index, irq_type, lid);
     45        soclib_xcu_disable_irq(icu, irq_index, irq_type, lid);
    4646}
    4747
     
    4949    uint32_t irq_type, lid_t lid)
    5050{
    51         soclib_xcu_enable_irq(icu, 1 << irq_index, irq_type, lid);
     51        soclib_xcu_enable_irq(icu, irq_index, irq_type, lid);
    5252}
    5353
  • trunk/hal/x86_64/core/hal_init.c

    r135 r137  
    8484static void init_bootinfo_icu(boot_device_t *dev)
    8585{
     86        extern uint32_t hwi_baseidx;
     87        extern uint32_t wti_baseidx;
     88        extern uint32_t pti_baseidx;
     89        extern size_t ioapic_pins;
     90
    8691        memset(dev, 0, sizeof(boot_device_t));
    8792
    88         dev->base = NULL; /* XXX */
     93        dev->base = 0;
    8994        dev->type = (DEV_FUNC_ICU << 16) | IMPL_ICU_XCU;
    9095        dev->channels = 1;
    91         dev->param0 = 0;
    92         dev->param1 = 0;
    93         dev->param2 = 0;
     96
     97        /*
     98         * Give 20% of the pins to HWI, 80% to WTI.
     99         */
     100        dev->param0 = (ioapic_pins * 20) / 100;  /* hwi_nr */
     101        dev->param1 = ioapic_pins - dev->param0; /* wti_nr */
     102
     103        /*
     104         * We always set 1 for pti_nr. On x86, timer interrupts are handled by
     105         * LAPIC, which is per-cpu and not global. Therefore, we always have one
     106         * timer for each CPU, and its IRQ number is faked to 0.
     107         */
     108        dev->param2 = 1; /* pti_nr */
     109
    94110        dev->param3 = 0;
     111
     112        /* Set the base idx for the XCU driver */
     113        hwi_baseidx = 0;
     114        wti_baseidx = dev->param0;
     115        pti_baseidx = 0xFFFFFFFF;
    95116
    96117#ifdef NOTYET
     
    132153        size_t i, rsvd_nr;
    133154
    134         memset(rsvd, 0, sizeof(boot_rsvd_t));
     155        memset(rsvd, 0, sizeof(boot_rsvd_t) * CONFIG_PPM_MAX_RSVD);
    135156
    136157        i = 0, rsvd_nr = 0;
     
    208229        init_bootinfo_core(&info->core[0]);
    209230
    210         info->rsvd_nr = init_bootinfo_rsvd(&info->rsvd);
     231        info->rsvd_nr = init_bootinfo_rsvd((boot_rsvd_t *)&info->rsvd);
    211232
    212233        init_bootinfo_icu(&info->dev_icu);
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