Changeset 16 for trunk/hal

Timestamp:

May 10, 2017, 5:04:01 PM (7 years ago)

Author:

alain

Message:

mprove the HAL for interrupt, exception, syscall handling.

Location:

trunk/hal

Files:

• generic (added)
• generic/hal_atomic.h (moved) (moved from trunk/hal/tsar_mips32/hal_atomic.h) (1 diff)
• generic/hal_context.h (moved) (moved from trunk/hal/tsar_mips32/hal_context.h)
• generic/hal_exception.h (added)
• generic/hal_gpt.h (moved) (moved from trunk/hal/tsar_mips32/hal_gpt.h)
• generic/hal_interrupt.h (added)
• generic/hal_irqmask.h (moved) (moved from trunk/hal/tsar_mips32/hal_irqmask.h)
• generic/hal_remote.h (moved) (moved from trunk/hal/tsar_mips32/hal_remote.h)
• generic/hal_special.h (moved) (moved from trunk/hal/tsar_mips32/hal_special.h) (1 diff)
• generic/hal_syscall.h (added)
• generic/hal_uspace.h (moved) (moved from trunk/hal/tsar_mips32/hal_uspace.h)
• i386/hal_types.h (modified) (1 diff)
• tsar_mips32/hal_exception.c (added)
• tsar_mips32/hal_interrupt.c (added)
• tsar_mips32/hal_kentry.S (added)
• tsar_mips32/hal_kentry.h (added)
• tsar_mips32/hal_special.c (modified) (2 diffs)
• tsar_mips32/hal_syscall.c (added)
• tsar_mips32/hal_types.h (modified) (3 diffs)
• tsar_mips32/mips32_context.h (added)
• tsar_mips32/mips32_uzone.h (added)

trunk/hal/generic/hal_atomic.h

@@ -25 +25 @@
 #define  _HAL_ATOMIC_H_
 
-#include <almos_config.h>
+#include <kernel_config.h>
 #include <hal_types.h>
 

trunk/hal/generic/hal_special.h

@@ -116 +116 @@
 void hal_fixed_delay();
 
+/*****************************************************************************************
+ * This function returns informations on MMU exceptions :
+ * @ mmu_ins_excp_code : [out] instruction fetch exception code
+ * @ mmu_ins_bad_vaddr : [out] instruction fetch faulty virtual address
+ * @ mmu_dat_excp_code : [out] data access exception code
+ * @ mmu_dat_bad_vaddr : [out] data access faulty virtual address
+ ****************************************************************************************/
+void hal_get_mmu_excp( intptr_t * mmu_ins_excp_code,
+                       intptr_t * mmu_ins_bad_vaddr,
+                       intptr_t * mmu_dat_excp_code,
+                       intptr_t * mmu_dat_bad_vaddr );
 
 

trunk/hal/i386/hal_types.h

@@ -25 +25 @@
 #define HAL_TYPES_H_
 
-#include <almos_config.h>
+#include <kernel_config.h>
 #include <stdint.h>
 

trunk/hal/tsar_mips32/hal_special.c

@@ -38 +38 @@
         asm volatile ("mfc0    %0,  $15, 1" : "=&r" (proc_id));
 
-        return (proc_id & 0xFFF);  // at most 4096 cores...
+        return (proc_id & 0x3FF);  // 4/4/2 format for TSAR
 }
 
@@ -186 +186 @@
 }
 
-
-
-
+//////////////////////////////////////////////////
+void hal_get_mmu_excp( intptr_t * mmu_ins_excp_code,
+                       intptr_t * mmu_ins_bad_vaddr,
+                       intptr_t * mmu_dat_excp_code,
+                       intptr_t * mmu_dat_bad_vaddr )
+{
+    asm volatile
+    ( "mfc2   %0,    $11        \n"
+      "mfc2   %1,    $13        \n"
+      "mfc2   %2,    $12        \n"
+      "mfc2   %3,    $14        \n"
+      : "=&r"(mmu_ins_excp_code),
+        "=&r"(mmu_ins_bad_vaddr),
+        "=&r"(mmu_dat_excp_code),
+        "=&r"(mmu_dat_bad_vaddr) );
+}

trunk/hal/tsar_mips32/hal_types.h

@@ -25 +25 @@
 #define HAL_TYPES_H_
 
-#include <almos_config.h>
+#include <kernel_config.h>
 
 #ifndef NULL
@@ -81 +81 @@
  **************************************************************************/
 
-typedef uint64_t      clock_t;   // for cycle counters
+typedef uint64_t      cycle_t;   // for cycle counters
 
 /***************************************************************************
@@ -144 +144 @@
 __attribute__((packed)) cacheline_t;
 
-#define CACHELINE_ALIGNED __attribute__((aligned(CONFIG_CACHE_LINE_SIZE)))
-
 /***************************************************************************
  *  Address types and macros         !!!  hardware dependant  !!!