Changeset 188 for trunk/hal/tsar_mips32/drivers/soclib_pic.c
- Timestamp:
- Jul 12, 2017, 8:12:41 PM (7 years ago)
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- 1 edited
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trunk/hal/tsar_mips32/drivers/soclib_pic.c
r141 r188 2 2 * soclib_pic.c - soclib PIC driver implementation. 3 3 * 4 * Author Alain Greiner (2016 )4 * Author Alain Greiner (2016,2017) 5 5 * 6 6 * Copyright (c) UPMC Sorbonne Universites … … 25 25 #include <chdev.h> 26 26 #include <soclib_pic.h> 27 #include <soclib_xcu.h>28 27 #include <errno.h> 29 28 #include <string.h> 30 29 #include <vfs.h> 30 #include <cluster.h> 31 #include <printk.h> 32 #include <core.h> 33 #include <thread.h> 34 35 ////////////////////////////////////////////////////////////////////////////////////// 36 // Extern variables 37 ////////////////////////////////////////////////////////////////////////////////////// 38 39 extern chdev_directory_t chdev_dir; // defined in chdev.h / allocated in kerneL-init.c 40 41 extern iopic_input_t iopic_input; // defined in dev_pic.h / allocated in kernel_init.c 42 extern lapic_input_t lapic_input; // defined in dev_pic.h / allocated in kernel_init.c 43 44 ////////////////////////////////////////////////////////////////////////////////////// 45 // SOCLIB PIC private functions 46 ////////////////////////////////////////////////////////////////////////////////////// 47 48 /////////////////////////////// 49 uint32_t soclib_pic_wti_alloc() 50 { 51 uint32_t index; 52 53 // get pointer on cluster extension for SOCLIB PIC (XCU descriptor) 54 soclib_pic_cluster_t * ext_ptr = LOCAL_CLUSTER->pic_extend; 55 56 assert( (ext_ptr->first_free_wti < ext_ptr->wti_nr) , __FUNCTION__ , 57 "no free WTI found : too much external IRQs\n"); 58 59 // update WTI allocator 60 index = ext_ptr->first_free_wti; 61 ext_ptr->first_free_wti++; 62 63 return index; 64 65 } // end soclib_pic_wti_alloc() 66 67 /////////////////////////////////////// 68 inline uint32_t * soclib_pic_xcu_base() 69 { 70 return ((soclib_pic_cluster_t *)LOCAL_CLUSTER->pic_extend)->xcu_base; 71 72 } // end soclib_pic_xcu_base() 73 74 75 ////////////////////////////////////////// 76 uint32_t soclib_pic_ack_timer( lid_t lid ) 77 { 78 // get local XCU segment base 79 uint32_t * base = soclib_pic_xcu_base(); 80 81 // read from register 82 return base[(XCU_PTI_ACK << 5) | lid]; 83 84 } // end soclib_pic_ack_timer() 85 86 /////////////////////////////////////////// 87 void soclib_pic_xcu_status( lid_t lid, 88 uint32_t * hwi_status, 89 uint32_t * wti_status, 90 uint32_t * pti_status ) 91 { 92 // get local XCU segment base 93 uint32_t * base = soclib_pic_xcu_base(); 94 95 // read PRIO register 96 uint32_t prio = base[(XCU_PRIO << 5) | lid]; 97 98 *wti_status = (prio & 0x4) ? (((prio >> 24) & 0x1F) + 1) : 0; 99 *hwi_status = (prio & 0x2) ? (((prio >> 16) & 0x1F) + 1) : 0; 100 *pti_status = (prio & 0x1) ? (((prio >> 8) & 0x1F) + 1) : 0; 101 102 } 103 104 ///////////////////////////// 105 void soclib_pic_irq_handler() 106 { 107 uint32_t hwi_status; // HWI index + 1 / no pending HWI if 0 108 uint32_t wti_status; // WTI index + 1 / no pending WTI if 0 109 uint32_t pti_status; // PTI index + 1 / no pending PTI if 0 110 chdev_t * src_chdev; // pointer on source chdev descriptor 111 uint32_t index; // IRQ index 112 113 core_t * core = CURRENT_THREAD->core; 114 115 // get XCU status 116 soclib_pic_xcu_status( core->lid, 117 &hwi_status, 118 &wti_status, 119 &pti_status ); 120 121 // analyse status and handle up to 3 pending IRQ (one WTI, one HWI, one PTI) 122 123 if( wti_status ) // pending WTI 124 { 125 index = wti_status - 1; 126 127 if( index < LOCAL_CLUSTER->cores_nr ) // it is an IPI 128 { 129 assert( (index == core->lid) , __FUNCTION__ , "illegal IPI index" ); 130 131 // TODO acknowledge WTI [AG] 132 133 // TODO force scheduling [AG] 134 } 135 else // it is an external device 136 { 137 // get pointer on source chdev 138 src_chdev = ((soclib_pic_core_t *)core->pic_extend)->wti_vector[index]; 139 140 if( src_chdev == NULL ) // strange, but not fatal 141 { 142 printk("\n[WARNING] in %s : no handler for WTI %d on core %d in cluster %x\n", 143 __FUNCTION__ , index , core->lid , local_cxy ); 144 145 core->spurious_irqs ++; 146 147 // TODO disable this WTI in local XCU [AG] 148 } 149 else // call relevant ISR 150 { 151 irq_dmsg("\n[INFO] %s received WTI : index = %d for core %d in cluster %d\n", 152 __FUNCTION__ , index , core->lid , local_cxy ); 153 154 // call ISR 155 src_chdev->isr( src_chdev ); 156 } 157 } 158 } 159 160 if( hwi_status ) // pending HWI 161 { 162 index = hwi_status - 1; 163 164 // get pointer on source chdev 165 src_chdev = ((soclib_pic_core_t *)core->pic_extend)->hwi_vector[index]; 166 167 if( src_chdev == NULL ) // strange, but not fatal 168 { 169 printk("\n[WARNING] in %s : no handler for HWI %d on core %d in cluster %x\n", 170 __FUNCTION__ , index , core->lid , local_cxy ); 171 172 core->spurious_irqs ++; 173 174 // TODO disable this HWI in local XCU [AG] 175 } 176 else // call relevant ISR 177 { 178 irq_dmsg("\n[INFO] %s received HWI : index = %d for core %d in cluster %d\n", 179 __FUNCTION__ , index , core->lid , local_cxy ); 180 181 // call ISR 182 src_chdev->isr( src_chdev ); 183 } 184 } 185 186 if( pti_status ) // pending PTI 187 { 188 index = pti_status - 1; 189 190 irq_dmsg("\n[INFO] %s received PTI : index = %d for cpu %d in cluster %d\n", 191 __FUNCTION__ , index , core->lid , local_cxy ); 192 193 assert( (index == core->lid) , __FUNCTION__ , "unconsistent PTI index\n"); 194 195 // acknowledge PTI 196 soclib_pic_ack_timer( index ); 197 198 // TODO execute all actions related to TICK event 199 core_clock( core ); 200 } 201 } // end soclib_pic_irq_handler() 202 203 204 205 206 ////////////////////////////////////////////////////////////////////////////////////// 207 // SOCLIC PIC device generic API 208 ////////////////////////////////////////////////////////////////////////////////////// 209 210 ///////////////////////////////////// 211 void soclib_pic_init( chdev_t * pic ) 212 { 213 uint32_t i; // for loop on IOPIC inputs 214 uint32_t x; // for loop on clusters in a row 215 uint32_t y; // for loop on clusters in a column inputs 216 uint32_t lid; // for loop on cores in a cluster 217 218 // get target architecture parameters 219 cluster_t * cluster = LOCAL_CLUSTER; 220 uint32_t x_size = cluster->x_size; 221 uint32_t y_size = cluster->y_size; 222 uint32_t y_width = cluster->y_width; 223 uint32_t ncores = cluster->cores_nr; 224 225 // get IOPIC controller cluster and segment base pointer 226 cxy_t iopic_seg_cxy = (cxy_t)GET_CXY( pic->base ); 227 uint32_t * iopic_seg_ptr = (uint32_t *)GET_PTR( pic->base ); 228 229 // reset the IOPIC component registers : mask all input IRQs 230 for( i = 0 ; i < CONFIG_MAX_EXTERNAL_IRQS ; i++ ) 231 { 232 xptr_t iopic_seg_xp = XPTR( iopic_seg_cxy, 233 iopic_seg_ptr + i*IOPIC_SPAN + IOPIC_MASK ); 234 hal_remote_sw( iopic_seg_xp , 0 ); 235 } 236 237 // GET XCU controller segment base 238 uint32_t * base = soclib_pic_xcu_base(); 239 240 // reset the XCU component registers in all clusters: 241 // mask all HWIs, all WTIs, and all PTIs, for all cores 242 for( x = 0 ; x < x_size ; x++ ) 243 { 244 for( y = 0 ; y < y_size ; y++ ) 245 { 246 for( lid = 0 ; lid < ncores ; lid++ ) 247 { 248 cxy_t cxy = (x<<y_width) + y; 249 xptr_t hwi_mask_xp = XPTR( cxy , base + (XCU_MSK_HWI_DISABLE << 5 | lid) ); 250 xptr_t wti_mask_xp = XPTR( cxy , base + (XCU_MSK_WTI_DISABLE << 5 | lid) ); 251 xptr_t pti_mask_xp = XPTR( cxy , base + (XCU_MSK_PTI_DISABLE << 5 | lid) ); 252 hal_remote_sw( hwi_mask_xp , 0xFFFFFFFF ); 253 hal_remote_sw( wti_mask_xp , 0xFFFFFFFF ); 254 hal_remote_sw( pti_mask_xp , 0xFFFFFFFF ); 255 } 256 } 257 } 258 } // end soclib_pic_init() 259 260 ////////////////////////////////////////////////// 261 void soclib_pic_extend_init( uint32_t * xcu_base ) 262 { 263 soclib_pic_cluster_t * cluster_ext_ptr; 264 soclib_pic_core_t * core_ext_ptr; 265 kmem_req_t req; 266 uint32_t lid; 267 uint32_t idx; 268 269 cluster_t * cluster = LOCAL_CLUSTER; 270 271 // create core extension for all cores in cluster 272 for( lid = 0 ; lid < cluster->cores_nr ; lid++ ) 273 { 274 // allocate memory for core extension 275 req.type = KMEM_GENERIC; 276 req.size = sizeof(soclib_pic_core_t); 277 req.flags = AF_KERNEL; 278 core_ext_ptr = kmem_alloc( &req ); 279 280 assert( (core_ext_ptr != NULL) , __FUNCTION__ , 281 "cannot allocate memory for core extension\n"); 282 283 // reset the HWI / WTI interrupt vectors 284 for( idx = 0 ; idx < SOCLIB_MAX_HWI ; idx++ ) core_ext_ptr->hwi_vector[idx] = NULL; 285 for( idx = 0 ; idx < SOCLIB_MAX_WTI ; idx++ ) core_ext_ptr->wti_vector[idx] = NULL; 286 287 // register PIC extension in core descriptor 288 cluster->core_tbl[lid].pic_extend = core_ext_ptr; 289 } 290 291 // allocate memory for cluster extension 292 req.type = KMEM_GENERIC; 293 req.size = sizeof(soclib_pic_cluster_t); 294 req.flags = AF_KERNEL; 295 cluster_ext_ptr = kmem_alloc( &req ); 296 297 assert( (cluster_ext_ptr != NULL) , __FUNCTION__ , 298 "cannot allocate memory for cluster extension\n"); 299 300 // get XCU characteristics from the XCU config register 301 uint32_t config = xcu_base[XCU_CONFIG<<5]; 302 uint32_t wti_nr = (config >> 16) & 0xFF; 303 uint32_t hwi_nr = (config >> 8 ) & 0xFF; 304 uint32_t pti_nr = (config ) & 0xFF; 305 306 // initialize the cluster extension 307 // The first WTI slots are for IPIs (one slot per core) 308 cluster_ext_ptr->xcu_base = xcu_base; 309 cluster_ext_ptr->hwi_nr = hwi_nr; 310 cluster_ext_ptr->wti_nr = wti_nr; 311 cluster_ext_ptr->pti_nr = pti_nr; 312 cluster_ext_ptr->first_free_wti = cluster->cores_nr; 313 314 // register PIC extension in cluster manager 315 cluster->pic_extend = cluster_ext_ptr; 316 317 } // end soclib_pic_extend_init() 31 318 32 319 //////////////////////////////////////// 33 void soclib_pic_init( chdev_t * chdev ) 34 { 35 // get PIC controller segment cluster and local pointer 36 cxy_t seg_cxy = (cxy_t)GET_CXY( chdev->base ); 37 uint32_t * seg_ptr = (uint32_t *)GET_PTR( chdev->base ); 38 uint32_t i; 39 40 // reset the MASK registers for all input IRQs 41 for( i = 0 ; i < CONFIG_MAX_IRQS_PER_PIC ; i++ ) 42 { 43 hal_remote_sw( XPTR( seg_cxy , seg_ptr + i*IOPIC_SPAN + IOPIC_MASK ) , 0 ); 44 } 320 void soclib_pic_bind_irq( lid_t lid, 321 chdev_t * src_chdev ) 322 { 323 // get extended & local pointers on PIC chdev descriptor 324 xptr_t pic_xp = chdev_dir.pic; 325 cxy_t pic_cxy = GET_CXY( pic_xp ); 326 chdev_t * pic_ptr = (chdev_t *)GET_PTR( pic_xp ); 327 328 // get extended and local pointers on IOPIC segment base 329 xptr_t seg_pic_xp = hal_remote_lwd( XPTR( pic_cxy , &pic_ptr->base ) ); 330 cxy_t seg_pic_cxy = GET_CXY( seg_pic_xp ); 331 uint32_t * seg_pic_ptr = (uint32_t *)GET_PTR( seg_pic_xp ); 332 333 // get local pointer on XCU segment base 334 uint32_t * seg_xcu_ptr = soclib_pic_xcu_base(); 335 336 // get the source chdev functionnal type, channel, and direction 337 uint32_t func = src_chdev->func; 338 uint32_t channel = src_chdev->channel; 339 bool_t is_rx = src_chdev->is_rx; 340 341 if( (func == DEV_FUNC_IOC) || (func == DEV_FUNC_NIC) || 342 (func == DEV_FUNC_TXT) || (func == DEV_FUNC_IOB) ) // external IRQ => WTI 343 { 344 // get external IRQ index 345 uint32_t irq_id; 346 if ( func == DEV_FUNC_IOC ) irq_id = iopic_input.ioc[channel]; 347 else if( func == DEV_FUNC_TXT ) irq_id = iopic_input.txt[channel]; 348 else if( (func == DEV_FUNC_NIC) && is_rx ) irq_id = iopic_input.nic_rx[channel]; 349 else if( (func == DEV_FUNC_NIC) && !is_rx ) irq_id = iopic_input.nic_tx[channel]; 350 else if( func == DEV_FUNC_IOB ) irq_id = iopic_input.iob; 351 else assert( false , __FUNCTION__ , "illegal device functionnal type\n"); 352 353 // get a WTI mailbox from local XCU descriptor 354 uint32_t wti_id = soclib_pic_wti_alloc(); 355 356 // register IRQ type and index in chdev 357 src_chdev->irq_type = SOCLIB_TYPE_WTI; 358 src_chdev->irq_id = wti_id; 359 360 // compute extended pointer on WTI mailbox in local XCU 361 xptr_t wti_xp = XPTR( local_cxy , &seg_xcu_ptr[(XCU_WTI_REG << 5) | wti_id] ); 362 363 // set the IOPIC_ADDRESS and IOPIC_EXTEND registers in IOPIC 364 uint32_t lsb_wdata = (uint32_t)wti_xp; 365 uint32_t msb_wdata = (uint32_t)(wti_xp >> 32); 366 xptr_t lsb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+irq_id*IOPIC_SPAN+IOPIC_ADDRESS ); 367 xptr_t msb_xp = XPTR( seg_pic_cxy , seg_pic_ptr+irq_id*IOPIC_SPAN+IOPIC_EXTEND ); 368 hal_remote_sw( lsb_xp , lsb_wdata ); 369 hal_remote_sw( msb_xp , msb_wdata ); 370 371 // unmask IRQ in IOPIC 372 hal_remote_sw( XPTR( seg_pic_cxy , seg_pic_ptr+irq_id*IOPIC_SPAN+IOPIC_MASK ), 1 ); 373 374 // update the WTI interrupt vector for core[lid] 375 core_t * core = &LOCAL_CLUSTER->core_tbl[lid]; 376 ((soclib_pic_core_t *)core->pic_extend)->wti_vector[wti_id] = src_chdev; 377 } 378 else if( (func == DEV_FUNC_DMA) || (func == DEV_FUNC_MMC) ) // internal IRQ => HWI 379 { 380 // get internal IRQ index 381 uint32_t hwi_id; 382 if( func == DEV_FUNC_DMA ) hwi_id = lapic_input.dma[channel]; 383 else hwi_id = lapic_input.mmc; 384 385 // register IRQ type and index in chdev 386 src_chdev->irq_type = SOCLIB_TYPE_HWI; 387 src_chdev->irq_id = hwi_id; 388 389 // update the HWI interrupt vector for core[lid] 390 core_t * core = &LOCAL_CLUSTER->core_tbl[lid]; 391 ((soclib_pic_core_t *)core->pic_extend)->wti_vector[hwi_id] = src_chdev; 392 } 393 else 394 { 395 assert( false , __FUNCTION__ , "illegal device functionnal type\n" ); 396 } 397 } // end soclib_pic_bind_irq(); 398 399 ////////////////////////////////////////// 400 void soclib_pic_enable_irq( lid_t lid, 401 chdev_t * src_chdev ) 402 { 403 // get local pointer on XCU segment base 404 uint32_t * seg_xcu_ptr = soclib_pic_xcu_base(); 405 406 // get the source chdev IRQ type and index 407 uint32_t irq_type = src_chdev->irq_type; 408 uint32_t irq_id = src_chdev->irq_id; 409 410 if( irq_type == SOCLIB_TYPE_HWI ) 411 { 412 // enable this HWI in local XCU controller 413 seg_xcu_ptr[(XCU_MSK_HWI_ENABLE << 5) | lid] = 1 << irq_id; 414 } 415 else if( irq_type == SOCLIB_TYPE_WTI ) 416 { 417 // enable this WTI in local XCU controller 418 seg_xcu_ptr[(XCU_MSK_WTI_ENABLE << 5) | lid] = 1 << irq_id; 419 } 420 else 421 { 422 assert( false , __FUNCTION__ , "illegal IRQ type\n" ); 423 } 424 } // end soclib_pic_enable_irq() 425 426 /////////////////////////////////////////// 427 void soclib_pic_disable_irq( lid_t lid, 428 chdev_t * src_chdev ) 429 { 430 // get local pointer on XCU segment base 431 uint32_t * seg_xcu_ptr = soclib_pic_xcu_base(); 432 433 // get the source chdev IRQ type and index 434 uint32_t irq_type = src_chdev->irq_type; 435 uint32_t irq_id = src_chdev->irq_id; 436 437 if( irq_type == SOCLIB_TYPE_HWI ) 438 { 439 // disable this HWI in local XCU controller 440 seg_xcu_ptr[(XCU_MSK_HWI_DISABLE << 5) | lid] = 1 << irq_id; 441 } 442 else if( irq_type == SOCLIB_TYPE_WTI ) 443 { 444 // disable this WTI in local XCU controller 445 seg_xcu_ptr[(XCU_MSK_WTI_DISABLE << 5) | lid] = 1 << irq_id; 446 } 447 else 448 { 449 assert( false , __FUNCTION__ , "illegal IRQ type\n" ); 450 } 451 } // end soclib_pic_enable_irq() 452 453 /////////////////////////////////////////////// 454 void soclib_pic_enable_timer( uint32_t period ) 455 { 456 // calling core local index 457 lid_t lid = CURRENT_CORE->lid; 458 459 // get XCU segment base 460 uint32_t * base = soclib_pic_xcu_base(); 461 462 // set period value in XCU 463 base[(XCU_PTI_PER << 5) | lid] = period; 464 465 // enable the PTI in local XCU controller 466 base[(XCU_MSK_PTI_ENABLE << 5) | lid] = 1 << lid; 45 467 } 46 468 47 //////////////////////////////////////////// 48 void soclib_pic_bind_irq( xptr_t dev_xp, 49 uint32_t irq_id, 50 xptr_t xp_wti ) 51 { 52 // get PIC device descriptor cluster and local pointer 53 cxy_t dev_cxy = GET_CXY( dev_xp ); 54 chdev_t * dev_ptr = (chdev_t *)GET_PTR( dev_xp ); 55 56 // get extended pointer on PIC segment base from PIC device descriptor 57 xptr_t seg_xp = (xptr_t)hal_remote_lwd( XPTR( dev_cxy , &dev_ptr->base ) ); 58 59 // get PIC controller segment cluster and local pointer 60 cxy_t seg_cxy = (cxy_t)GET_CXY( seg_xp); 61 uint32_t * seg_ptr = (uint32_t *)GET_PTR( seg_xp ); 62 63 uint32_t lsb = (uint32_t)xp_wti; 64 uint32_t msb = (uint32_t)(xp_wti>>32); 65 66 // set the IOPIC_ADDRESS and IOPIC_EXTEND registers 67 hal_remote_sw( XPTR( seg_cxy , seg_ptr+irq_id*IOPIC_SPAN+IOPIC_ADDRESS ) , lsb ); 68 hal_remote_sw( XPTR( seg_cxy , seg_ptr+irq_id*IOPIC_SPAN+IOPIC_EXTEND ) , msb ); 69 70 // set IOPIC_MASK register 71 hal_remote_sw( XPTR( seg_cxy , seg_ptr+irq_id*IOPIC_SPAN+IOPIC_MASK ) , 1 ); 469 /////////////////////////////////////// 470 void soclib_pic_send_ipi( cxy_t cxy, 471 lid_t lid ) 472 { 473 // get pointer on local XCU segment base 474 uint32_t * base = soclib_pic_xcu_base(); 475 476 // write to WTI mailbox[cxy][lid] 477 hal_remote_sw( XPTR( cxy , &base[(XCU_WTI_REG << 5) | lid] ) , 0 ); 72 478 } 73 479 74 ////////////////////////////////////////////// 75 void soclib_pic_unbind_irq( xptr_t dev_xp, 76 uint32_t irq_id ) 77 { 78 // get PIC device descriptor cluster and local pointer 79 cxy_t dev_cxy = GET_CXY( dev_xp ); 80 chdev_t * dev_ptr = (chdev_t *)GET_PTR( dev_xp ); 81 82 // get extended pointer on PIC segment base from PIC device descriptor 83 xptr_t seg_xp = (xptr_t)hal_remote_lwd( XPTR( dev_cxy , &dev_ptr->base ) ); 84 85 // get PIC controller segment cluster and local pointer 86 cxy_t seg_cxy = (cxy_t)GET_CXY( seg_xp); 87 uint32_t * seg_ptr = (uint32_t *)GET_PTR( seg_xp ); 88 89 // set IOPIC_MASK register 90 hal_remote_sw( XPTR( seg_cxy , seg_ptr+irq_id*IOPIC_SPAN+IOPIC_MASK ) , 0 ); 91 } 92 93 ////////////////////////////////////////////// 94 void soclib_pic_get_status( xptr_t dev_xp, 95 uint32_t irq_id, 96 uint32_t * status) 97 { 98 // get PIC device descriptor cluster and local pointer 99 cxy_t dev_cxy = GET_CXY( dev_xp ); 100 chdev_t * dev_ptr = (chdev_t *)GET_PTR( dev_xp ); 101 102 // get extended pointer on PIC segment base from PIC device descriptor 103 xptr_t seg_xp = (xptr_t)hal_remote_lwd( XPTR( dev_cxy , &dev_ptr->base ) ); 104 105 // get PIC controller segment cluster and local pointer 106 cxy_t seg_cxy = (cxy_t)GET_CXY( seg_xp); 107 uint32_t * seg_ptr = (uint32_t *)GET_PTR( seg_xp ); 108 109 // return status 110 *status = hal_remote_lw( XPTR( seg_cxy , seg_ptr+irq_id*IOPIC_SPAN+IOPIC_STATUS ) ); 111 } 112 480 481
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