Index: trunk/hal/tsar_mips32/core/hal_drivers.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_drivers.c	(revision 266)
+++ trunk/hal/tsar_mips32/core/hal_drivers.c	(revision 279)
@@ -75,4 +75,5 @@
 	/* update the PIC chdev extension */
 	pic->ext.pic.enable_timer = &soclib_pic_enable_timer;
+	pic->ext.pic.enable_ipi   = &soclib_pic_enable_ipi;
 	pic->ext.pic.enable_irq   = &soclib_pic_enable_irq;
 	pic->ext.pic.disable_irq  = &soclib_pic_disable_irq;
Index: trunk/hal/tsar_mips32/core/hal_interrupt.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_interrupt.c	(revision 266)
+++ trunk/hal/tsar_mips32/core/hal_interrupt.c	(revision 279)
@@ -23,9 +23,10 @@
 
 #include <hal_types.h>
+#include <hal_special.h>
 #include <kernel_config.h>
 #include <thread.h>
+#include <printk.h>
 #include <do_interrupt.h>
 #include <hal_interrupt.h>
-#include <mips32_uzone.h>
 #include <soclib_pic.h>
 
@@ -34,4 +35,6 @@
 		               reg_t    * regs_tbl ) 
 {
+    irq_dmsg("\n[INFO] %s : enter at cycle %d\n", __FUNCTION__ , hal_time_stamp() );
+
 	// update user time	
 	thread_user_time_update( this );
@@ -45,3 +48,5 @@
 	// update kernel time
 	thread_kernel_time_update( this );
+
+    irq_dmsg("\n[INFO] %s : exit at cycle %d\n", __FUNCTION__ , hal_time_stamp() );
 }
Index: trunk/hal/tsar_mips32/core/hal_irqmask.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_irqmask.c	(revision 266)
+++ trunk/hal/tsar_mips32/core/hal_irqmask.c	(revision 279)
@@ -28,18 +28,15 @@
 inline void hal_disable_irq( uint32_t * old )
 {
-	register unsigned int sr;
+	register uint32_t sr;
 	
 	__asm__ volatile 
 		(".set noat                          \n"
-		 ".set noreorder                     \n"
-		 "mfc0   $1,     $12                 \n"
-		 "nop                                \n"
-		 ".set reorder                       \n"
+         "mfc0   $1,     $12                 \n"
 		 "or     %0,     $0,     $1          \n"
 		 "srl    $1,     $1,     1           \n"
 		 "sll    $1,     $1,     1           \n"
 		 "mtc0   $1,     $12                 \n"
-		 ".set at                            \n"
-		 : "=&r" (sr));
+         ".set at                            \n"
+		 : "=&r" (sr) );
 
 	if( old ) *old = sr;
@@ -49,18 +46,14 @@
 inline void hal_enable_irq( uint32_t * old )
 {
-	register unsigned int sr;
+	register uint32_t sr;
  
 	__asm__ volatile 
 		(".set noat                          \n"
-		 ".set noreorder                     \n"
 		 "mfc0   $1,     $12                 \n"
-		 "nop                                \n"
 		 "or     %0,     $0,     $1          \n"
-		 "ori    $1,     $1,     0x1         \n"
+		 "ori    $1,     $1,     0xFF01      \n"
 		 "mtc0   $1,     $12                 \n"
-		 "nop                                \n"
-		 ".set reorder                       \n"
-		 ".set at                            \n"
-		 : "=&r" (sr));
+         ".set at                            \n"
+		 : "=&r" (sr) );
   
 	if( old ) *old = sr;
@@ -71,14 +64,6 @@
 {
 	__asm__ volatile 
-		(".set noat                          \n"
-		 ".set noreorder                     \n"
-		 "mfc0    $1,    $12                 \n"
-		 "ori     $2,    $0,      0xFF       \n"
-		 "and     $2,    $2,      %0         \n"
-		 "or      $1,    $1,      $2         \n"
-		 "mtc0    $1,    $12                 \n"
-		 ".set reorder                       \n" 
-		 ".set at                            \n"
-		 : : "r" (old) : "$2");
+		( "mtc0    %0,    $12" : : "r" (old) );
 }
 
+
Index: trunk/hal/tsar_mips32/core/hal_kentry.S
===================================================================
--- trunk/hal/tsar_mips32/core/hal_kentry.S	(revision 266)
+++ trunk/hal/tsar_mips32/core/hal_kentry.S	(revision 279)
@@ -1,4 +1,4 @@
 /*
- * hal_kentry.S - exception/interrupt/syscall kernel entry point for MIPS32
+ * hal_kentry.S - Interrupt / Exception / Syscall kernel entry point for MIPS32
  * 
  * AUthors   Ghassan Almaless (2007,2008,2009,2010,2011,2012)
@@ -30,29 +30,28 @@
 # or syscall for the TSAR_MIPS32 architecture.  
 #
-# - If the core is in user mode:
-#   . we desactivate the MMU.
-#   . we save the context in the uzone of the calling thread descriptor.
-#   . we increment the cores_in_kernel variable.
-#   . we call the relevant exception/interrupt/syscall handler
+# When we enter the kernel, we test the ststus register:
+# - If the core is in user mode, we desactivate the MMU, and we save
+#   the core context in the uzone of the calling thread descriptor.
+# - If the core is already in kernel mode (in case of interrupt), 
+#   we save the context in the kernel stack.
+# - In both cases, we increment the cores_in_kernel variable,
+#   and we call the relevant exception/interrupt/syscall handler
 #
-# - If the core is already in kernel mode: 
-#   . we save the context in the kernel stack
-#   . we call the relevant exception/interrupt/syscall handler
-#
-# - In both cases, when the handler returns:
-#   . we restore the context
-#   . we reactivate the MMU ??? TODO
+# When we exit the kernel after handler execution:
+# - we restore the core context from the uzone
 #---------------------------------------------------------------------------------
 
-	.section   .kentry,"ax",@progbits
-	.extern    cpu_do_interrupt
-	.extern    cpu_do_exception
-	.extern    cpu_do_syscall
-	.extern    cpu_kentry
-	.extern    cpu_kexit
+	.section   .kgiet, "ax", @progbits
+
+	.extern    hal_do_interrupt
+	.extern    hal_do_exception
+	.extern    hal_do_syscall
+	.extern    cluster_core_kernel_enter
+	.extern    cluster_core_kernel_exit
+
 	.org       0x180
-	.ent       kentry
-	.global    kentry
-	.global    kentry_load
+	.ent       kernel_enter
+	.global    kernel_enter
+
 	.set       noat
 	.set       noreorder
@@ -67,8 +66,8 @@
 
 #---------------------------------------------------------------------------------
-# Kernel Entry point
+# Kernel Entry point for Interrupt / Exception / Syscall
 #---------------------------------------------------------------------------------
 
-kentry:
+kernel_enter:
 	mfc0    $26,    $12                 # read SR to test user/kernel mode
 	andi    $26,    $26,  0x10          # User Mode bitmask
@@ -101,5 +100,5 @@
 #---------------------------------------------------------------------------------------	
 # this code is executed when the core is in kernel mode:
-# - we use an uzone allocated in kernel stack.
+# - we use an uzone dynamically allocated in kernel stack.
 # - we set the MMU off, set the MMU data_paddr extension to local_cxy,
 #   and save the CP2_MODE and CP2_DEXT to uzone.
@@ -141,6 +140,7 @@
 
 #--------------------------------------------------------------------------------------	
-# this code is executed in both modes, with the two following assumptions:
-# - $27 contains the pointer on uzone to save the cpu registers
+# This code is executed in both modes, and saves the core context,
+# with the two following assumptions:
+# - $27 contains the pointer on uzone to save the core registers
 # - $29 contains the kernel stack pointer
 
@@ -186,21 +186,28 @@
 	sw      $17,	(UZ_CR*4)($27)		# Save CR
 
-	srl	    $3,     $18,  5	            # put SR in kernel mode, IRQ disabled, clear exl
+    # put SR in kernel mode, IRQ disabled, clear exl
+	srl	    $3,     $18,  5
 	sll     $3,	    $3,   5	
 	mtc0	$3,	    $12			        # Set new SR
 
-	andi    $1,     $17,  0x3F          # $1 <= XCODE (from CR)
-
 	# signal that core enters kernel
-	jal	    cluster_core_kernel_enter
+	la      $1,     cluster_core_kernel_enter
+	jal	    $1
     nop
 
 #---------------------------------------------------------------------------------------
-# Depending on XCODE (in $1) , call the apropriate handler. The three called
-# functions take the same two arguments: thread pointer and uzone pointer.
+# This code call the relevant Interrupt / Exception / Syscall handler,
+# depending on XCODE in CP0_CR, with the two following assumptions:
+# - $27 contains the pointer on uzone containing to save the core registers
+# - $29 contains the kernel stack pointer
+# The three handlers take the same two arguments: thread pointer and uzone pointer.
+# The uzone pointer is saved in $19 to be used by kernel_exit.
+
+	mfc0    $17,    $13                 # $1 <= CR
+	andi    $1,     $1,   0x3F          # $1 <= XCODE
 
 	mfc0    $4,     $4,   2             # $4 <= thread pointer (first arg)
 	or	    $5,	    $0,   $27		    # $5 <= uzone pointer (second arg)
-	or	    $19,    $0,	  $27	        # $19 <= &uzone (for kentry_exit)
+	or	    $19,    $0,	  $27	        # $19 <= &uzone (for kernel_exit)
 
 	ori	    $8,     $0,   0x20          # $8 <= cause syscall
@@ -215,5 +222,5 @@
 	addiu	$29,	$29,  -8	        # hal_do_exception has 2 args
 	addiu	$29,	$29,  8
-	j       kentry_exit                 # jump to kentry_exit
+	j       kernel_exit                 # jump to kernel_exit
     nop
 
@@ -223,6 +230,6 @@
 	addiu	$29,	$29,  -8            # hal_do_syscall has 2 args
 	addiu	$29,	$29,  8
-	j	    kentry_exit                 # jump to kentry_exit
-	or	    $19,	$0,   $2
+	j	    kernel_exit                 # jump to kernel_exit
+	nop 
 	
 cause_int:
@@ -233,10 +240,13 @@
 
 # -----------------------------------------------------------------------------------
-# Kentry exit
+# Kernel exit
+# The pointer on uzone is supposed to be stored in $19
 # -----------------------------------------------------------------------------------
-kentry_exit:
+kernel_exit:
 
 	# signal that core exit kernel
-    jal     cluster_core_kernel_exit
+    la      $1,     cluster_core_kernel_exit
+    jalr    $1
+    nop
 
 	# restore context from uzone
@@ -286,57 +296,17 @@
 	lw	    $31,	(UZ_RA*4)($27)
 
-
 	lw	    $26,    (UZ_DEXT*4)($27)
 	mtc2	$26,    $24			        # restore CP2_DEXT from uzone
 
-    #TODO: optimize
-	lw	    $26,    (UZ_MODE*4)($27)    # get saved CP2_MODE from uzone
-	andi	$26,	$26,	0xc         # keep only the TLBs controling bits
-	beq     $26,    $0,	    out_mmu_3   # both MSB are 0 (the first two LSB are always set)
-	andi	$26,	$26,	0x8
-	beq     $26,    $0,	    out_mmu_7   # first MSB is 0 (bit 2 is set)
-
-# Possible value for MMU_MODE
-# In kernel mode : 0x7/0x3
-# In user mode   : 0xF
-
-# DP_EXT can either be local or remote
-# Once these register set we can no longuer 
-# access global data
-
-out_mmu_F:
-	ori	    $26,	$0,	   0xF
-	mtc2    $26,    $1			        # CP2_MODE <= 0xF
-	j	    out_kentry
-	nop
-
-out_mmu_7:
-	ori	    $26,    $0,    0x7	
-	mtc2    $26,    $1			        # CP2_MODE <= 0x7
-	j	out_kentry
-	nop
-
-out_mmu_3:
-	ori     $26,    $0,	   0x3
-	mtc2    $26,    $1			        # CP2_MODE <= 0x3
-
-out_kentry:
+	lw	    $26,    (UZ_MODE*4)($27)    
+    mtc2    $26,    $1                  # restore CP2_MODE from uzone
+
 	nop
     eret
 
-    .end kentry
+    .end kernel_enter
     .set reorder
     .set at
 
-	.ent kentry_load
-kentry_load:
-	# theses nops are required to load the eret instruction
-	# while we are in virtual mode (processor pipeline) ?
-	mtc2     $26,    $1	       # set MMU MODE
-	nop			
-	nop
-    eret
-    .end kentry_load
-
 #-------------------------------------------------------------------------------
 
Index: trunk/hal/tsar_mips32/core/hal_kentry.h
===================================================================
--- trunk/hal/tsar_mips32/core/hal_kentry.h	(revision 266)
+++ trunk/hal/tsar_mips32/core/hal_kentry.h	(revision 279)
@@ -24,47 +24,4 @@
 #define _HAL_KENTRY_H_
 
-/***************************************************************************************
- * This file ... TODO
- **************************************************************************************/
-
-#define      KSP          0
-#define      AT           1
-#define      V0           2
-#define      V1           3
-#define      A0           4 
-#define      A1           5
-#define      A2           6
-#define      A3           7
-#define      T0           8
-#define      T1           9
-#define      T2           10
-#define      T3           11
-#define      T4           12
-#define      T5           13
-#define      T6           14
-#define      T7           15
-#define      T8           16
-#define      T9           17
-#define      S0           18
-#define      S1           19
-#define      S2           20
-#define      S3           21
-#define      S4           22
-#define      S5           23
-#define      S6           24
-#define      S7           25
-#define      S8           26
-#define      GP           27
-#define      RA           28
-#define      EPC          29
-#define      CR           30
-#define      SP           31
-#define      SR           32
-#define      LO           33
-#define      HI           34
-#define      TLS_K1       35
-#define      DP_EXT	      36   // DATA PADDR EXTENSION
-#define      MMU_MD	      37   // MMU MODE
-#define      REGS_NR      38
 
 #define CPU_IN_KERNEL 1
Index: trunk/hal/tsar_mips32/core/hal_ppm.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_ppm.c	(revision 266)
+++ trunk/hal/tsar_mips32/core/hal_ppm.c	(revision 279)
@@ -39,7 +39,5 @@
 // - the 64 bits XPTR value is identical to the 64 bits PADDR value.
 // The pages_tbl[] is mapped in first free page after kernel code.
-// There is no other reserved zones than the zone occupied by the kernel code.
 //////////////////////////////////////////////////////////////////////////////////////////
-
 
 ///////////////////////////////////////////
@@ -52,7 +50,4 @@
 	uint32_t pages_tbl_offset = info->pages_offset;
 	uint32_t rsvd_nr          = info->rsvd_nr;
-
-	// check no reserved zones other than kernel code for TSAR
-	assert( (rsvd_nr == 0 ) , __FUNCTION__ , "NO reserved zones for TSAR\n" );
 
 	// get pointer on local Physical Page Manager
Index: trunk/hal/tsar_mips32/core/hal_remote.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_remote.c	(revision 266)
+++ trunk/hal/tsar_mips32/core/hal_remote.c	(revision 279)
@@ -34,18 +34,25 @@
     uint32_t cxy = (uint32_t)GET_CXY( xp );
 
-    hal_disable_irq( &save_sr );
-
-    asm volatile( 
-        ".set noreorder              \n"
-        "mfc2   $15,    $24          \n"  /* $15 <= PADDR_EXT */   
-        "mtc2   %2,     $24          \n"  /* PADDR_EXT <= cxy */   
-        "sb     %0,     0(%1)        \n"  /* *paddr <= value  */
-        "mtc2   $15,    $24          \n"  /* PADDR_EXT <= $15 */   
+/* TODO improve all hal remote functions to include SR handling in assembly code */
+/* as it is done below for hal_remote_sb                                         */
+
+    asm volatile( 
+        ".set noreorder              \n"
+        "mfc0   $14,    $12          \n"  /* $14 <= CP0_SR      */
+        "srl    $13,    $14,    1    \n" 
+        "sll    $13,    $13,    1    \n"  /* $13 <= SR masked   */
+        "mtc0   $13,    $12          \n"  /* IRQ disabled       */
+        
+
+        "mfc2   $15,    $24          \n"  /* $15 <= PADDR_EXT   */   
+        "mtc2   %2,     $24          \n"  /* PADDR_EXT <= cxy   */   
+        "sb     %0,     0(%1)        \n"  /* *paddr <= value    */
+        "mtc2   $15,    $24          \n"  /* PADDR_EXT <= $15   */   
+
+        "mtc0   $14,    $12          \n"  /* SR restored        */
+
         "sync                        \n"
         ".set reorder                \n"
-        : : "r" (data), "r" (ptr), "r" (cxy) : "$15" );
-
-    hal_restore_irq( save_sr );
-
+        : : "r" (data), "r" (ptr), "r" (cxy) : "$13", "$14", "$15" );
 }
 
Index: trunk/hal/tsar_mips32/core/hal_special.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_special.c	(revision 266)
+++ trunk/hal/tsar_mips32/core/hal_special.c	(revision 279)
@@ -32,4 +32,9 @@
 struct thread_s;
 
+/////////////////////////////////
+void hal_set_ebase( reg_t  base )
+{ 
+	asm volatile ("mtc0    %0,  $15,  1" : : "r" (base));
+}
 
 //////////////////////////
@@ -48,7 +53,17 @@
     cycle_t count;
 
-	asm volatile ("mfc0   %0,  $9  " : "=&r" (count));
+	asm volatile ("mfc0   %0,  $9" : "=&r" (count));
 
     return count;
+}
+
+/////////////////////////
+inline reg_t hal_get_sr()
+{
+    register uint32_t sr;
+
+	asm volatile ("mfc0    %0,    $12" : "=&r" (sr));
+
+	return sr;
 }
 
@@ -90,7 +105,5 @@
 	void * thread_ptr;
  
-	asm volatile
-    ( "mfc0    %0,  $4,  2  \n"
-      : "=&r" (thread_ptr)  );
+	asm volatile ("mfc0    %0,  $4,  2" : "=&r" (thread_ptr));
 
 	return thread_ptr;
@@ -100,7 +113,5 @@
 void hal_set_current_thread( struct thread_s * thread )
 { 
-	asm volatile
-    ( "mtc0    %0,  $4,  2  \n"
-      : : "r" (thread) );
+	asm volatile ("mtc0    %0,  $4,  2" : : "r" (thread));
 }
 
@@ -135,7 +146,5 @@
 	register uint32_t sp;
   
-	asm volatile
-	( "or    %0,   $0,   $29  \n" 
-       : "=&r" (sp) );
+	asm volatile ("or    %0,   $0,   $29" : "=&r" (sp));
   
 	return sp;
