Changeset 296 for trunk/hal/tsar_mips32/core/hal_context.c
- Timestamp:
- Jul 31, 2017, 1:59:52 PM (7 years ago)
- File:
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- 1 edited
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trunk/hal/tsar_mips32/core/hal_context.c
r151 r296 43 43 44 44 ///////////////////////////////////////////////////////////////////////////////////////// 45 // Th is structure defines the cpu_context for TSAR MIPS32.45 // These structuree defines the cpu_context anf fpu_context for TSAR MIPS32. 46 46 // These registers are saved/restored at each context switch. 47 // WARNING : update the hal_cpu_context_save() and hal_cpu_context_restore() 48 // functions when modifying this structure. 47 // WARNING : update the hal_***_context_save() and hal_***_context_restore() 48 // functions when modifying this structure, and check the two 49 // CONFIG_CPU_CTX_SIZE & CONFIGFPU_CTX_SIZE configuration parameterss. 49 50 ///////////////////////////////////////////////////////////////////////////////////////// 50 51 51 52 typedef struct hal_cpu_context_s 52 53 { 53 uint32_t s0_16; // slot 0 54 uint32_t s1_17; // slot 1 55 uint32_t s2_18; // slot 2 56 uint32_t s3_19; // slot 3 57 uint32_t s4_20; // slot 4 58 uint32_t s5_21; // slot 5 59 uint32_t s6_22; // slot 6 60 uint32_t s7_23; // slot 7 61 uint32_t sp_29; // slot 8 62 uint32_t fp_30; // slot 9 63 uint32_t ra_31; // slot 10 64 uint32_t c0_sr; // slot 11 65 uint32_t c0_th; // slot 12 66 uint32_t c2_ptpr; // slot 13 67 uint32_t c2_mode; // slot 14 54 uint32_t c0_epc; // slot 0 55 uint32_t at_01; // slot 1 56 uint32_t v0_02; // slot 2 57 uint32_t v1_03; // slot 3 58 uint32_t a0_04; // slot 4 59 uint32_t a1_05; // slot 5 60 uint32_t a2_06; // slot 6 61 uint32_t a3_07; // slot 7 62 63 uint32_t t0_08; // slot 8 64 uint32_t t1_09; // slot 9 65 uint32_t t2_10; // slot 10 66 uint32_t t3_11; // slot 11 67 uint32_t t4_12; // slot 12 68 uint32_t t5_13; // slot 13 69 uint32_t t6_14; // slot 14 70 uint32_t t7_15; // slot 15 71 72 uint32_t s0_16; // slot 16 73 uint32_t s1_17; // slot 17 74 uint32_t s2_18; // slot 18 75 uint32_t s3_19; // slot 19 76 uint32_t s4_20; // slot 20 77 uint32_t s5_21; // slot 21 78 uint32_t s6_22; // slot 22 79 uint32_t s7_23; // slot 23 80 81 uint32_t t8_24; // slot 24 82 uint32_t t8_25; // slot 25 83 uint32_t hi_26; // slot 26 84 uint32_t lo_27; // slot 27 85 uint32_t gp_28; // slot 28 86 uint32_t sp_29; // slot 29 87 uint32_t fp_30; // slot 30 88 uint32_t ra_31; // slot 31 89 90 uint32_t c2_ptpr; // slot 32 91 uint32_t c2_mode; // slot 33 92 93 uint32_t c0_sr; // slot 34 94 uint32_t c0_th; // slot 35 68 95 } 69 96 hal_cpu_context_t; … … 79 106 hal_fpu_context_t; 80 107 81 ////////////////////////////////////////////////////////// 82 error_t hal_cpu_context_create( struct thread_s * thread ) 108 109 110 ///////////////////////////////////////////////////////////////////////////////////////// 111 // CPU context access functions 112 ///////////////////////////////////////////////////////////////////////////////////////// 113 114 115 ///////////////////////////////////////////////////////////////////////////////////////// 116 // Seven registers are initialised by this function: 117 // GPR : sp_29 / fp_30 / ra_31 118 // CP0 : c0_sr / c0_th 119 // CP2 : c2_ptpr / c2_mode 120 ///////////////////////////////////////////////////////////////////////////////////////// 121 error_t hal_cpu_context_create( thread_t * thread ) 83 122 { 84 123 kmem_req_t req; … … 127 166 context->c2_mode = c2_mode; 128 167 129 context_dmsg("\n[INFO] %s : exit for thread %x in process %x \n",130 __FUNCTION__ , thread->trdid , thread->process->pid );168 context_dmsg("\n[INFO] %s : exit for thread %x in process %x / ra = %x\n", 169 __FUNCTION__ , thread->trdid , thread->process->pid , context->ra_31 ); 131 170 132 171 return 0; 133 172 } // end hal_cpu_context_create() 173 174 ///////////////////////////////////////////////// 175 void hal_cpu_context_display( thread_t * thread ) 176 { 177 hal_cpu_context_t * ctx = (hal_cpu_context_t *)thread->cpu_context; 178 179 printk("\n*** cpu_context for thread %x in cluster %x / ctx = %x ***\n" 180 " gp_28 = %X sp_29 = %X ra_31 = %X\n" 181 " c0_sr = %X c0_epc = %X c0_th = %X\n" 182 " c2_ptpr = %X c2_mode = %X\n", 183 thread->trdid, local_cxy, ctx, 184 ctx->gp_28 , ctx->sp_29 , ctx->ra_31, 185 ctx->c0_sr , ctx->c0_epc , ctx->c0_th, 186 ctx->c2_ptpr , ctx->c2_mode ); 187 } 188 189 ///////////////////////////////////////////////////////////////////////////////////////// 190 // These registers are saved to CPU context defined by <ctx> argument. 191 // - GPR : all, but (zero, k0, k1), plus (hi, lo) 192 // - CP0 : c0_th , c0_sr 193 // - CP2 : c2_ptpr , C2_mode, C2_epc 194 ///////////////////////////////////////////////////////////////////////////////////////// 195 void hal_cpu_context_save( void * ctx ) 196 { 197 asm volatile( 198 ".set noat \n" 199 ".set noreorder \n" 200 "move $26, $4 \n" /* $26 <= &ctx */ 201 202 "mfc0 $27, $14 \n" 203 "sw $27, 0*4($26) \n" /* save c0_epc to slot 0 */ 204 205 "sw $1, 1*4($26) \n" 206 "sw $2, 2*4($26) \n" 207 "sw $3, 3*4($26) \n" 208 "sw $4, 4*4($26) \n" 209 "sw $5, 5*4($26) \n" 210 "sw $6, 6*4($26) \n" 211 "sw $7, 7*4($26) \n" 212 213 "sw $8, 8*4($26) \n" 214 "sw $9, 9*4($26) \n" 215 "sw $10, 10*4($26) \n" 216 "sw $11, 11*4($26) \n" 217 "sw $12, 12*4($26) \n" 218 "sw $13, 13*4($26) \n" 219 "sw $14, 14*4($26) \n" 220 "sw $15, 15*4($26) \n" 221 222 "sw $16, 16*4($26) \n" 223 "sw $17, 17*4($26) \n" 224 "sw $18, 18*4($26) \n" 225 "sw $19, 19*4($26) \n" 226 "sw $20, 20*4($26) \n" 227 "sw $21, 21*4($26) \n" 228 "sw $22, 22*4($26) \n" 229 "sw $23, 23*4($26) \n" 230 231 "sw $24, 24*4($26) \n" 232 "sw $25, 25*4($26) \n" 233 234 "mfhi $27 \n" 235 "sw $27, 26*4($26) \n" /* save hi to slot 26 */ 236 "mflo $27 \n" 237 "sw $27, 27*4($26) \n" /* save lo to slot 27 */ 238 239 "sw $28, 28*4($26) \n" 240 "sw $29, 29*4($26) \n" 241 "sw $30, 30*4($26) \n" 242 "sw $31, 31*4($26) \n" 243 244 "mfc2 $27, $0 \n" 245 "sw $27, 32*4($26) \n" /* save c2_ptpr to slot 32 */ 246 "mfc2 $27, $1 \n" 247 "sw $27, 33*4($26) \n" /* save c2_mode to slot 33 */ 248 249 "mfc0 $27, $12 \n" 250 "sw $27, 34*4($26) \n" /* save c0_sr to slot 34 */ 251 "mfc0 $27, $4, 2 \n" 252 "sw $27, 35*4($26) \n" /* save c0_th to slot 35 */ 253 254 "sync \n" 255 256 "move $4, $27 \n" 257 "jal hal_cpu_context_display \n" /* display context */ 258 "nop \n" 259 260 ".set reorder \n" 261 ".set at \n" 262 : : : "$26" , "$27" , "memory" ); 263 } 264 265 ///////////////////////////////////////////////////////////////////////////////////////// 266 // These registers are restored from cpu context defined by <ctx> argument: 267 // - GPR : all, but (zero, k0, k1), plus (hi, lo) 268 // - CP0 : c0_th , c0_sr 269 // - CP2 : c2_ptpr , C2_mode 270 ///////////////////////////////////////////////////////////////////////////////////////// 271 void hal_cpu_context_restore( void * ctx ) 272 { 273 asm volatile( 274 ".set noat \n" 275 ".set noreorder \n" 276 "move $26, $4 \n" /* $26 <= &ctx */ 277 278 "lw $4, 35*4($26) \n" 279 "jal hal_cpu_context_display \n" /* display context */ 280 "nop \n" 281 282 "lw $27, 0*4($26) \n" 283 "mtc0 $27, $14 \n" /* restore C0_epc from slot 0 */ 284 285 "lw $1, 1*4($26) \n" 286 "lw $2, 2*4($26) \n" 287 "lw $3, 3*4($26) \n" 288 "lw $4, 4*4($26) \n" 289 "lw $5, 5*4($26) \n" 290 "lw $6, 6*4($26) \n" 291 "lw $7, 7*4($26) \n" 292 293 "lw $8, 8*4($26) \n" 294 "lw $9, 9*4($26) \n" 295 "lw $10, 10*4($26) \n" 296 "lw $11, 11*4($26) \n" 297 "lw $12, 12*4($26) \n" 298 "lw $13, 13*4($26) \n" 299 "lw $14, 14*4($26) \n" 300 "lw $15, 15*4($26) \n" 301 302 "lw $16, 16*4($26) \n" 303 "lw $17, 17*4($26) \n" 304 "lw $18, 18*4($26) \n" 305 "lw $19, 19*4($26) \n" 306 "lw $20, 20*4($26) \n" 307 "lw $21, 21*4($26) \n" 308 "lw $22, 22*4($26) \n" 309 "lw $23, 23*4($26) \n" 310 311 "lw $24, 24*4($26) \n" 312 "lw $25, 25*4($26) \n" 313 314 "lw $27, 26*4($26) \n" 315 "mthi $27 \n" /* restore hi from slot 26 */ 316 "lw $27, 27*4($26) \n" 317 "mtlo $27 \n" /* restote lo from slot 27 */ 318 319 "lw $28, 28*4($26) \n" 320 "lw $29, 29*4($26) \n" 321 "lw $30, 30*4($26) \n" 322 "lw $31, 31*4($26) \n" 323 324 "lw $27, 32*4($26) \n" 325 "mtc2 $27, $0 \n" /* restore c2_ptpr from slot 32 */ 326 "lw $27, 33*4($26) \n" 327 "mtc2 $27, $1 \n" /* restore c2_mode from slot 33 */ 328 329 "lw $27, 34*4($26) \n" 330 "mtc0 $27, $12 \n" /* restore c0_sr from slot 34 */ 331 "lw $27, 35*4($26) \n" 332 "mtc0 $27, $4, 2 \n" /* restore co_th from slot 35 */ 333 334 ".set reorder \n" 335 ".set at \n" 336 : : : "$26" , "$27" ); 337 } 134 338 135 339 ///////////////////////////////////////////// … … 226 430 } // end hal_fpu_context_destroy() 227 431 228 ////////////////////////////////////////////// 229 void hal_cpu_context_save( thread_t * thread ) 230 { 231 uint32_t ctx = (uint32_t)thread->cpu_context; 232 233 asm volatile( 234 ".set noreorder \n" 235 "sw $16, 0*4(%0) \n" /* save s0 to slot 0 */ 236 "sw $17, 1*4(%0) \n" /* save s1 to slot 1 */ 237 "sw $18, 2*4(%0) \n" /* save s2 to slot 2 */ 238 "sw $19, 3*4(%0) \n" /* save s3 to slot 3 */ 239 "sw $20, 4*4(%0) \n" /* save s4 to slot 4 */ 240 "sw $21, 5*4(%0) \n" /* save s5 to slot 5 */ 241 "sw $22, 6*4(%0) \n" /* save s6 to slot 6 */ 242 "sw $23, 7*4(%0) \n" /* save s7 to slot 7 */ 243 "sw $29, 8*4(%0) \n" /* save sp to slot 8 */ 244 "sw $30, 9*4(%0) \n" /* save fp to slot 9 */ 245 "sw $31, 10*4(%0) \n" /* save ra to slot 10 */ 246 "mfc0 $26, $4, 2 \n" /* get c0_th from CP0 */ 247 "sw $26, 12*4(%0) \n" /* save c0_th to slot 12 */ 248 "mfc2 $26, $0 \n" /* get c2_ptpr from CP2 */ 249 "sw $26, 13*4(%0) \n" /* save c2_ptpr to slot 13 */ 250 "mfc2 $26, $1 \n" /* get c2_mod from CP2 */ 251 "sw $26, 14*4(%0) \n" /* save c2_mode to slot 14 */ 252 "sync \n" 253 ".set reorder \n" 254 : : "r"( ctx ) : "$26" , "memory" ); 255 } 256 257 ///////////////////////////////////////////////// 258 void hal_cpu_context_restore( thread_t * thread ) 259 { 260 uint32_t ctx = (uint32_t)thread->cpu_context; 261 262 asm volatile( 263 ".set noreorder \n" 264 "nop \n" 265 "lw $16, 0*4(%0) \n" /* restore s0_16 */ 266 "lw $17, 1*4(%0) \n" /* restore s1_17 */ 267 "lw $18, 2*4(%0) \n" /* restore s2_18 */ 268 "lw $19, 3*4(%0) \n" /* restore s3_19 */ 269 "lw $20, 4*4(%0) \n" /* restore s4_20 */ 270 "lw $21, 5*4(%0) \n" /* restore s5_21 */ 271 "lw $22, 6*4(%0) \n" /* restore s6_22 */ 272 "lw $23, 7*4(%0) \n" /* restore s7_23 */ 273 "lw $29, 8*4(%0) \n" /* restore sp_29 */ 274 "lw $30, 9*4(%0) \n" /* restore fp_30 */ 275 "lw $31, 10*4(%0) \n" /* restore ra_31 */ 276 "lw $26, 12*4(%0) \n" /* get c0_th from slot 12 */ 277 "mtc0 $26, $4, 2 \n" /* restore c0_th */ 278 "lw $26, 13*4(%0) \n" /* get c2_ptpr from slot 13 */ 279 "mtc2 $26, $0 \n" /* restore c2_ptpr */ 280 "lw $26, 14*4(%0) \n" /* get c2_mode from slot 14 */ 281 "mtc2 $26, $1 \n" /* restore c2_mode */ 282 ".set reorder \n" 283 : : "r"(ctx) 284 : "$16","$17","$18","$19","$20","$21","$22","$23","$26","$29","$30","$31" ); 285 } 286 287 ////////////////////////////////////////////// 432 ///////////////////////////////////////////////////////////////////////////////////////// 433 // These registers are initialised: 434 // - GPR : sp_29 , fp_30 , a0 435 // - CP0 : c0_sr , c0_epc , c0_th 436 // - CP2 : C2_ptpr , c2_mode 437 // TODO Quand cette fonction est-elle appelée? [AG] 438 ///////////////////////////////////////////////////////////////////////////////////////// 288 439 void hal_cpu_context_load( thread_t * thread ) 289 440 {
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