Changeset 296 for trunk/hal/tsar_mips32/core/hal_ppm.c

Timestamp:

Jul 31, 2017, 1:59:52 PM (7 years ago)

Author:

alain

Message:

Several modifs in the generic scheduler and in the hal_context to
fix the context switch mechanism.

File:

• trunk/hal/tsar_mips32/core/hal_ppm.c (modified) (3 diffs)

trunk/hal/tsar_mips32/core/hal_ppm.c

@@ -35 +35 @@
 
 //////////////////////////////////////////////////////////////////////////////////////////
+// This file contains the TSAR specific code for cores registers,
+// and for physical memory allocators initialisation in a given cluster.
+
 // For The TSAR architecture, the kernel pointers are identity mapped:
 // - the 32 bits PTR value is identical to the 32 bits LPA value,
 // - the 64 bits XPTR value is identical to the 64 bits PADDR value.
-// The pages_tbl[] is mapped in first free page after kernel code.
+// This hal_ppm_init() function initializes the pages_tbl[] array used by the generic
+// kmem memory allocator in the local cluster. This array starts in first free page
+// after kernel code, as defined by the 'offset' field in boot_info.
+//
+// For the TSAR architecture the MIP32 EBASE register defining the kernel entry point
+// fot Interrupts, Exceptions and Syscalls, has to be redefined.
 //////////////////////////////////////////////////////////////////////////////////////////
 
@@ -49 +57 @@
         uint32_t pages_nr         = info->pages_nr;
         uint32_t pages_tbl_offset = info->pages_offset;
-        uint32_t rsvd_nr          = info->rsvd_nr;
 
         // get pointer on local Physical Page Manager
@@ -113 +120 @@
         // check consistency
         return ppm_assert_order( ppm );
-}
 
+}  // end hal_ppm_init()
+
+////////////////////////////////////////
+void hal_core_init( boot_info_t * info )
+{
+        // get relevant info from boot_info structure
+        reg_t kentry_base = info->kentry_base;
+
+    // set CP0_EBASE register
+    hal_set_ebase( kentry_base );
+
+}  // end hal_core_init()