Index: trunk/hal/tsar_mips32/core/hal_context.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_context.c	(revision 285)
+++ trunk/hal/tsar_mips32/core/hal_context.c	(revision 296)
@@ -43,27 +43,54 @@
 
 /////////////////////////////////////////////////////////////////////////////////////////
-// This structure defines the cpu_context for TSAR MIPS32.
+// These structuree defines the cpu_context anf fpu_context for TSAR MIPS32.
 // These registers are saved/restored at each context switch.
-// WARNING : update the hal_cpu_context_save() and hal_cpu_context_restore()
-//           functions when modifying this structure. 
+// WARNING : update the hal_***_context_save() and hal_***_context_restore()
+//           functions when modifying this structure, and check the two
+//           CONFIG_CPU_CTX_SIZE & CONFIGFPU_CTX_SIZE configuration parameterss. 
 /////////////////////////////////////////////////////////////////////////////////////////
 
 typedef struct hal_cpu_context_s
 {
-	uint32_t s0_16;      // slot 0
-	uint32_t s1_17;      // slot 1
-	uint32_t s2_18;      // slot 2
-	uint32_t s3_19;      // slot 3
-	uint32_t s4_20;      // slot 4
-	uint32_t s5_21;      // slot 5
-	uint32_t s6_22;      // slot 6
-	uint32_t s7_23;      // slot 7
-	uint32_t sp_29;      // slot 8
-	uint32_t fp_30;      // slot 9
-	uint32_t ra_31;      // slot 10
-	uint32_t c0_sr;      // slot 11
-	uint32_t c0_th;      // slot 12
-	uint32_t c2_ptpr;    // slot 13
-	uint32_t c2_mode;    // slot 14
+    uint32_t c0_epc;     // slot 0
+    uint32_t at_01;      // slot 1
+    uint32_t v0_02;      // slot 2
+    uint32_t v1_03;      // slot 3
+    uint32_t a0_04;      // slot 4
+    uint32_t a1_05;      // slot 5
+    uint32_t a2_06;      // slot 6
+    uint32_t a3_07;      // slot 7
+
+    uint32_t t0_08;      // slot 8
+    uint32_t t1_09;      // slot 9
+    uint32_t t2_10;      // slot 10
+    uint32_t t3_11;      // slot 11
+    uint32_t t4_12;      // slot 12
+    uint32_t t5_13;      // slot 13
+    uint32_t t6_14;      // slot 14
+    uint32_t t7_15;      // slot 15
+
+	uint32_t s0_16;      // slot 16
+	uint32_t s1_17;      // slot 17
+	uint32_t s2_18;      // slot 18
+	uint32_t s3_19;      // slot 19
+	uint32_t s4_20;      // slot 20
+	uint32_t s5_21;      // slot 21
+	uint32_t s6_22;      // slot 22
+	uint32_t s7_23;      // slot 23
+
+    uint32_t t8_24;      // slot 24
+    uint32_t t8_25;      // slot 25
+    uint32_t hi_26;      // slot 26
+    uint32_t lo_27;      // slot 27
+    uint32_t gp_28;      // slot 28
+	uint32_t sp_29;      // slot 29
+	uint32_t fp_30;      // slot 30
+	uint32_t ra_31;      // slot 31
+
+	uint32_t c2_ptpr;    // slot 32
+	uint32_t c2_mode;    // slot 33
+
+	uint32_t c0_sr;      // slot 34
+	uint32_t c0_th;      // slot 35
 } 
 hal_cpu_context_t;
@@ -79,6 +106,18 @@
 hal_fpu_context_t;
 
-//////////////////////////////////////////////////////////
-error_t hal_cpu_context_create( struct thread_s * thread )
+
+
+/////////////////////////////////////////////////////////////////////////////////////////
+//        CPU context access functions
+/////////////////////////////////////////////////////////////////////////////////////////
+
+
+/////////////////////////////////////////////////////////////////////////////////////////
+// Seven registers are initialised by this function:
+// GPR : sp_29 / fp_30 / ra_31
+// CP0 : c0_sr / c0_th
+// CP2 : c2_ptpr / c2_mode
+/////////////////////////////////////////////////////////////////////////////////////////
+error_t hal_cpu_context_create( thread_t * thread )
 {
     kmem_req_t  req;
@@ -127,9 +166,174 @@
 	context->c2_mode    = c2_mode;
 
-    context_dmsg("\n[INFO] %s : exit for thread %x in process %x\n",
-                 __FUNCTION__ , thread->trdid , thread->process->pid );
+    context_dmsg("\n[INFO] %s : exit for thread %x in process %x / ra = %x\n",
+                 __FUNCTION__ , thread->trdid , thread->process->pid , context->ra_31 );
 
     return 0;
 }  // end hal_cpu_context_create()
+
+/////////////////////////////////////////////////
+void hal_cpu_context_display( thread_t * thread )
+{
+    hal_cpu_context_t * ctx = (hal_cpu_context_t *)thread->cpu_context;
+
+    printk("\n*** cpu_context for thread %x in cluster %x / ctx = %x ***\n" 
+           " gp_28   = %X    sp_29   = %X    ra_31   = %X\n" 
+           " c0_sr   = %X    c0_epc  = %X    c0_th = %X\n"
+           " c2_ptpr = %X    c2_mode = %X\n",
+           thread->trdid, local_cxy, ctx,
+           ctx->gp_28   , ctx->sp_29   , ctx->ra_31,
+           ctx->c0_sr   , ctx->c0_epc  , ctx->c0_th,
+           ctx->c2_ptpr , ctx->c2_mode );
+}
+
+/////////////////////////////////////////////////////////////////////////////////////////
+// These registers are saved to CPU context defined by <ctx> argument.
+// - GPR : all, but (zero, k0, k1), plus (hi, lo)
+// - CP0 : c0_th , c0_sr 
+// - CP2 : c2_ptpr , C2_mode, C2_epc
+/////////////////////////////////////////////////////////////////////////////////////////
+void hal_cpu_context_save( void * ctx )
+{
+    asm volatile(
+    ".set noat                     \n"
+    ".set noreorder                \n"
+    "move    $26,   $4             \n"   /* $26 <= &ctx */
+
+    "mfc0    $27,   $14            \n"
+    "sw      $27,   0*4($26)       \n"   /* save c0_epc to slot 0 */
+ 
+    "sw      $1,    1*4($26)       \n"
+    "sw      $2,    2*4($26)       \n"
+    "sw      $3,    3*4($26)       \n"
+    "sw      $4,    4*4($26)       \n"
+    "sw      $5,    5*4($26)       \n"
+    "sw      $6,    6*4($26)       \n"
+    "sw      $7,    7*4($26)       \n"
+
+    "sw      $8,    8*4($26)       \n"
+    "sw      $9,    9*4($26)       \n"
+    "sw      $10,  10*4($26)       \n"
+    "sw      $11,  11*4($26)       \n"
+    "sw      $12,  12*4($26)       \n"
+    "sw      $13,  13*4($26)       \n"
+    "sw      $14,  14*4($26)       \n"
+    "sw      $15,  15*4($26)       \n"
+
+    "sw      $16,  16*4($26)       \n"
+    "sw      $17,  17*4($26)       \n"
+    "sw      $18,  18*4($26)       \n"
+    "sw      $19,  19*4($26)       \n"
+    "sw      $20,  20*4($26)       \n"
+    "sw      $21,  21*4($26)       \n"
+    "sw      $22,  22*4($26)       \n"
+    "sw      $23,  23*4($26)       \n"
+
+    "sw      $24,  24*4($26)       \n"
+    "sw      $25,  25*4($26)       \n"
+
+    "mfhi    $27                   \n"
+    "sw      $27,  26*4($26)       \n"   /* save hi to slot 26 */
+    "mflo    $27                   \n"
+    "sw      $27,  27*4($26)       \n"   /* save lo to slot 27 */
+
+    "sw      $28,  28*4($26)       \n"
+    "sw      $29,  29*4($26)       \n"
+    "sw      $30,  30*4($26)       \n"
+    "sw      $31,  31*4($26)       \n"
+
+	"mfc2    $27,  $0              \n"
+	"sw      $27,  32*4($26)       \n"   /* save c2_ptpr to slot 32 */
+	"mfc2    $27,  $1              \n"
+	"sw      $27,  33*4($26)       \n"   /* save c2_mode to slot 33 */
+
+    "mfc0	 $27,  $12             \n"
+	"sw      $27,  34*4($26)       \n"   /* save c0_sr to slot 34 */
+    "mfc0	 $27,  $4, 2           \n"
+	"sw      $27,  35*4($26)       \n"   /* save c0_th to slot 35 */
+
+    "sync                          \n"
+
+    "move    $4,   $27               \n"
+    "jal     hal_cpu_context_display \n"    /* display context */
+    "nop                             \n"
+
+	".set reorder                  \n"
+    ".set at                       \n"
+    : : : "$26" , "$27" , "memory" ); 
+}
+
+/////////////////////////////////////////////////////////////////////////////////////////
+// These registers are restored from cpu context defined by <ctx> argument:
+// - GPR : all, but (zero, k0, k1), plus (hi, lo)
+// - CP0 : c0_th , c0_sr
+// - CP2 : c2_ptpr , C2_mode
+/////////////////////////////////////////////////////////////////////////////////////////
+void hal_cpu_context_restore( void * ctx )
+{
+    asm volatile(
+    ".set noat                     \n"
+    ".set noreorder                \n"
+    "move    $26,   $4             \n"   /* $26 <= &ctx */
+
+    "lw      $4,   35*4($26)         \n"
+    "jal     hal_cpu_context_display \n"    /* display context */ 
+    "nop                             \n"
+
+    "lw      $27,   0*4($26)       \n"
+    "mtc0    $27,   $14            \n"   /* restore C0_epc from slot 0 */
+
+    "lw      $1,    1*4($26)       \n"
+    "lw      $2,    2*4($26)       \n"
+    "lw      $3,    3*4($26)       \n"
+    "lw      $4,    4*4($26)       \n"
+    "lw      $5,    5*4($26)       \n"
+    "lw      $6,    6*4($26)       \n"
+    "lw      $7,    7*4($26)       \n"
+
+    "lw      $8,    8*4($26)       \n"
+    "lw      $9,    9*4($26)       \n"
+    "lw      $10,  10*4($26)       \n"
+    "lw      $11,  11*4($26)       \n"
+    "lw      $12,  12*4($26)       \n"
+    "lw      $13,  13*4($26)       \n"
+    "lw      $14,  14*4($26)       \n"
+    "lw      $15,  15*4($26)       \n"
+
+	"lw      $16,  16*4($26)       \n"
+	"lw      $17,  17*4($26)       \n"
+    "lw      $18,  18*4($26)       \n"
+    "lw      $19,  19*4($26)       \n"
+    "lw      $20,  20*4($26)       \n"
+    "lw      $21,  21*4($26)       \n"
+    "lw      $22,  22*4($26)       \n"
+    "lw      $23,  23*4($26)       \n"
+
+    "lw      $24,  24*4($26)       \n"
+    "lw      $25,  25*4($26)       \n"
+
+    "lw      $27,  26*4($26)       \n"
+    "mthi    $27                   \n"   /* restore hi from slot 26 */
+    "lw      $27,  27*4($26)       \n"
+    "mtlo    $27                   \n"   /* restote lo from slot 27 */
+
+	"lw      $28,  28*4($26)       \n"
+	"lw      $29,  29*4($26)       \n"
+	"lw      $30,  30*4($26)       \n"
+	"lw      $31,  31*4($26)       \n"
+
+	"lw      $27,  32*4($26)       \n"
+	"mtc2    $27,  $0              \n"   /* restore c2_ptpr from slot 32 */
+	"lw      $27,  33*4($26)       \n"
+	"mtc2    $27,  $1              \n"   /* restore c2_mode from slot 33 */
+
+	"lw      $27,  34*4($26)       \n"
+    "mtc0	 $27,  $12             \n"   /* restore c0_sr from slot 34 */
+	"lw      $27,  35*4($26)       \n"
+    "mtc0	 $27,  $4, 2           \n"   /* restore co_th from slot 35 */
+
+    ".set reorder                  \n"
+    ".set at                       \n"
+    : : : "$26" , "$27" ); 
+}
 
 /////////////////////////////////////////////
@@ -226,64 +430,11 @@
 }  // end hal_fpu_context_destroy()
 
-//////////////////////////////////////////////      
-void hal_cpu_context_save( thread_t * thread )
-{
-    uint32_t ctx = (uint32_t)thread->cpu_context;
-
-    asm volatile(
-    ".set noreorder                \n" 
-    "sw      $16,   0*4(%0)        \n"   /* save s0 to slot 0                   */
-    "sw      $17,   1*4(%0)        \n"   /* save s1 to slot 1                   */
-    "sw      $18,   2*4(%0)        \n"   /* save s2 to slot 2                   */
-    "sw      $19,   3*4(%0)        \n"   /* save s3 to slot 3                   */
-    "sw      $20,   4*4(%0)        \n"   /* save s4 to slot 4                   */
-    "sw      $21,   5*4(%0)        \n"   /* save s5 to slot 5                   */
-    "sw      $22,   6*4(%0)        \n"   /* save s6 to slot 6                   */
-    "sw      $23,   7*4(%0)        \n"   /* save s7 to slot 7                   */
-    "sw      $29,   8*4(%0)        \n"   /* save sp to slot 8                   */
-    "sw      $30,   9*4(%0)        \n"   /* save fp to slot 9                   */
-    "sw      $31,   10*4(%0)       \n"   /* save ra to slot 10                  */
-    "mfc0	 $26,   $4,	  2        \n"   /* get c0_th from CP0                  */
-	"sw      $26,   12*4(%0)       \n"   /* save c0_th to slot 12               */
-	"mfc2    $26,   $0             \n"   /* get c2_ptpr from CP2                */
-	"sw      $26,   13*4(%0)       \n"   /* save c2_ptpr to slot 13             */
-	"mfc2    $26,   $1             \n"   /* get c2_mod from CP2                 */
-	"sw      $26,   14*4(%0)       \n"   /* save c2_mode to slot 14             */
-    "sync                          \n"
-	".set reorder                  \n"
-    : : "r"( ctx ) : "$26" , "memory" ); 
-}
-
-/////////////////////////////////////////////////      
-void hal_cpu_context_restore( thread_t * thread )
-{
-    uint32_t ctx = (uint32_t)thread->cpu_context;
-
-    asm volatile(
-    ".set noreorder                \n"
-    "nop                           \n"
-	"lw      $16,  0*4(%0)         \n"   /* restore s0_16                       */
-	"lw      $17,  1*4(%0)         \n"   /* restore s1_17                       */
-    "lw      $18,  2*4(%0)         \n"   /* restore s2_18                       */
-    "lw      $19,  3*4(%0)         \n"   /* restore s3_19                       */
-    "lw      $20,  4*4(%0)         \n"   /* restore s4_20                       */
-    "lw      $21,  5*4(%0)         \n"   /* restore s5_21                       */
-    "lw      $22,  6*4(%0)         \n"   /* restore s6_22                       */
-    "lw      $23,  7*4(%0)         \n"   /* restore s7_23                       */
-	"lw      $29,  8*4(%0)         \n"   /* restore sp_29                       */	
-	"lw      $30,  9*4(%0)         \n"   /* restore fp_30                       */
-	"lw  	 $31,  10*4(%0)        \n"   /* restore ra_31                       */
-    "lw      $26,  12*4(%0)        \n"   /* get c0_th from slot 12              */
-	"mtc0    $26,  $4,    2        \n"   /* restore c0_th                       */
-    "lw      $26,  13*4(%0)        \n"   /* get c2_ptpr from slot 13            */
-	"mtc2    $26,  $0              \n"   /* restore c2_ptpr                     */
-    "lw      $26,  14*4(%0)        \n"   /* get c2_mode from slot 14            */
-	"mtc2    $26,  $1              \n"   /* restore c2_mode                     */
-    ".set reorder                  \n"
-    : : "r"(ctx)
-      : "$16","$17","$18","$19","$20","$21","$22","$23","$26","$29","$30","$31" ); 
-}
-
-//////////////////////////////////////////////
+/////////////////////////////////////////////////////////////////////////////////////////
+// These registers are initialised:
+// - GPR : sp_29 , fp_30 , a0
+// - CP0 : c0_sr , c0_epc , c0_th
+// - CP2 : C2_ptpr , c2_mode
+// TODO Quand cette fonction est-elle appelée? [AG]
+/////////////////////////////////////////////////////////////////////////////////////////
 void hal_cpu_context_load( thread_t * thread )
 {
Index: trunk/hal/tsar_mips32/core/hal_exception.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_exception.c	(revision 285)
+++ trunk/hal/tsar_mips32/core/hal_exception.c	(revision 296)
@@ -49,11 +49,11 @@
 typedef enum
 {
-    XCODE_ADEL = 4,        // Illegal address for data load 
-    XCODE_ADES = 5,        // Illegal address for data store
-    XCODE_IBE  = 6,        // Instruction MMU exception       (can be NON-FATAL)
-    XCODE_DBE  = 7,        // Data MMU exception              (can be NON-FATAL)
-    XCODE_RI   = 10,       // Reserved instruction exception
-    XCODE_CPU  = 11,       // Coprocessor unusable exception  (can be NON-FATAl)
-    XCODE_OVR  = 12        // Arithmetic Overflow exception
+    XCODE_ADEL = 0x4,        // Illegal address for data load 
+    XCODE_ADES = 0x5,        // Illegal address for data store
+    XCODE_IBE  = 0x6,        // Instruction MMU exception       (can be NON-FATAL)
+    XCODE_DBE  = 0x7,        // Data MMU exception              (can be NON-FATAL)
+    XCODE_RI   = 0xA,        // Reserved instruction exception
+    XCODE_CPU  = 0xB,        // Coprocessor unusable exception  (can be NON-FATAl)
+    XCODE_OVR  = 0xC,        // Arithmetic Overflow exception
 }
 xcode_values_t;
@@ -105,5 +105,5 @@
         case XCODE_RI:   // user fatal error
         {
-            printk("\n[ERROR] in thread %x / arithmetic overflow\n",
+            printk("\n[ERROR] in thread %x / Illegal Codop\n",
 		           this->trdid );
 		    error = EXCP_USER_ERROR;
@@ -123,6 +123,6 @@
         default:
         {
-            printk("\n[PANIC] in %s for thread %x / illegal XCODE value\n",
-		           __FUNCTION__ , this->trdid );
+            printk("\n[PANIC] in %s for thread %x / illegal XCODE value = %x\n",
+		           __FUNCTION__ , this->trdid , excCode );
 		    error = EXCP_USER_ERROR;
         }
@@ -149,37 +149,34 @@
     remote_spinlock_lock( XPTR( LOCAL_CLUSTER->io_cxy , &exception_lock ) );
 
-    // dump core registers values
+    if( this->type == THREAD_USER )
+    printk("\n================= USER ERROR =======================================\n");
+    else
+    printk("\n================= KERNEL PANIC =====================================\n");
 
-    printk("\n====================================================================\n");
-	printk("  thread %x / process %x / core %x / cycle %d\n",
-           this->trdid , this->process->pid , this->core->gid , hal_get_cycles() );
+	printk("  thread type = %s / trdid = %x / pid %x / core[%x,%d]\n"
+           "  local locks = %d / remote locks = %d / blocked_vector = %X\n\n",
+           thread_type_str(this->type), this->trdid, this->process->pid, local_cxy,
+           this->core->lid, this->local_locks, this->remote_locks, this->blocked );
 
-	printk("  - Processor State:\n");
-  
-	printk("    CR:   %x\tEPC:  %x\tSR:   %x\tSP:    %x\n",
+	printk("CR    %X  EPC   %X  SR    %X  SP     %X\n",
 		   regs_tbl[UZ_CR], regs_tbl[UZ_EPC], regs_tbl[UZ_SR], regs_tbl[UZ_SP]);
 
-    printk("    at_1  %x\tv0_2  %x\t\tv1_3  %x\ta0_4   %x\ta1_5   %x\n",
+    printk("at_1  %X  v0_2  %X  v1_3  %X  a0_4   %X  a1_5   %X\n",
    	       regs_tbl[UZ_AT], regs_tbl[UZ_V0], regs_tbl[UZ_V1], regs_tbl[UZ_A0], regs_tbl[UZ_A1]);
 
-    printk("    a2_6  %x\t\ta3_7  %x\tt0_8  %x\tt1_9   %x\tt2_10  %x\n",
+    printk("a2_6  %X  a3_7  %X  t0_8  %X  t1_9   %X  t2_10  %X\n",
 		   regs_tbl[UZ_A2],regs_tbl[UZ_A3],regs_tbl[UZ_T0],regs_tbl[UZ_T1],regs_tbl[UZ_T2]);
   
-    printk("    t3_11 %x\tt4_12 %x\t\tt5_13 %x\tt6_14  %x\tt7_15  %x\n",
+    printk("t3_11 %X  t4_12 %X  t5_13 %X  t6_14  %X  t7_15  %X\n",
 		   regs_tbl[UZ_T3],regs_tbl[UZ_T4],regs_tbl[UZ_T5],regs_tbl[UZ_T6],regs_tbl[UZ_T7]);
 
-    printk("    t8_24 %x\t\tt9_25 %x\tgp_28 %x\tc0_hi  %x\tc0_lo  %x\n",
+    printk("t8_24 %X  t9_25 %X  gp_28 %X  c0_hi  %X  c0_lo  %X\n",
 		   regs_tbl[UZ_T8],regs_tbl[UZ_T9],regs_tbl[UZ_GP],regs_tbl[UZ_HI],regs_tbl[UZ_LO]);
 
-    printk("    s0_16 %x\ts1_17 %x\ts2_18 %x\ts3_19  %x\ts4_20  %x\n",
+    printk("s0_16 %X  s1_17 %X  s2_18 %X  s3_19  %X  s4_20  %X\n",
 		   regs_tbl[UZ_S0],regs_tbl[UZ_S1],regs_tbl[UZ_S2],regs_tbl[UZ_S3],regs_tbl[UZ_S4]);
   
-    printk("    s5_21 %x\ts6_22 %x\t\ts7_23 %x\ts8_30  %x\tra_31  %x\n\n",
+    printk("s5_21 %X  s6_22 %X  s7_23 %X  s8_30  %X  ra_31  %X\n",
 	       regs_tbl[UZ_S5],regs_tbl[UZ_S6],regs_tbl[UZ_S7],regs_tbl[UZ_S8],regs_tbl[UZ_RA]);
-
-    printk("  - Thread State: %x\n"
-           "    type = %s / local_locks = %d / remote_locks = %d / blocked = %x\n",
-           thread_type_str( this->type ), this->local_locks, this->remote_locks,
-           this->blocked );
 
     // release the exception_lock
Index: trunk/hal/tsar_mips32/core/hal_kentry.S
===================================================================
--- trunk/hal/tsar_mips32/core/hal_kentry.S	(revision 285)
+++ trunk/hal/tsar_mips32/core/hal_kentry.S	(revision 296)
@@ -30,5 +30,5 @@
 # or syscall for the TSAR_MIPS32 architecture.  
 #
-# When we enter the kernel, we test the ststus register:
+# When we enter the kernel, we test the status register:
 # - If the core is in user mode, we desactivate the MMU, and we save
 #   the core context in the uzone of the calling thread descriptor.
@@ -42,5 +42,5 @@
 #---------------------------------------------------------------------------------
 
-	.section   .kgiet, "ax", @progbits
+	.section   .kentry, "ax", @progbits
 
 	.extern    hal_do_interrupt
@@ -204,6 +204,6 @@
 # The uzone pointer is saved in $19 to be used by kernel_exit.
 
-	mfc0    $17,    $13                 # $1 <= CR
-	andi    $1,     $1,   0x3F          # $1 <= XCODE
+	mfc0    $17,    $13                 # $17 <= CR
+	andi    $17,    $17,   0x3F         # $17 <= XCODE
 
 	mfc0    $4,     $4,   2             # $4 <= thread pointer (first arg)
@@ -212,7 +212,7 @@
 
 	ori	    $8,     $0,   0x20          # $8 <= cause syscall
-    beq	    $8,	    $1,   cause_sys
-    nop
-	beq     $1,    	$0,	  cause_int
+    beq	    $8,	    $17,  cause_sys     # go to syscall handler
+    nop
+	beq     $17,   	$0,	  cause_int     # go to interrupt handler
     nop
 
Index: trunk/hal/tsar_mips32/core/hal_ppm.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_ppm.c	(revision 285)
+++ trunk/hal/tsar_mips32/core/hal_ppm.c	(revision 296)
@@ -35,8 +35,16 @@
 
 //////////////////////////////////////////////////////////////////////////////////////////
+// This file contains the TSAR specific code for cores registers,
+// and for physical memory allocators initialisation in a given cluster.
+
 // For The TSAR architecture, the kernel pointers are identity mapped:
 // - the 32 bits PTR value is identical to the 32 bits LPA value,
 // - the 64 bits XPTR value is identical to the 64 bits PADDR value.
-// The pages_tbl[] is mapped in first free page after kernel code.
+// This hal_ppm_init() function initializes the pages_tbl[] array used by the generic
+// kmem memory allocator in the local cluster. This array starts in first free page
+// after kernel code, as defined by the 'offset' field in boot_info.
+//
+// For the TSAR architecture the MIP32 EBASE register defining the kernel entry point
+// fot Interrupts, Exceptions and Syscalls, has to be redefined.
 //////////////////////////////////////////////////////////////////////////////////////////
 
@@ -49,5 +57,4 @@
 	uint32_t pages_nr         = info->pages_nr;
 	uint32_t pages_tbl_offset = info->pages_offset;
-	uint32_t rsvd_nr          = info->rsvd_nr;
 
 	// get pointer on local Physical Page Manager
@@ -113,4 +120,15 @@
 	// check consistency
 	return ppm_assert_order( ppm );
-}
 
+}  // end hal_ppm_init()
+
+////////////////////////////////////////
+void hal_core_init( boot_info_t * info )
+{
+	// get relevant info from boot_info structure
+	reg_t kentry_base = info->kentry_base;
+
+    // set CP0_EBASE register
+    hal_set_ebase( kentry_base );
+
+}  // end hal_core_init()
Index: trunk/hal/tsar_mips32/core/hal_remote.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_remote.c	(revision 285)
+++ trunk/hal/tsar_mips32/core/hal_remote.c	(revision 296)
@@ -30,10 +30,6 @@
                     uint8_t  data )
 {
-    uint32_t save_sr;
-    uint32_t ptr = (uint32_t)GET_PTR( xp );
-    uint32_t cxy = (uint32_t)GET_CXY( xp );
-
-/* TODO improve all hal remote functions to include SR handling in assembly code */
-/* as it is done below for hal_remote_sb                                         */
+    uint32_t ptr = (uint32_t)GET_PTR( xp );
+    uint32_t cxy = (uint32_t)GET_CXY( xp );
 
     asm volatile( 
@@ -44,5 +40,4 @@
         "mtc0   $13,    $12          \n"  /* IRQ disabled       */
         
-
         "mfc2   $15,    $24          \n"  /* $15 <= PADDR_EXT   */   
         "mtc2   %2,     $24          \n"  /* PADDR_EXT <= cxy   */   
@@ -61,21 +56,24 @@
                     uint32_t  data )
 {
-    uint32_t save_sr;
-    uint32_t ptr = (uint32_t)GET_PTR( xp );
-    uint32_t cxy = (uint32_t)GET_CXY( xp );
-
-    hal_disable_irq( &save_sr );
-
-    asm volatile( "mfc2   $15,    $24          \n"  /* $15 <= PADDR_EXT */   
-        ".set noreorder              \n"
-        "mtc2   %2,     $24          \n"  /* PADDR_EXT <= cxy */   
-        "sw     %0,     0(%1)        \n"  /* *paddr <= value  */
-        "mtc2   $15,    $24          \n"  /* PADDR_EXT <= $15 */   
+    uint32_t ptr = (uint32_t)GET_PTR( xp );
+    uint32_t cxy = (uint32_t)GET_CXY( xp );
+
+    asm volatile( 
+        ".set noreorder              \n"
+        "mfc0   $14,    $12          \n"  /* $14 <= CP0_SR      */
+        "srl    $13,    $14,    1    \n" 
+        "sll    $13,    $13,    1    \n"  /* $13 <= SR masked   */
+        "mtc0   $13,    $12          \n"  /* IRQ disabled       */
+
+        "mfc2   $15,    $24          \n"  /* $15 <= PADDR_EXT   */   
+        "mtc2   %2,     $24          \n"  /* PADDR_EXT <= cxy   */   
+        "sw     %0,     0(%1)        \n"  /* *paddr <= value    */
+        "mtc2   $15,    $24          \n"  /* PADDR_EXT <= $15   */   
+
+        "mtc0   $14,    $12          \n"  /* SR restored        */
+
         "sync                        \n"
         ".set reorder                \n"
-        : : "r" (data), "r" (ptr), "r" (cxy) : "$15" );
-
-    hal_restore_irq( save_sr );
-
+        : : "r" (data), "r" (ptr), "r" (cxy) : "$13", "$14", "$15" );
 }
 
@@ -84,5 +82,4 @@
                      uint64_t  data )
 {
-    uint32_t save_sr;
     uint32_t ptr = (uint32_t)GET_PTR( xp );
     uint32_t cxy = (uint32_t)GET_CXY( xp );
@@ -91,19 +88,22 @@
     uint32_t data_msb = (uint32_t)(data>>32);
 
-    hal_disable_irq( &save_sr );
-
-    asm volatile( 
-        ".set noreorder              \n"
-        "mfc2   $15,    $24          \n"  /* $15 <= PADDR_EXT  */   
-        "mtc2   %3,     $24          \n"  /* PADDR_EXT <= cxy  */   
-        "sw     %0,     0(%2)        \n"  /* *paddr <= lsb     */
-        "sw     %1,     4(%2)        \n"  /* *(paddr+4) <= msb */
-        "mtc2   $15,    $24          \n"  /* PADDR_EXT <= $15  */   
+    asm volatile( 
+        ".set noreorder              \n"
+        "mfc0   $14,    $12          \n"  /* $14 <= CP0_SR      */
+        "srl    $13,    $14,    1    \n" 
+        "sll    $13,    $13,    1    \n"  /* $13 <= SR masked   */
+        "mtc0   $13,    $12          \n"  /* IRQ disabled       */
+
+        "mfc2   $15,    $24          \n"  /* $15 <= PADDR_EXT   */   
+        "mtc2   %3,     $24          \n"  /* PADDR_EXT <= cxy   */   
+        "sw     %0,     0(%2)        \n"  /* *paddr <= lsb      */
+        "sw     %1,     4(%2)        \n"  /* *(paddr+4) <= msb  */
+        "mtc2   $15,    $24          \n"  /* PADDR_EXT <= $15   */   
+
+        "mtc0   $14,    $12          \n"  /* SR restored        */
+
         "sync                        \n"
         ".set reorder                \n"
-        : : "r" (data_lsb), "r" (data_msb), "r" (ptr), "r" (cxy) : "$15" );
-
-    hal_restore_irq( save_sr );
-
+        : : "r" (data_lsb), "r" (data_msb), "r" (ptr), "r" (cxy) : "$13", "$14", "$15" );
 }
 
@@ -118,21 +118,23 @@
 uint8_t hal_remote_lb( xptr_t  xp )
 {
-    uint32_t save_sr;
 	char     data;
     uint32_t ptr = (uint32_t)GET_PTR( xp );
     uint32_t cxy = (uint32_t)GET_CXY( xp );
 
-    hal_disable_irq( &save_sr );
-
-    asm volatile( 
-        ".set noreorder              \n"
+    asm volatile( 
+        ".set noreorder              \n"
+        "mfc0   $14,    $12          \n"  /* $14 <= CP0_SR      */
+        "srl    $13,    $14,    1    \n" 
+        "sll    $13,    $13,    1    \n"  /* $13 <= SR masked   */
+        "mtc0   $13,    $12          \n"  /* IRQ disabled       */
+
         "mfc2   $15,    $24          \n"  /* $15 <= PADDR_EXT   */ 
         "mtc2   %2,     $24          \n"  /* PADDR_EXT <= cxy   */   
         "lb     %0,     0(%1)        \n"  /* data <= *paddr     */
         "mtc2   $15,    $24          \n"  /* PADDR_EXT <= $15   */   
-        ".set reorder                \n"
-        : "=r" (data) : "r" (ptr), "r" (cxy) : "$15" );
-
-    hal_restore_irq( save_sr );
+
+        "mtc0   $14,    $12          \n"  /* SR restored        */
+        ".set reorder                \n"
+        : "=r" (data) : "r" (ptr), "r" (cxy) : "$13", "$14", "$15" );
 
 	return ( data );
@@ -142,21 +144,23 @@
 uint32_t hal_remote_lw( xptr_t  xp )
 {
-    uint32_t save_sr;
 	uint32_t data;
     uint32_t ptr = (uint32_t)GET_PTR( xp );
     uint32_t cxy = (uint32_t)GET_CXY( xp );
 
-    hal_disable_irq( &save_sr );
-
-    asm volatile( 
-        ".set noreorder              \n"
+    asm volatile( 
+        ".set noreorder              \n"
+        "mfc0   $14,    $12          \n"  /* $14 <= CP0_SR      */
+        "srl    $13,    $14,    1    \n" 
+        "sll    $13,    $13,    1    \n"  /* $13 <= SR masked   */
+        "mtc0   $13,    $12          \n"  /* IRQ disabled       */
+
         "mfc2   $15,    $24          \n"  /* $15 <= PADDR_EXT   */ 
         "mtc2   %2,     $24          \n"  /* PADDR_EXT <= cxy   */   
         "lw     %0,     0(%1)        \n"  /* data <= *paddr     */
         "mtc2   $15,    $24          \n"  /* PADDR_EXT <= $15   */   
-        ".set reorder                \n"
-        : "=r" (data) : "r" (ptr), "r" (cxy) : "$15" );
-
-    hal_restore_irq( save_sr );
+
+        "mtc0   $14,    $12          \n"  /* SR restored        */
+        ".set reorder                \n"
+        : "=r" (data) : "r" (ptr), "r" (cxy) : "$13", "$14", "$15" );
 
     return ( data );
@@ -166,5 +170,4 @@
 uint64_t hal_remote_lwd( xptr_t  xp )
 {
-    uint32_t save_sr;
     uint32_t data_lsb;
     uint32_t data_msb;
@@ -172,8 +175,11 @@
     uint32_t cxy = (uint32_t)GET_CXY( xp );
 
-    hal_disable_irq( &save_sr );
-
-    asm volatile( 
-        ".set noreorder              \n"
+    asm volatile( 
+        ".set noreorder              \n"
+        "mfc0   $14,    $12          \n"  /* $14 <= CP0_SR        */
+        "srl    $13,    $14,    1    \n" 
+        "sll    $13,    $13,    1    \n"  /* $13 <= SR masked     */
+        "mtc0   $13,    $12          \n"  /* IRQ disabled         */
+
         "mfc2   $15,    $24          \n"  /* $15 <= PADDR_EXT     */ 
         "mtc2   %3,     $24          \n"  /* PADDR_EXT <= cxy     */   
@@ -181,8 +187,8 @@
         "lw     %1,     4(%2)        \n"  /* data_msb <= *paddr+4 */
         "mtc2   $15,    $24          \n"  /* PADDR_EXT <= $15     */   
-        ".set reorder                \n"
-        : "=r" (data_lsb), "=r"(data_msb) : "r" (ptr), "r" (cxy) : "$15" );
-
-    hal_restore_irq( save_sr );
+
+        "mtc0   $14,    $12          \n"  /* SR restored          */
+        ".set reorder                \n"
+        : "=r" (data_lsb), "=r"(data_msb) : "r" (ptr), "r" (cxy) : "$13", "$14", "$15" );
 
     return ( (((uint64_t)data_msb)<<32) + (((uint64_t)data_lsb)) );
Index: trunk/hal/tsar_mips32/core/hal_special.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_special.c	(revision 285)
+++ trunk/hal/tsar_mips32/core/hal_special.c	(revision 296)
@@ -48,8 +48,8 @@
 }
 
-////////////////////////////////
-inline cycle_t hal_time_stamp()
-{
-    cycle_t count;
+/////////////////////////////
+inline reg_t hal_time_stamp()
+{
+    reg_t count;
 
 	asm volatile ("mfc0   %0,  $9" : "=&r" (count));
@@ -61,5 +61,5 @@
 inline reg_t hal_get_sr()
 {
-    register uint32_t sr;
+    reg_t sr;
 
 	asm volatile ("mfc0    %0,    $12" : "=&r" (sr));
