Index: trunk/hal/tsar_mips32/core/hal_gpt.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_gpt.c	(revision 391)
+++ trunk/hal/tsar_mips32/core/hal_gpt.c	(revision 401)
@@ -35,9 +35,9 @@
 
 ////////////////////////////////////////////////////////////////////////////////////////
-// This define the masks for the TSAR MMU PTE attributes. (from TSAR MMU specification)
+// This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification)
 ////////////////////////////////////////////////////////////////////////////////////////
 
-#define TSAR_MMU_PRESENT        0x80000000 
-#define TSAR_MMU_PTD1           0x40000000 
+#define TSAR_MMU_MAPPED         0x80000000 
+#define TSAR_MMU_SMALL          0x40000000 
 #define TSAR_MMU_LOCAL          0x20000000 
 #define TSAR_MMU_REMOTE         0x10000000 
@@ -49,7 +49,7 @@
 #define TSAR_MMU_DIRTY          0x00400000 
 
-#define TSAR_MMU_COW            0x00000001
-#define TSAR_MMU_SWAP           0x00000004
-#define TSAR_MMU_LOCKED         0x00000008
+#define TSAR_MMU_COW            0x00000001       // only for small pages
+#define TSAR_MMU_SWAP           0x00000004       // only for small pages
+#define TSAR_MMU_LOCKED         0x00000008       // only for small pages
 
 ////////////////////////////////////////////////////////////////////////////////////////
@@ -64,4 +64,7 @@
 #define TSAR_MMU_PPN_WIDTH                 28
 
+#define TSAR_MMU_PTE1_ATTR_MASK            0xFFC00000
+#define TSAR_MMU_PTE1_PPN_MASK             0x0007FFFF
+
 #define TSAR_MMU_IX1_FROM_VPN( vpn )       ((vpn >> 9) & 0x7FF)
 #define TSAR_MMU_IX2_FROM_VPN( vpn )       (vpn & 0x1FF)
@@ -73,4 +76,53 @@
 #define TSAR_MMU_PPN_FROM_PTE2( pte2 )     (pte2 & 0x0FFFFFFF) 
 #define TSAR_MMU_ATTR_FROM_PTE2( pte2 )    (pte2 & 0xFFC000FF)
+
+
+///////////////////////////////////////////////////////////////////////////////////////
+// This static function translates the GPT attributes to the TSAR attributes
+///////////////////////////////////////////////////////////////////////////////////////
+static inline uint32_t gpt2tsar( uint32_t gpt_attr )
+{
+    uint32_t tsar_attr = 0;
+
+    if( gpt_attr & GPT_MAPPED     ) tsar_attr |= TSAR_MMU_MAPPED;
+    if( gpt_attr & GPT_SMALL      ) tsar_attr |= TSAR_MMU_SMALL;
+    if( gpt_attr & GPT_WRITABLE   ) tsar_attr |= TSAR_MMU_WRITABLE;
+    if( gpt_attr & GPT_EXECUTABLE ) tsar_attr |= TSAR_MMU_EXECUTABLE;
+    if( gpt_attr & GPT_CACHABLE   ) tsar_attr |= TSAR_MMU_CACHABLE; 
+    if( gpt_attr & GPT_USER       ) tsar_attr |= TSAR_MMU_USER;
+    if( gpt_attr & GPT_DIRTY      ) tsar_attr |= TSAR_MMU_DIRTY;
+    if( gpt_attr & GPT_ACCESSED   ) tsar_attr |= TSAR_MMU_LOCAL;
+    if( gpt_attr & GPT_GLOBAL     ) tsar_attr |= TSAR_MMU_GLOBAL;
+    if( gpt_attr & GPT_COW        ) tsar_attr |= TSAR_MMU_COW;
+    if( gpt_attr & GPT_SWAP       ) tsar_attr |= TSAR_MMU_SWAP;
+    if( gpt_attr & GPT_LOCKED     ) tsar_attr |= TSAR_MMU_LOCKED;
+
+    return tsar_attr;
+}
+
+///////////////////////////////////////////////////////////////////////////////////////
+// This static function translates the TSAR attributes to the GPT attributes
+///////////////////////////////////////////////////////////////////////////////////////
+static inline uint32_t tsar2gpt( uint32_t tsar_attr )
+{
+    uint32_t gpt_attr = 0;
+
+    if( tsar_attr & TSAR_MMU_MAPPED     ) gpt_attr |= GPT_MAPPED;
+    if( tsar_attr & TSAR_MMU_MAPPED     ) gpt_attr |= GPT_READABLE;
+    if( tsar_attr & TSAR_MMU_SMALL      ) gpt_attr |= GPT_SMALL;
+    if( tsar_attr & TSAR_MMU_WRITABLE   ) gpt_attr |= GPT_WRITABLE;
+    if( tsar_attr & TSAR_MMU_EXECUTABLE ) gpt_attr |= GPT_EXECUTABLE;
+    if( tsar_attr & TSAR_MMU_CACHABLE   ) gpt_attr |= GPT_CACHABLE; 
+    if( tsar_attr & TSAR_MMU_USER       ) gpt_attr |= GPT_USER;
+    if( tsar_attr & TSAR_MMU_DIRTY      ) gpt_attr |= GPT_DIRTY;
+    if( tsar_attr & TSAR_MMU_LOCAL      ) gpt_attr |= GPT_ACCESSED;
+    if( tsar_attr & TSAR_MMU_REMOTE     ) gpt_attr |= GPT_ACCESSED;
+    if( tsar_attr & TSAR_MMU_GLOBAL     ) gpt_attr |= GPT_GLOBAL;
+    if( tsar_attr & TSAR_MMU_COW        ) gpt_attr |= GPT_COW;
+    if( tsar_attr & TSAR_MMU_SWAP       ) gpt_attr |= GPT_SWAP;
+    if( tsar_attr & TSAR_MMU_LOCKED     ) gpt_attr |= GPT_LOCKED;
+
+    return gpt_attr;
+}
 
 /////////////////////////////////////
@@ -107,20 +159,4 @@
 	gpt->page = GET_PTR( page_xp );
 
-/*
-    // initialize PTE entries attributes masks
-    GPT_MAPPED     = TSAR_MMU_PRESENT;
-    GPT_SMALL      = TSAR_MMU_PTD1;
-    GPT_READABLE   = TSAR_MMU_PRESENT;
-    GPT_WRITABLE   = TSAR_MMU_WRITABLE;
-    GPT_EXECUTABLE = TSAR_MMU_EXECUTABLE;
-    GPT_CACHABLE   = TSAR_MMU_CACHABLE;
-    GPT_USER       = TSAR_MMU_USER;     
-    GPT_DIRTY      = TSAR_MMU_DIRTY;    
-    GPT_ACCESSED   = TSAR_MMU_LOCAL | TSAR_MMU_REMOTE;
-    GPT_GLOBAL     = TSAR_MMU_GLOBAL; 
-    GPT_COW        = TSAR_MMU_COW;
-    GPT_SWAP       = TSAR_MMU_SWAP;
-    GPT_LOCKED     = TSAR_MMU_LOCKED;
-*/
 	return 0;
 } // end hal_gpt_create()
@@ -154,7 +190,7 @@
 	{
         pte1 = pt1[ix1];
-		if( (pte1 & TSAR_MMU_PRESENT) != 0 )  // PTE1 valid
+		if( (pte1 & TSAR_MMU_MAPPED) != 0 )  // PTE1 valid
         {
-            if( (pte1 & TSAR_MMU_PTD1) == 0 )   // BIG page
+            if( (pte1 & TSAR_MMU_SMALL) == 0 )   // BIG page
             {
                 if( (pte1 & TSAR_MMU_USER) != 0 ) 
@@ -185,5 +221,5 @@
                     {
                         attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] );
-		                if( ((attr & TSAR_MMU_PRESENT) != 0 ) && ((attr & TSAR_MMU_USER) != 0) )  
+		                if( ((attr & TSAR_MMU_MAPPED) != 0 ) && ((attr & TSAR_MMU_USER) != 0) )  
                         {
                             // release the physical page
@@ -230,7 +266,7 @@
 	{
         pte1 = pt1[ix1];
-		if( (pte1 & TSAR_MMU_PRESENT) != 0 )
+		if( (pte1 & TSAR_MMU_MAPPED) != 0 )
         {
-            if( (pte1 & TSAR_MMU_PTD1) == 0 )  // BIG page
+            if( (pte1 & TSAR_MMU_SMALL) == 0 )  // BIG page
             {
                 printk(" - BIG   : pt1[%d] = %x\n", ix1 , pte1 );
@@ -247,5 +283,5 @@
                     pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( pt2[2 * ix2] );
                     pte2_ppn  = TSAR_MMU_PPN_FROM_PTE2( pt2[2 * ix2 + 1] );
-		            if( (pte2_attr & TSAR_MMU_PRESENT) != 0 )
+		            if( (pte2_attr & TSAR_MMU_MAPPED) != 0 )
                     {
                         printk(" - SMALL   : pt1[%d] = %x / pt2[%d] / pt2[%d]\n",
@@ -263,21 +299,23 @@
                          vpn_t     vpn,
                          ppn_t     ppn,
-                         uint32_t  attr )
-{
-    uint32_t          * pt1;         // virtual base addres of PT1
-	volatile uint32_t * pte1_ptr;    // pointer on PT1 entry
-	uint32_t            pte1;        // PT1 entry value
-
-	ppn_t               pt2_ppn;     // PPN of PT2
-	uint32_t          * pt2;         // virtual base address of PT2
-
-	uint32_t            small;       // requested PTE is for a small page
+                         uint32_t  attr )    // generic GPT attributes
+{
+    uint32_t          * pt1;                 // virtual base addres of PT1
+	volatile uint32_t * pte1_ptr;            // pointer on PT1 entry
+	uint32_t            pte1;                // PT1 entry value
+
+	ppn_t               pt2_ppn;             // PPN of PT2
+	uint32_t          * pt2;                 // virtual base address of PT2
+
+	uint32_t            small;               // requested PTE is for a small page
 	bool_t              atomic;
 
-	page_t            * page;        // pointer on new physical page descriptor
-    xptr_t              page_xp;     // extended pointer on new page descriptor
-
-    uint32_t            ix1;         // index in PT1
-    uint32_t            ix2;         // index in PT2
+	page_t            * page;                // pointer on new physical page descriptor
+    xptr_t              page_xp;             // extended pointer on new page descriptor
+
+    uint32_t            ix1;                 // index in PT1
+    uint32_t            ix2;                 // index in PT2
+
+    uint32_t            tsar_attr;           // PTE attributes for TSAR MMU
 
     // compute indexes in PT1 and PT2
@@ -286,5 +324,8 @@
 
     pt1   = gpt->ptr;
-	small = (attr & TSAR_MMU_PTD1);
+	small = attr & GPT_SMALL;
+
+    // compute tsar_attr from generic attributes
+    tsar_attr = gpt2tsar( attr );
 
     // get PT1 entry value
@@ -294,15 +335,15 @@
     // Big pages (PTE1) are only set for the kernel vsegs, in the kernel init phase.
     // There is no risk of concurrent access.
-	if( small == 0 )
-	{
-		if( (pte1 != 0) || (attr & GPT_COW) )
+	if( small == 0 ) 
+    {
+        if( pte1 != 0 )
 		{
-			printk("\n[ERROR] in %s : set a big page in a mapped PT1 entry / PT1[%d] = %x\n",
+			panic("\n[PANIC] in %s : set a big page in a mapped PT1 entry / PT1[%d] = %x\n",
                    __FUNCTION__ , ix1 , pte1 );
-			return EINVAL;
 		}
       
         // set the PTE1 
-		*pte1_ptr = attr | (ppn >> 9);
+		*pte1_ptr = (tsar_attr  & TSAR_MMU_PTE1_ATTR_MASK) | 
+                    ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK);
 		hal_fence();
 		return 0;
@@ -311,5 +352,5 @@
     // From this point, the requested PTE is a PTE2 (small page)
 
-	if( (pte1 & TSAR_MMU_PRESENT) == 0 )      // the PT1 entry is not valid
+	if( (pte1 & TSAR_MMU_MAPPED) == 0 )      // the PT1 entry is not valid
 	{
         // allocate one physical page for the PT2
@@ -334,5 +375,5 @@
 		{
 		    atomic = hal_atomic_cas( (void*)pte1, 0 , 
-                                      TSAR_MMU_PRESENT | TSAR_MMU_PTD1 | pt2_ppn );
+                                      TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn );
         } 
         while( (atomic == false) && (*pte1_ptr == 0) );
@@ -356,5 +397,5 @@
 	{
         // This valid entry must be a PTD1
-        if( (pte1 & TSAR_MMU_PTD1) == 0 )
+        if( (pte1 & TSAR_MMU_SMALL) == 0 )
         {
 			printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n",
@@ -373,8 +414,9 @@
 	pt2[2 * ix2 + 1] = ppn;
 	hal_fence();
-	pt2[2 * ix2]     = attr;
+	pt2[2 * ix2]     = tsar_attr;
 	hal_fence();
 
 	return 0;
+
 } // end of hal_gpt_set_pte()
 
@@ -398,5 +440,5 @@
     pte1 = pt1[ix1];
 
-	if( (pte1 & TSAR_MMU_PRESENT) == 0 )   // PT1 entry not present
+	if( (pte1 & TSAR_MMU_MAPPED) == 0 )   // PT1 entry not present
 	{
 		*attr = 0;
@@ -404,7 +446,7 @@
 	}
 
-	if( (pte1 & TSAR_MMU_PTD1) == 0 )     // it's a PTE1
-	{
-		*attr = TSAR_MMU_ATTR_FROM_PTE1( pte1 );
+	if( (pte1 & TSAR_MMU_SMALL) == 0 )     // it's a PTE1
+	{
+		*attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) );
         *ppn  = TSAR_MMU_PPN_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1));
 	}
@@ -416,5 +458,5 @@
 
 	    *ppn  = pt2[2*ix2+1] & ((1<<TSAR_MMU_PPN_WIDTH)-1);
-	    *attr = pt2[2*ix2];
+	    *attr = tsar2gpt( pt2[2*ix2] );
     }
 } // end hal_gpt_get_pte()
@@ -432,26 +474,18 @@
     ppn_t      ppn;         // PPN of page to be released
 
-    kmem_req_t req;
-
     // get ix1 & ix2 indexes
     uint32_t   ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
     uint32_t   ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
 
-    // get pointer on calling process
-    process_t  * process = CURRENT_THREAD->process;
-
-    // compute is_ref 
-    bool_t is_ref = ( GET_CXY( process->ref_xp ) == local_cxy );
-
     // get PTE1 value 
 	pt1      = gpt->ptr;
     pte1     = pt1[ix1];
 
-	if( (pte1 & TSAR_MMU_PRESENT) == 0 )   // PT1 entry not present
+	if( (pte1 & TSAR_MMU_MAPPED) == 0 )   // PT1 entry not present
 	{
 		return;
 	}
 
-	if( (pte1 & TSAR_MMU_PTD1) == 0 )      // it's a PTE1
+	if( (pte1 & TSAR_MMU_SMALL) == 0 )      // it's a PTE1
 	{
         // get PPN 
@@ -461,10 +495,4 @@
         pt1[ix1] = 0;
 	    hal_fence();
-
-        // releases the physical page if local
-        // req.type  = KMEM_PAGE;
-	    // req.size  = 9;
-        // req.ptr   = (void*)(ppn << CONFIG_PPM_PAGE_SHIFT);
-	    // kmem_free( &req );
 
         return;
@@ -483,10 +511,4 @@
 	    hal_fence();        
 
-        // releases the small page 
-        // req.type  = KMEM_PAGE;
-	    // req.size  = 0;
-        // req.ptr   = (void*)(ppn << CONFIG_PPM_PAGE_SHIFT);
-	    // kmem_free( &req );
-
         return;
     }
@@ -519,5 +541,5 @@
 
     // If present, the page must be small
-	if( ((pte1 & TSAR_MMU_PRESENT) != 0) && ((pte1 & TSAR_MMU_PTD1) == 0) )
+	if( ((pte1 & TSAR_MMU_MAPPED) != 0) && ((pte1 & TSAR_MMU_SMALL) == 0) )
     {
         printk("\n[ERROR] in %s : try to lock a big page / PT1[%d] = %x\n",
@@ -526,5 +548,5 @@
     }
 
-	if( (pte1 & TSAR_MMU_PRESENT) == 0 )  // missing PT1 entry   
+	if( (pte1 & TSAR_MMU_MAPPED) == 0 )  // missing PT1 entry   
 	{
         // allocate one physical page for PT2
@@ -550,5 +572,5 @@
 		{
 			atomic = hal_atomic_cas( (void*)pte1_ptr , 0 , 
-                                     TSAR_MMU_PRESENT | TSAR_MMU_PTD1 | pt2_ppn );
+                                     TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn );
 		} 
         while( (atomic == false) && (*pte1_ptr == 0) );
@@ -570,5 +592,5 @@
     {
         // This valid entry must be a PTD1
-        if( (pte1 & TSAR_MMU_PTD1) == 0 )
+        if( (pte1 & TSAR_MMU_SMALL) == 0 )
         {
 			printk("\n[ERROR] in %s : set a small page in a big PT1 entry / PT1[%d] = %x\n",
@@ -592,5 +614,5 @@
 	do
     {
-        // busy waiting until GPT_LOCK == 0
+        // busy waiting until TSAR_MMU_LOCK == 0
         do
 		{
@@ -598,12 +620,12 @@
 			hal_rdbar();
 		}
-        while( (attr & GPT_LOCKED) != 0 );
-
-        // try to set the GPT_LOCK wit a CAS
-		atomic = hal_atomic_cas( (void*)pte2_ptr, attr , (attr | GPT_LOCKED) );
+        while( (attr & TSAR_MMU_LOCKED) != 0 );
+
+		atomic = hal_atomic_cas( (void*)pte2_ptr, attr , (attr | TSAR_MMU_LOCKED) );
 	}
     while( atomic == 0 );
 
 	return 0;
+
 }  // end hal_gpt_lock_pte()
 
@@ -632,5 +654,5 @@
 
     // check PTE1 present and small page
-    if( ((pte1 & TSAR_MMU_PRESENT) == 0) || ((pte1 & TSAR_MMU_PTD1) == 0) )
+    if( ((pte1 & TSAR_MMU_MAPPED) == 0) || ((pte1 & TSAR_MMU_SMALL) == 0) )
     {
         printk("\n[ERROR] in %s : try to unlock a big or undefined page / PT1[%d] = %x\n",
@@ -650,7 +672,7 @@
 
     // check PTE2 present and locked
-    if( ((attr & TSAR_MMU_PRESENT) == 0) || ((attr & GPT_LOCKED) == 0) );
-    {
-        printk("\n[ERROR] in %s : try to unlock an undefined page / PT1[%d] = %x\n",
+    if( ((attr & TSAR_MMU_MAPPED) == 0) || ((attr & TSAR_MMU_LOCKED) == 0) );
+    {
+        printk("\n[ERROR] in %s : unlock an unlocked/unmapped page / PT1[%d] = %x\n",
                  __FUNCTION__ , ix1 , pte1 );
         return EINVAL;
@@ -658,7 +680,8 @@
 
     // reset GPT_LOCK
-	*pte2_ptr = attr & !GPT_LOCKED;
+	*pte2_ptr = attr & ~TSAR_MMU_LOCKED;
 
 	return 0;
+
 }  // end hal_gpt_unlock_pte()
 
@@ -695,7 +718,7 @@
 	{
         pte1 = src_pt1[ix1];
-		if( (pte1 & TSAR_MMU_PRESENT) != 0 )
+		if( (pte1 & TSAR_MMU_MAPPED) != 0 )
         {
-            if( (pte1 & TSAR_MMU_PTD1) == 0 )  // PTE1 => big kernel page
+            if( (pte1 & TSAR_MMU_SMALL) == 0 )  // PTE1 => big kernel page
             {
                 // big kernel pages are shared by all processes => copy it
@@ -727,5 +750,5 @@
                 // set a new PTD1 in DST_GPT
                 dst_pt2_ppn  = (ppn_t)ppm_page2ppn( page_xp );
-                dst_pt1[ix1] = TSAR_MMU_PRESENT | TSAR_MMU_PTD1 | dst_pt2_ppn;
+                dst_pt1[ix1] = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | dst_pt2_ppn;
 
                 // get pointer on PT2 in SRC_GPT
@@ -739,5 +762,5 @@
                     pte2_attr = TSAR_MMU_ATTR_FROM_PTE2( src_pt2[2 * ix2] );
 
-		            if( (pte2_attr & TSAR_MMU_PRESENT) != 0 )  // valid PTE2 in SRC_GPT
+		            if( (pte2_attr & TSAR_MMU_MAPPED) != 0 )  // valid PTE2 in SRC_GPT
                     {
                         // get GPT_WRITABLE & PPN
