Changeset 406 for trunk/hal/tsar_mips32/core/hal_kentry.h

Timestamp:

Aug 29, 2017, 12:03:37 PM (7 years ago)

Author:

alain

Message:

This version executed successfully the user "init" process on a mono-processor TSAR architecture.

File:

• trunk/hal/tsar_mips32/core/hal_kentry.h (modified) (1 diff)

trunk/hal/tsar_mips32/core/hal_kentry.h

@@ -24 +24 @@
 #define _HAL_KENTRY_H_
 
+//////////////////////////////////////////////////////////////////////////////////////////
+// This file defines the MIPS32 specific mnemonics to access the "uzone", that is
+// a fixed size array of 32 bits integers, used by the kentry function to save/restore 
+// the MIPS32 CPU registers, at each exception / interruption / syscall.
+// It also defines several initial values for the SR register.
+//
+// This file is included in the hal_kentry.S, hal_syscall.c, hal_exception.c,
+// and hal_context.c files.
+//////////////////////////////////////////////////////////////////////////////////////////
 
-#define CPU_IN_KERNEL 1
+
+/****************************************************************************************
+ * This structure defines the cpu_uzone for TSAR MIPS32, as well as the
+ *  mnemonics used by the hal_kentry assembly code.
+ ***************************************************************************************/
+
+#define      UZ_MODE         0    /* c2_mode */             
+#define      UZ_AT           1
+#define      UZ_V0           2
+#define      UZ_V1           3
+#define      UZ_A0           4 
+#define      UZ_A1           5
+#define      UZ_A2           6
+#define      UZ_A3           7
+#define      UZ_T0           8
+#define      UZ_T1           9
+#define      UZ_T2           10
+#define      UZ_T3           11
+#define      UZ_T4           12
+#define      UZ_T5           13
+#define      UZ_T6           14
+#define      UZ_T7           15
+#define      UZ_T8           16
+#define      UZ_T9           17
+#define      UZ_S0           18
+#define      UZ_S1           19
+#define      UZ_S2           20
+#define      UZ_S3           21
+#define      UZ_S4           22
+#define      UZ_S5           23
+#define      UZ_S6           24
+#define      UZ_S7           25
+#define      UZ_S8           26
+#define      UZ_GP           27
+#define      UZ_RA           28
+#define      UZ_EPC          29   /* c0_epc */
+#define      UZ_CR           30   /* c0_cr */
+#define      UZ_SP           31
+#define      UZ_SR           32   /* c0_sr */
+#define      UZ_LO           33
+#define      UZ_HI           34
+
+#define      UZ_REGS         35
+
+/*************************************************************************************
+ * The hal_kentry_enter() function is the unique kernel entry point in case of 
+ * exception, interrupt, or syscall for the TSAR_MIPS32 architecture.  
+ *
+ * When we enter the kernel, we test the status register:
+ * - If the core is in user mode, we desactivate the MMU, and we save
+ *   the core context in the uzone of the calling thread descriptor.
+ * - If the core is already in kernel mode (in case of interrupt), 
+ *   we save the context in the kernel stack.
+ * - In both cases, we increment the cores_in_kernel variable,
+ *   and we call the relevant exception/interrupt/syscall handler
+ *
+ * When we exit the kernel after handler execution:
+ * - we restore the core context from the uzone and return to user space,
+ *   calling the hal_kentry_eret()
+ ************************************************************************************/
+void hal_kentry_enter();
+
+/*************************************************************************************
+ * The hal_kentry_eret() function contains only the assembly "eret" instruction,
+ * that and the EXL bit in the c0_sr register, and jump to the address 
+ * contained in the c0_epc register. 
+ * ************************************************************************************/
+void hal_kentry_eret();
 
 #endif  /* _HAL_KENTRY_H_ */