Changeset 408 for trunk/hal/tsar_mips32/core/hal_kentry.h

Timestamp:

Dec 5, 2017, 4:20:07 PM (6 years ago)

Author:

alain

Message:

Fix several bugs in the fork() syscall.

File:

• trunk/hal/tsar_mips32/core/hal_kentry.h (modified) (3 diffs)

trunk/hal/tsar_mips32/core/hal_kentry.h

@@ -36 +36 @@
 
 /****************************************************************************************
- * This structure defines the cpu_uzone for TSAR MIPS32, as well as the
- *  mnemonics used by the hal_kentry assembly code.
+ * This structure defines the cpu_uzone dynamically allocated in the kernel stack
+ * by the hal_kentry assembly code for the TSAR_MIPS32 architecture.
+ * WARNING : It is replicated in hal_kentry.S file.
  ***************************************************************************************/
 
@@ -56 +57 @@
 #define      UZ_T6           14   /* t6_14   */
 #define      UZ_T7           15   /* t7_15   */
-#define      UZ_T8           16   /* t8_24   */
-#define      UZ_T9           17   /* t9_25   */
-#define      UZ_S0           18   /* s0_16   */
-#define      UZ_S1           19   /* s1_17   */
-#define      UZ_S2           20   /* s2_18   */
-#define      UZ_S3           21   /* s3_19   */
-#define      UZ_S4           22   /* s4_20   */
-#define      UZ_S5           23   /* s5_21   */
-#define      UZ_S6           24   /* s6_22   */
-#define      UZ_S7           25   /* s7_23   */
-#define      UZ_S8           26   /* s8_30   */
-#define      UZ_GP           27   /* gp_28   */
-#define      UZ_RA           28   /* ra_31   */
-#define      UZ_EPC          29   /* c0_epc  */
-#define      UZ_CR           30   /* c0_cr   */
-#define      UZ_SP           31   /* sp_29   */
-#define      UZ_SR           32   /* c0_sr   */
-#define      UZ_LO           33
-#define      UZ_HI           34
+#define      UZ_S0           16   /* s0_16   */
+#define      UZ_S1           17   /* s1_17   */
+#define      UZ_S2           18   /* s2_18   */
+#define      UZ_S3           19   /* s3_19   */
+#define      UZ_S4           20   /* s4_20   */
+#define      UZ_S5           21   /* s5_21   */
+#define      UZ_S6           22   /* s6_22   */
+#define      UZ_S7           23   /* s7_23   */
+#define      UZ_T8           24   /* t8_24   */
+#define      UZ_T9           25   /* t9_25   */
 
-#define      UZ_REGS         35
+#define      UZ_LO           26
+#define      UZ_HI           27
+
+#define      UZ_GP           28   /* gp_28   */
+#define      UZ_SP           29   /* sp_29   */
+#define      UZ_S8           30   /* s8_30   */
+#define      UZ_RA           31   /* ra_31   */
+
+#define      UZ_PTPR         32   /* c2_ptpr */
+#define      UZ_EPC          33   /* c0_epc  */
+#define      UZ_SR           34   /* c0_sr   */
+#define      UZ_TH           35   /* c0_th   */
+#define      UZ_CR           36   /* c0_cr   */
+
+#define      UZ_REGS         37
 
 /*************************************************************************************
  * The hal_kentry_enter() function is the unique kernel entry point in case of 
  * exception, interrupt, or syscall for the TSAR_MIPS32 architecture.  
+ * It can be executed by a core in user mode (in case of exception or syscall),
+ * or by a core already in kernel mode (in case of interrupt).
  *
- * When we enter the kernel, we test the status register:
- * - If the core is in user mode, we desactivate the MMU, and we save
- *   the core context in the uzone of the calling thread descriptor.
- * - If the core is already in kernel mode (in case of interrupt), 
- *   we save the context in the kernel stack.
- * - In both cases, we increment the cores_in_kernel variable,
- *   and we call the relevant exception/interrupt/syscall handler
+ * In both cases it allocates an "uzone" space in the kernel stack to save the
+ * CPU registers values, desactivates the MMU, and calls the relevant handler 
+ * (exception/interrupt/syscall) 
  *
- * When we exit the kernel after handler execution:
- * - we restore the core context from the uzone and return to user space,
- *   calling the hal_kentry_eret()
+ * After handler execution, it restores the CPU context from the uzone and jumps 
+ * to address contained in EPC calling hal_kentry_eret()
  ************************************************************************************/
 void hal_kentry_enter();
@@ -98 +101 @@
 /*************************************************************************************
  * The hal_kentry_eret() function contains only the assembly "eret" instruction,
- * that and the EXL bit in the c0_sr register, and jump to the address 
+ * that reset the EXL bit in the c0_sr register, and jump to the address 
  * contained in the c0_epc register. 
  * ************************************************************************************/