Changeset 432


Ignore:
Timestamp:
Feb 14, 2018, 3:39:35 PM (4 years ago)
Author:
alain
Message:

bloup

Location:
trunk/hal
Files:
11 edited

Legend:

Unmodified
Added
Removed
  • trunk/hal/generic/hal_gpt.h

    r408 r432  
    214214
    215215/****************************************************************************************
    216  * This function atomically flip the COW flag and WRITABLE flag for all PTEs
     216 * This function atomically set the COW flag and reset the WRITABLE flag for all PTEs
    217217 * of a remote GPT identified by the <gpt_xp>, <vpn_base>, and <vpn_size arguments.
    218  * - it set COW and reset WRITABLE when <set_cow> argument is true and PTE is WRITABLE.
    219  * - it set WRITABLE and reset COW when <set_cow> is false and PTE is COW.
    220218 * It does nothing if the remote PTE is not MAPPED and SMALL.
    221  * It is called when a fork is executed, or when a COW must be resolved.
    222  ****************************************************************************************
    223  * @ set_cow   : [in]  set COW & reset WRITABLE if true / do the opposite if false.
     219 ****************************************************************************************
    224220 * @ gpt_xp    : [in]  extended pointer on the remote GPT.
    225221 * @ vpn_base  : [in]  first virtual page.
    226222 * @ vpn_size  : [in]  number of pages.
    227223 ***************************************************************************************/
    228 void hal_gpt_flip_cow( bool_t  set_cow,
    229                        xptr_t  gpt_xp,
    230                        vpn_t   vpn_base,
    231                        vpn_t   vpn_size );
     224void hal_gpt_set_cow( xptr_t  gpt_xp,
     225                      vpn_t   vpn_base,
     226                      vpn_t   vpn_size );
    232227
    233228/****************************************************************************************
  • trunk/hal/tsar_mips32/core/hal_context.c

    r408 r432  
    4141#define SR_USR_MODE       0x0000FF13
    4242#define SR_USR_MODE_FPU   0x2000FF13
    43 #define SR_SYS_MODE       0x0000FF00
     43#define SR_SYS_MODE       0x0000FF01
    4444
    4545/////////////////////////////////////////////////////////////////////////////////////////
     
    174174    }
    175175
    176 context_dmsg("\n[DBG] %s : thread %x in process %x\n"
    177                  " - a0   = %x\n"
    178                  " - sp   = %x\n"
    179                  " - ra   = %x\n"
    180                  " - sr   = %x\n"
    181                  " - th   = %x\n"   
    182                  " - epc  = %x\n"   
    183                  " - ptpr = %x\n"   
    184                  " - mode = %x\n", 
    185                  __FUNCTION__ , thread->trdid , thread->process->pid,
    186                  context->a0_04, context->sp_29, context->ra_31,
    187                  context->c0_sr, context->c0_th, context->c0_epc,
    188                  context->c2_ptpr, context->c2_mode );
    189176    return 0;
    190177
     
    284271           " c0_sr   = %X    c0_epc  = %X    c0_th = %X\n"
    285272           " c2_ptpr = %X    c2_mode = %X\n",
    286            ptr->trdid, ptr->process->pid, hal_time_stamp(),
     273           ptr, ptr->process->pid, (uint32_t)hal_get_cycles(),
    287274           sp_29   , ra_31,
    288275           c0_sr   , c0_epc  , c0_th,
  • trunk/hal/tsar_mips32/core/hal_exception.c

    r425 r432  
    201201    }
    202202
    203 excp_dmsg("\n[DBG] %s : core[%x,%d] / is_ins %d / %s / vaddr %x\n",
    204 __FUNCTION__ , local_cxy , this->core->lid , is_ins,
    205 hal_mmu_exception_str(excp_code) , bad_vaddr );
     203#if CONFIG_DEBUG_HAL_EXCEPTIONS
     204uint32_t cycle = (uint32_t)hal_get_cycles();
     205if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
     206printk("\n[DBG] %s : thread %x enter / is_ins %d / %s / vaddr %x / cycle %d\n",
     207__FUNCTION__, this, is_ins, hal_mmu_exception_str(excp_code), bad_vaddr, cycle );
     208#endif
    206209
    207210   // analyse exception code
     
    226229            {
    227230
    228 excp_dmsg("\n[DBG] %s : core[%x,%d] / page-fault handled for vaddr = %x\n",
    229 __FUNCTION__ , local_cxy , this->core->lid , bad_vaddr );
     231#if CONFIG_DEBUG_HAL_EXCEPTIONS
     232cycle = (uint32_t)hal_get_cycles();
     233if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
     234printk("\n[DBG] %s : thread %x exit / page-fault handled for vaddr = %x\n",
     235__FUNCTION__ , this , bad_vaddr );
     236#endif
    230237 
    231238                return EXCP_NON_FATAL;
     
    261268                {
    262269
    263 excp_dmsg("\n[DBG] %s : core[%x,%d] / copy-on-write handled for vaddr = %x\n",
    264 __FUNCTION__ , local_cxy , this->core->lid , bad_vaddr );
     270#if CONFIG_DEBUG_HAL_EXCEPTIONS
     271cycle = (uint32_t)hal_get_cycles();
     272if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
     273printk("\n[DBG] %s : thread %x exit / copy-on-write handled for vaddr = %x\n",
     274__FUNCTION__ , this , bad_vaddr );
     275#endif
    265276
    266277                    return EXCP_NON_FATAL;
     
    377388        excCode        = (uzone[UZ_CR] >> 2) & 0xF;
    378389
    379 excp_dmsg("\n[DBG] %s : core[%x,%d] / thread %x in process %x / xcode %x / cycle %d\n",
    380 __FUNCTION__, local_cxy, this->core->lid, this->trdid,
    381 this->process->pid, excCode, (uint32_t)hal_get_cycles() );
     390#if CONFIG_DEBUG_HAL_EXCEPTIONS
     391uint32_t cycle = (uint32_t)hal_get_cycles();
     392if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
     393printk("\n[DBG] %s : thread %x on core[%x,%d] enter / process %x / xcode %x / cycle %d\n",
     394__FUNCTION__, this, local_cxy, this->core->lid, this->process->pid, excCode, cycle );
     395#endif
    382396
    383397        switch(excCode)
     
    434448    }
    435449
    436 excp_dmsg("\n[DBG] %s : core[%x,%d] exit / thread %x in process %x / cycle %d\n",
    437 __FUNCTION__, local_cxy, this->core->lid, this->trdid, this->process->pid,
    438 (uint32_t)hal_get_cycles() );
     450#if CONFIG_DEBUG_HAL_EXCEPTIONS
     451cycle = (uint32_t)hal_get_cycles();
     452if( CONFIG_DEBUG_HAL_EXCEPTIONS < cycle )
     453printk("\n[DBG] %s : thread %x on core[%x,%d] exit / process %x / xcode %x / cycle %d\n",
     454__FUNCTION__, this, local_cxy, this->core->lid, this->process->pid, excCode, cycle );
     455#endif
    439456
    440457}  // end hal_do_exception()
  • trunk/hal/tsar_mips32/core/hal_gpt.c

    r420 r432  
    132132    xptr_t     page_xp;
    133133
    134 gpt_dmsg("\n[DBG] %s : core[%x,%d] enter\n",
    135 __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
     134#if CONFIG_DEBUG_GPT_ACCESS
     135uint32_t cycle = (uint32_t)hal_get_cycles;
     136if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     137printk("\n[DBG] %s : thread %x enter / cycle %d\n",
     138__FUNCTION__, CURRENT_THREAD, cycle );
     139#endif
    136140
    137141    // check page size
     
    157161        gpt->ppn  = ppm_page2ppn( page_xp );
    158162
    159 gpt_dmsg("\n[DBG] %s : core[%x,%d] exit\n",
    160 __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid );
     163#if CONFIG_DEBUG_GPT_ACCESS
     164cycle = (uint32_t)hal_get_cycles;
     165if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     166printk("\n[DBG] %s : thread %x exit / cycle %d\n",
     167__FUNCTION__, CURRENT_THREAD, cycle );
     168#endif
    161169
    162170        return 0;
     
    332340    uint32_t            tsar_attr;           // PTE attributes for TSAR MMU
    333341
    334 gpt_dmsg("\n[DBG] %s : core[%x,%d] enter for vpn = %x / ppn = %x / gpt_attr = %x\n",
    335 __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn , ppn , attr );
    336  
     342#if CONFIG_DEBUG_GPT_ACCESS
     343uint32_t cycle = (uint32_t)hal_get_cycles;
     344if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     345printk("\n[DBG] %s : thread %x enter / vpn %x / attr %x / ppn %x / cycle %d\n",
     346__FUNCTION__, CURRENT_THREAD, vpn, attr, ppn, cycle );
     347#endif
     348
    337349    // compute indexes in PT1 and PT2
    338350    ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
     
    342354        small = attr & GPT_SMALL;
    343355
    344     // compute tsar_attr from generic attributes
     356    // compute tsar attributes from generic attributes
    345357    tsar_attr = gpt2tsar( attr );
    346358
    347 gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / &pt1 = %x / tsar_attr = %x\n",
    348 __FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pt1 , tsar_attr );
     359#if (CONFIG_DEBUG_GPT_ACCESS & 1)
     360if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     361printk("\n[DBG] %s : thread %x / vpn %x / &pt1 %x / tsar_attr %x\n",
     362__FUNCTION__, CURRENT_THREAD, vpn, pt1, tsar_attr );
     363#endif
    349364
    350365    // get pointer on PT1[ix1]
     
    377392        pte1 = *pte1_ptr;
    378393       
    379 gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / current_pte1 = %x\n",
    380 __FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pte1 );
     394#if (CONFIG_DEBUG_GPT_ACCESS & 1)
     395if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     396printk("\n[DBG] %s : thread %x / vpn %x / current_pte1 %x\n",
     397__FUNCTION__, CURRENT_THREAD, vpn, pte1 );
     398#endif
    381399       
    382400        // allocate a PT2 if PT1 entry not valid
     
    419437            pt2     = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) );
    420438
    421 gpt_dmsg("\n[DBG] %s : core[%x,%d] / vpn = %x / pte1 = %x / &pt2 = %x\n",
    422 __FUNCTION__, local_cxy , CURRENT_THREAD->core->lid , vpn , pte1 , pt2 );
     439#if (CONFIG_DEBUG_GPT_ACCESS & 1)
     440if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     441printk("\n[DBG] %s : thread %x / vpn %x / pte1 %x / &pt2 %x\n",
     442__FUNCTION__, CURRENT_THREAD, vpn, pte1, pt2 );
     443#endif
    423444       
    424445    }
     
    431452        hal_fence();
    432453
    433 gpt_dmsg("\n[DBG] %s : core[%x,%d] exit / vpn = %x / pte2_attr = %x / pte2_ppn = %x\n",
    434 __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn ,
    435 pt2[2 * ix2] , pt2[2 * ix2 + 1] );
    436  
     454#if CONFIG_DEBUG_GPT_ACCESS
     455cycle = (uint32_t)hal_get_cycles;
     456if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     457printk("\n[DBG] %s : thread %x exit / vpn %x / pte2_attr %x / pte2_ppn %x / cycle %d\n",
     458__FUNCTION__, CURRENT_THREAD, vpn, pt2[2 * ix2], pt2[2 * ix2 + 1], cycle );
     459#endif
     460
    437461        return 0;
    438462
     
    738762    ppn_t        dst_pt2_ppn;
    739763
    740 gpt_dmsg("\n[DBG] %s : core[%x,%d] enter for vpn %x\n",
    741 __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn );
     764#if CONFIG_DEBUG_GPT_ACCESS
     765uint32_t cycle = (uint32_t)hal_get_cycles;
     766if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     767printk("\n[DBG] %s : thread %x enter / vpn %x / cycle %d\n",
     768__FUNCTION__, CURRENT_THREAD, vpn, cycle );
     769#endif
    742770
    743771    // get remote src_gpt cluster and local pointer
     
    825853            *ppn    = src_pte2_ppn;
    826854       
    827 gpt_dmsg("\n[DBG] %s : core[%x,%d] exit for vpn %x / copy done\n",
    828 __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn );
     855#if CONFIG_DEBUG_GPT_ACCESS
     856cycle = (uint32_t)hal_get_cycles;
     857if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     858printk("\n[DBG] %s : thread %x exit / copy done for vpn %x / cycle %d\n",
     859__FUNCTION__, CURRENT_THREAD, vpn, cycle );
     860#endif
    829861
    830862            hal_fence();
     
    837869    *mapped = false;
    838870    *ppn    = 0;
    839    
    840 gpt_dmsg("\n[DBG] %s : core[%x,%d] exit for vpn %x / nothing done\n",
    841 __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , vpn );
     871   
     872#if CONFIG_DEBUG_GPT_ACCESS
     873cycle = (uint32_t)hal_get_cycles;
     874if( CONFIG_DEBUG_GPT_ACCESS < cycle )
     875printk("\n[DBG] %s : thread %x exit / nothing done for vpn %x / cycle %d\n",
     876__FUNCTION__, CURRENT_THREAD, vpn, cycle );
     877#endif
    842878
    843879    hal_fence();
     
    918954
    919955/////////////////////////////////////////
    920 void hal_gpt_flip_cow( bool_t  set_cow,
    921                        xptr_t  gpt_xp,
    922                        vpn_t   vpn_base,
    923                        vpn_t   vpn_size )
     956void hal_gpt_set_cow( xptr_t  gpt_xp,
     957                      vpn_t   vpn_base,
     958                      vpn_t   vpn_size )
    924959{
    925960    cxy_t      gpt_cxy;
     
    936971    uint32_t * pt2;
    937972    ppn_t      pt2_ppn;
    938 
    939     uint32_t   old_attr;
    940     uint32_t   new_attr;
     973    uint32_t   attr;
    941974
    942975    // get GPT cluster and local pointer
     
    9671000 
    9681001            // get current PTE2 attributes
    969             old_attr = hal_remote_lw( XPTR( gpt_cxy , &pt2[2*ix2] ) );
     1002            attr = hal_remote_lw( XPTR( gpt_cxy , &pt2[2*ix2] ) );
    9701003
    9711004            // only MAPPED PTEs are modified       
    972             if( old_attr & TSAR_MMU_MAPPED )
     1005            if( attr & TSAR_MMU_MAPPED )
    9731006            {
    974                 if( (set_cow != 0) && (old_attr & TSAR_MMU_WRITABLE) )
    975                 {
    976                     new_attr = (old_attr | TSAR_MMU_COW) & (~TSAR_MMU_WRITABLE);
    977                     hal_remote_sw( XPTR( gpt_cxy , &pt2[2*ix2] ) , new_attr );
    978                 }
    979                 if( (set_cow == 0) && (old_attr & TSAR_MMU_COW ) )
    980                 {
    981                     new_attr = (old_attr | TSAR_MMU_WRITABLE) & (~TSAR_MMU_COW);
    982                     hal_remote_sw( XPTR( gpt_cxy , &pt2[2*ix2] ) , new_attr );
    983                 }
    984             }   // end if PTE2 mapped
    985         }   // end if PTE1 mapped
     1007                attr = (attr | TSAR_MMU_COW) & (~TSAR_MMU_WRITABLE);
     1008                hal_remote_sw( XPTR( gpt_cxy , &pt2[2*ix2] ) , attr );
     1009            }
     1010        }
    9861011    }   // end loop on pages
    9871012
    988 }  // end hal_gpt_flip_cow()
     1013}  // end hal_gpt_set_cow()
    9891014
    9901015//////////////////////////////////////////
  • trunk/hal/tsar_mips32/core/hal_interrupt.c

    r408 r432  
    3434
    3535irq_dmsg("\n[DBG] %s : core[%x,%d] enter at cycle %d\n",
    36 __FUNCTION__ , local_cxy , this->core->lid , hal_time_stamp() );
     36__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , hal_time_stamp() );
    3737
    3838    // As ALMOS-MKH does not define a generic interrupt handler,
     
    4141
    4242irq_dmsg("\n[DBG] %s : core[%x,%d] exit at cycle %d\n",
    43 __FUNCTION__ , local_cxy , this->core->lid , hal_time_stamp() );
     43__FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , hal_time_stamp() );
    4444
    4545}
  • trunk/hal/tsar_mips32/core/hal_kentry.S

    r425 r432  
    200200        mtc0    $3,         $12                         # set new c0_sr
    201201
    202 #-----------------------
    203 #if CONFIG_KENTRY_DEBUG
     202#--------------------------
     203#if CONFIG_DEBUG_HAL_KENTRY
    204204
    205205    # display "enter" message
     
    349349    sw      $5,    8($4)                # current uzone pointer <= previous
    350350
    351 #----------------------
    352 #if CONFIG_KENTRY_DEBUG
     351#--------------------------
     352#if CONFIG_DEBUG_HAL_KENTRY
    353353
    354354    # display "exit" message
  • trunk/hal/tsar_mips32/core/hal_ppm.c

    r409 r432  
    4343// This hal_ppm_init() function initializes the pages_tbl[] array used by the generic
    4444// kmem memory allocator in the local cluster. This array starts in first free page
    45 // after kernel code, as defined by the 'offset' field in boot_info.
     45// after kernel code, as defined by the 'pages_offset' field in boot_info.
    4646//////////////////////////////////////////////////////////////////////////////////////////
    4747
     
    101101        }
    102102
     103// printk("\n@@@ in %s : reserved = %d / total = %d\n", __FUNCTION__, reserved_pages, pages_nr );
     104
    103105        // - set PG_RESERVED flag for reserved pages (kernel code & pages_tbl[])
    104106        // - release all other pages to populate the free lists
     
    112114
    113115                // TODO optimisation : decompose this enormous set of small pages
    114                 // to several sets of big pages with various order values
     116                // to several sets of big pages with various order values [AG]
     117
     118// if( (i < (reserved_pages+10)) || (i > (pages_nr-5)) ) ppm_print();
     119
    115120        }
    116121
     122// assert( false , __FUNCTION__ , "PMM init completed\n");
     123 
    117124        // check consistency
    118125        return ppm_assert_order( ppm );
  • trunk/hal/tsar_mips32/drivers/soclib_nic.c

    r279 r432  
    4949
    5050    // initialize Soclib NIC global registers
    51     hal_remote_sw( XPTR( nic_cxy , &nic_ptr + NIC_G_BC_ENABLE ) , 0 );
    52     hal_remote_sw( XPTR( nic_cxy , &nic_ptr + NIC_G_RUN       ) , 0 );
     51    hal_remote_sw( XPTR( nic_cxy , nic_ptr + NIC_GLOBAL_SPAN + NIC_G_BC_ENABLE ) , 0 );
     52    hal_remote_sw( XPTR( nic_cxy , nic_ptr + NIC_GLOBAL_SPAN + NIC_G_RUN       ) , 0 );
    5353
    5454    // allocate memory for chbuf descriptor (one page)
  • trunk/hal/tsar_mips32/drivers/soclib_pic.c

    r424 r432  
    9696
    9797    // read PRIO register
    98         uint32_t prio = base[(XCU_PRIO << 5) | lid];
     98    // in TSAR : XCU output [4*lid] is connected to core [lid]
     99        uint32_t prio = base[ (XCU_PRIO << 5) | (lid<<2) ];
    99100
    100101    *wti_status = (prio & 0x4) ? (((prio >> 24) & 0x1F) + 1) : 0;
     
    129130                           &pti_status );
    130131
    131     irq_dmsg("\n[DBG] %s : core[%x,%d] enter / WTI = %x / HWI = %x / WTI = %x\n",
     132    irq_dmsg("\n[DBG] %s : core[%x,%d] enter / WTI = %x / HWI = %x / PTI = %x\n",
    132133             __FUNCTION__ , local_cxy , core->lid , wti_status , hwi_status , pti_status );
    133134
     
    447448    {
    448449        // enable this HWI in remote XCU controller
     450        // in TSAR : XCU output [4*lid] is connected to core [lid]
    449451        hal_remote_sw( XPTR( src_chdev_cxy ,
    450                        &seg_xcu_ptr[(XCU_MSK_HWI_ENABLE << 5) | lid] ) , (1 << irq_id) );
     452                       &seg_xcu_ptr[ (XCU_MSK_HWI_ENABLE << 5) | (lid<<4) ] ) , (1 << irq_id) );
    451453    }
    452454    else if( irq_type == SOCLIB_TYPE_WTI )
    453455    {
    454456        // enable this WTI in remote XCU controller
     457        // in TSAR : XCU output [4*lid] is connected to core [lid]
    455458        hal_remote_sw( XPTR( src_chdev_cxy ,
    456                        &seg_xcu_ptr[(XCU_MSK_WTI_ENABLE << 5) | lid] ) , (1 << irq_id) );
     459                       &seg_xcu_ptr[ (XCU_MSK_WTI_ENABLE << 5) | (lid<<4) ] ) , (1 << irq_id) );
    457460    }
    458461    else
     
    479482    if( irq_type == SOCLIB_TYPE_HWI )
    480483    {
    481         // enable this HWI in remote XCU controller
     484        // enable this HWI in remote XCU controller
     485        // in TSAR : XCU output [4*lid] is connected to core [lid]
    482486        hal_remote_sw( XPTR( src_chdev_cxy ,
    483                        &seg_xcu_ptr[(XCU_MSK_HWI_DISABLE << 5) | lid] ) , (1 << irq_id) );
     487                       &seg_xcu_ptr[(XCU_MSK_HWI_DISABLE << 5) | (lid<<2) ] ) , (1 << irq_id) );
    484488    }
    485489    else if( irq_type == SOCLIB_TYPE_WTI )
    486490    {
    487491        // enable this WTI in remote XCU controller
     492        // in TSAR : XCU output [4*lid] is connected to core [lid]
    488493        hal_remote_sw( XPTR( src_chdev_cxy ,
    489                        &seg_xcu_ptr[(XCU_MSK_WTI_DISABLE << 5) | lid] ) , (1 << irq_id) );
     494                       &seg_xcu_ptr[(XCU_MSK_WTI_DISABLE << 5) | (lid<<4) ] ) , (1 << irq_id) );
    490495    }
    491496    else
     
    509514
    510515    // enable PTI in local XCU controller
    511     base[(XCU_MSK_PTI_ENABLE << 5) | lid] = 1 << lid;
     516    // In TSAR : XCU output [4*lid] is connected to core [lid]
     517    base[ (XCU_MSK_PTI_ENABLE << 5) | (lid<<2) ] = 1 << lid;
    512518}
    513519
     
    522528
    523529    // enable WTI in local XCU controller
    524     base[(XCU_MSK_WTI_ENABLE << 5) | lid] = 1 << lid;
     530    // In TSAR : XCU output [4*lid] is connected to core [lid]
     531    base[ (XCU_MSK_WTI_ENABLE << 5) | (lid<<2) ] = 1 << lid;
    525532}
    526533
     
    533540
    534541    // write to WTI mailbox[cxy][lid]
    535     hal_remote_sw( XPTR( cxy , &base[(XCU_WTI_REG << 5) | lid] ) , 0 );
     542    hal_remote_sw( XPTR( cxy , &base[(XCU_WTI_REG << 5) | lid ] ) , 0 );
    536543}
    537544
     
    546553
    547554    // acknowlege IPI
    548     uint32_t   ack  = base[(XCU_WTI_REG << 5) | lid];
     555    uint32_t   ack  = base[ (XCU_WTI_REG << 5) | lid ];
    549556
    550557    // we must make a fake use for ack value to avoid a warning
  • trunk/hal/tsar_mips32/drivers/soclib_pic.h

    r407 r432  
    137137typedef struct soclib_pic_core_s
    138138{
    139     struct chdev_s * hwi_vector[SOCLIB_MAX_HWI];
    140     struct chdev_s * wti_vector[SOCLIB_MAX_WTI];
     139    struct chdev_s * hwi_vector[SOCLIB_MAX_HWI];    /* HWI interrupt vector             */
     140    struct chdev_s * wti_vector[SOCLIB_MAX_WTI];    /* WTI interrupt vector             */
    141141}
    142142soclib_pic_core_t;
  • trunk/hal/tsar_mips32/drivers/soclib_tty.c

    r424 r432  
    7272#endif
    7373
    74 txt_dmsg("\n[DBG] %s : core[%x,%d] / DEV thread enter / cycle %d\n",
    75 __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , hal_time_stamp() );
     74#if CONFIG_DEBUG_HAL_TXT
     75uint32_t cycle = (uint32_t)hal_get_cycles();
     76if (CONFIG_DEBUG_HAL_TXT < cycle )
     77printk("\n[DBG] %s : thread %x enter / cycle %d\n",
     78__FUNCTION__ , CURRENT_THREAD , cycle );
     79#endif
    7680
    7781    // get client thread cluster and local pointer
     
    108112    hal_remote_sw( reg_xp , 1 );
    109113
    110 txt_dmsg("\n[DBG] %s : core[%x,%d] DEV thread deschedule / cycle %d\n",
    111 __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , hal_time_stamp() );
     114#if CONFIG_DEBUG_HAL_TXT
     115cycle = (uint32_t)hal_get_cycles();
     116if (CONFIG_DEBUG_HAL_TXT < cycle )
     117printk("\n[DBG] %s : thread %x deschedule / cycle %d\n",
     118__FUNCTION__ , CURRENT_THREAD , cycle );
     119#endif
    112120
    113121    // Block and deschedule server thread
     
    115123    sched_yield("blocked on ISR");
    116124
    117 txt_dmsg("\n[DBG] %s : core[%x,%d] / DEV thread resume / cycle %d\n",
    118 __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , hal_time_stamp() );
     125#if CONFIG_DEBUG_HAL_TXT
     126cycle = (uint32_t)hal_get_cycles();
     127if (CONFIG_DEBUG_HAL_TXT < cycle )
     128printk("\n[DBG] %s : thread %x resume / cycle %d\n",
     129__FUNCTION__ , CURRENT_THREAD , cycle );
     130#endif
    119131
    120132#if CONFIG_READ_DEBUG
     
    184196#endif
    185197
     198#if CONFIG_DEBUG_HAL_TXT
     199uint32_t cycle = (uint32_t)hal_get_cycles();
     200if (CONFIG_DEBUG_HAL_TXT < cycle)
     201printk("\n[DBG] %s : enter / cycle %d\n", __FUNCTION__ , cycle );
     202#endif
     203
    186204    // get extended pointer on client thread
    187205    xptr_t root      = XPTR( local_cxy , &chdev->wait_root );
     
    197215    buf_xp  = hal_remote_lwd( XPTR( client_cxy , &client_ptr->txt_cmd.buf_xp ) );
    198216
    199 txt_dmsg("\n[DBG] %s : core[%x,%d] enter / cycle %d\n",
    200 __FUNCTION__ , local_cxy, CURRENT_THREAD->core->lid , hal_time_stamp() );
    201 
    202217    // get SOCLIB_TTY peripheral cluster and local pointer
    203218    cxy_t      tty_cxy = GET_CXY( chdev->base );
     
    234249        hal_remote_sw( reg_xp , 0 );
    235250    }
    236     else if( type == TXT_WRITE )         // write all characters in string
     251    else   // type == TXT_WRITE           // write all characters in string
    237252    {
    238253        // loop on characters
     
    276291    hal_fence();
    277292
    278 txt_dmsg("\n[DBG] %s : core[%x,%d] exit / cycle %d\n",
    279 __FUNCTION__ , local_cxy , CURRENT_THREAD->core->lid , hal_time_stamp() );
     293#if CONFIG_DEBUG_HAL_TXT
     294cycle = (uint32_t)hal_get_cycles();
     295if (CONFIG_DEBUG_HAL_TXT < cycle)
     296{
     297    if( type == TXT_READ)
     298        printk("\n[DBG] %s : exit after RX / cycle %d\n", __FUNCTION__ , cycle );
     299    else
     300        printk("\n[DBG] %s : exit after TX / cycle %d\n", __FUNCTION__ , cycle );
     301}     
     302#endif
    280303
    281304#if (CONFIG_READ_DEBUG & 0x1) || (CONFIG_WRITE_DEBUG & 0x1)
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