Changeset 451


Ignore:
Timestamp:
Jul 5, 2018, 3:45:43 PM (3 years ago)
Author:
alain
Message:

Fix a bug in soclib_pic driver (bad separation between IOPIC an LAPIC initialisation)

Location:
trunk/hal/tsar_mips32/drivers
Files:
13 edited

Legend:

Unmodified
Added
Removed
  • trunk/hal/tsar_mips32/drivers/soclib_bdv.c

    r440 r451  
    2222 */
    2323
     24#include <soclib_bdv.h>
     25#include <hal_kernel_types.h>
    2426#include <chdev.h>
    2527#include <dev_ioc.h>
    26 #include <soclib_bdv.h>
    2728#include <printk.h>
    2829#include <thread.h>
    2930#include <spinlock.h>
    30 
    3131
    3232///////////////////////////////////////
  • trunk/hal/tsar_mips32/drivers/soclib_bdv.h

    r437 r451  
    2626
    2727#include <chdev.h>
    28 #include <hal_types.h>
     28#include <hal_kernel_types.h>
    2929
    3030/********************************************************************************************
  • trunk/hal/tsar_mips32/drivers/soclib_dma.c

    r436 r451  
    2222 */
    2323
    24 #include <hal_types.h>
     24#include <hal_kernel_types.h>
    2525#include <chdev.h>
    2626#include <dev_dma.h>
  • trunk/hal/tsar_mips32/drivers/soclib_hba.h

    r437 r451  
    2626
    2727#include <chdev.h>
    28 #include <hal_types.h>
     28#include <hal_kernel_types.h>
    2929
    3030/*****************************************************************************************
  • trunk/hal/tsar_mips32/drivers/soclib_iob.c

    r75 r451  
    2323
    2424#include <kernel_config.h>
    25 #include <hal_types.h>
     25#include <hal_kernel_types.h>
    2626#include <hal_remote.h>
    2727#include <soclib_iob.h>
  • trunk/hal/tsar_mips32/drivers/soclib_iob.h

    r75 r451  
    2525#define _SOCLIB_IOB_H_
    2626
    27 #include <hal_types.h>
     27#include <hal_kernel_types.h>
    2828#include <chdev.h>
    2929
  • trunk/hal/tsar_mips32/drivers/soclib_mmc.c

    r440 r451  
    2323
    2424
    25 #include <hal_types.h>
     25#include <hal_kernel_types.h>
    2626#include <chdev.h>
    2727#include <dev_mmc.h>
  • trunk/hal/tsar_mips32/drivers/soclib_mmc.h

    r75 r451  
    2727#include <chdev.h>
    2828#include <dev_mmc.h>
    29 #include <hal_types.h>
     29#include <hal_kernel_types.h>
    3030
    3131/********************************************************************************************
  • trunk/hal/tsar_mips32/drivers/soclib_nic.c

    r432 r451  
    2222 */
    2323
    24 #include <hal_types.h>
     24#include <hal_kernel_types.h>
    2525#include <hal_remote.h>
    2626#include <hal_special.h>
  • trunk/hal/tsar_mips32/drivers/soclib_nic.h

    r75 r451  
    2626
    2727#include <chdev.h>
    28 #include <hal_types.h>
     28#include <hal_kernel_types.h>
    2929
    3030/********************************************************************************************
  • trunk/hal/tsar_mips32/drivers/soclib_pic.c

    r440 r451  
    2222 */
    2323
    24 #include <hal_types.h>
     24#include <hal_kernel_types.h>
    2525#include <chdev.h>
    2626#include <soclib_pic.h>
     
    255255{
    256256    uint32_t    i;      // for loop on IOPIC inputs
    257     uint32_t    x;      // for loop on clusters in a row
    258     uint32_t    y;      // for loop on clusters in a column inputs
    259     uint32_t    lid;    // for loop on cores in a cluster
    260 
    261     // get target architecture parameters
    262     cluster_t * cluster = LOCAL_CLUSTER;
    263     uint32_t    x_size  = cluster->x_size;
    264     uint32_t    y_size  = cluster->y_size;
    265     uint32_t    y_width = cluster->y_width;
    266     uint32_t    ncores  = cluster->cores_nr;
    267257
    268258    // get IOPIC controller cluster and segment base pointer
    269     cxy_t      iopic_seg_cxy = (cxy_t)GET_CXY( pic->base );
    270     uint32_t * iopic_seg_ptr = (uint32_t *)GET_PTR( pic->base );
     259    cxy_t      iopic_seg_cxy = GET_CXY( pic->base );
     260    uint32_t * iopic_seg_ptr = GET_PTR( pic->base );
    271261
    272262    // reset the IOPIC component registers : disable all input IRQs
     
    277267        hal_remote_sw( iopic_seg_xp , 0 );
    278268    }
    279    
    280     // GET XCU controller segment base
    281     uint32_t * base = soclib_pic_xcu_base();
    282 
    283     // reset the XCU component registers in all clusters:
    284     // mask all HWIs, all WTIs, and all PTIs, for all cores   
    285     for( x = 0 ; x < x_size ; x++ )
    286     {
    287         for( y = 0 ; y < y_size ; y++ )
    288         {
    289             for( lid = 0 ; lid < ncores ; lid++ )
    290             {
    291                 cxy_t cxy = (x<<y_width) + y;
    292                 xptr_t hwi_mask_xp = XPTR( cxy , base + (XCU_MSK_HWI_DISABLE << 5 | lid) );
    293                 xptr_t wti_mask_xp = XPTR( cxy , base + (XCU_MSK_WTI_DISABLE << 5 | lid) );
    294                 xptr_t pti_mask_xp = XPTR( cxy , base + (XCU_MSK_PTI_DISABLE << 5 | lid) );
    295                 hal_remote_sw( hwi_mask_xp , 0xFFFFFFFF );
    296                 hal_remote_sw( wti_mask_xp , 0xFFFFFFFF );
    297                 hal_remote_sw( pti_mask_xp , 0xFFFFFFFF );
    298             }
    299         }
    300     }
     269
    301270}  // end soclib_pic_init()
    302271
     
    357326    // register PIC extension in cluster manager
    358327    cluster->pic_extend = cluster_ext_ptr;
     328
     329    // reset the XCU component registers
     330    // mask all HWIs, all WTIs, and all PTIs, for all cores in local cluster   
     331    for( lid = 0 ; lid < cluster->cores_nr ; lid++ )
     332    {
     333        xcu_base[XCU_MSK_HWI_DISABLE << 5 | lid] = 0xFFFFFFFF;
     334        xcu_base[XCU_MSK_WTI_DISABLE << 5 | lid] = 0xFFFFFFFF;
     335        xcu_base[XCU_MSK_PTI_DISABLE << 5 | lid] = 0xFFFFFFFF;
     336    }
    359337
    360338}  // end soclib_pic_extend_init()
  • trunk/hal/tsar_mips32/drivers/soclib_pic.h

    r432 r451  
    2525#define _SOCLIB_PIC_H_
    2626
    27 #include <hal_types.h>
     27#include <hal_kernel_types.h>
    2828
    2929/****  Forward declarations  ****/
     
    167167
    168168/******************************************************************************************
    169  * This blocking function disables all input IRQs in the IOPIC controller, and
    170  * disables all HWIs, WTIs, and PTIs in the XCU (LAPIC) controllers, for all cores,
    171  * in all clusters.
     169 * This function disables all input IRQs in the external IOPIC controller.
    172170 * It must be called by a thread running in the cluster containing the PIC chdev.
    173171******************************************************************************************
     
    177175
    178176/*****************************************************************************************
    179  * This function allocates memory from local cluster for the SOCLIB PIC core extensions
     177 * This function allocates memory from local cluster for the local PIC core extensions
    180178 * of all cores contained in the cluster, initializes the two HWI, WTI interrupt vectors
    181179 * as empty, and registers - for each core - the pointer in core descriptor.
    182  * Then it allocates memory from local cluster for the SOCLIB PIC cluster extension,
    183  * to implement the XCU WTI allocator, and registers the pointer in cluster manager.
    184  * It access the local XCU component to get actual number of HWI / WTI / PTI.
     180 * Then it allocates memory from local cluster for the PIC cluster extension,
     181 * and registers the pointer in cluster manager.
     182 * It accesses the local XCU component to get actual number of HWI / WTI / PTI.
     183 * Finally, it disables all HWI/WTI/PTI interrupts for all cores by writing in the
     184 * relevant mask registers of the local XCU component.
    185185 *****************************************************************************************
    186186 * @ xcu_base  : local pointer on XCU controller segment base.
  • trunk/hal/tsar_mips32/drivers/soclib_tty.c

    r446 r451  
    22 * soclib_tty.c - soclib tty driver implementation.
    33 *
    4  * Author  Alain Greiner (2016)
     4 * Author  Alain Greiner (2016,2017,2018)
    55 *
    66 * Copyright (c)  UPMC Sorbonne Universites
     
    2222 */
    2323
     24
     25#include <hal_kernel_types.h>
    2426#include <dev_txt.h>
    2527#include <chdev.h>
     
    123125#endif
    124126
    125 #if DEBUG_HAL_TXT_RX
    126 uint32_t rx_cycle = (uint32_t)hal_get_cycles();
    127 if( (DEBUG_HAL_TXT_RX < rx_cycle) && (type == TXT_READ) )
    128 printk("\n[DBG] %s : thread %x enter for RX / cycle %d\n",
    129 __FUNCTION__ , CURRENT_THREAD , rx_cycle );
    130 #endif
    131 
    132 #if DEBUG_HAL_TXT_TX
    133 uint32_t tx_cycle = (uint32_t)hal_get_cycles();
    134 if( (DEBUG_HAL_TXT_TX < tx_cycle) && (type == TXT_WRITE) )
    135 printk("\n[DBG] %s : thread %x enter for TX / cycle %d\n",
    136 __FUNCTION__ , CURRENT_THREAD , tx_cycle );
    137 #endif
    138 
    139127    // get TXT device cluster and pointers
    140128    xptr_t     dev_xp = (xptr_t)hal_remote_lwd( XPTR( th_cxy , &th_ptr->txt_cmd.dev_xp ) );
     
    165153                byte = hal_remote_lb( buf_xp + done );
    166154
     155#if DEBUG_HAL_TXT_TX
     156uint32_t tx_cycle = (uint32_t)hal_get_cycles();
     157if( DEBUG_HAL_TXT_TX < tx_cycle )
     158printk("\n[DBG] %s : thread %x put character <%c> to TXT%d_TX fifo / cycle %d\n",
     159__FUNCTION__, CURRENT_THREAD, byte, channel, tx_cycle );
     160#endif
    167161                // write byte to FIFO
    168162                fifo->data[fifo->ptw] = byte;
     
    208202                char byte = fifo->data[fifo->ptr];
    209203
     204#if DEBUG_HAL_TXT_RX
     205uint32_t rx_cycle = (uint32_t)hal_get_cycles();
     206if( DEBUG_HAL_TXT_RX < rx_cycle )
     207printk("\n[DBG] %s : thread %x get character <%c> from TXT%d_RX fifo / cycle %d\n",
     208__FUNCTION__, CURRENT_THREAD, byte, channel, rx_cycle );
     209#endif
    210210                // update FIFO state
    211211                fifo->ptr = (fifo->ptr + 1) % TTY_FIFO_DEPTH;
     
    235235        assert( false , __FUNCTION__ , "illegal TXT command\n" );
    236236    }
    237 
    238 #if DEBUG_HAL_TXT_RX
    239 rx_cycle = (uint32_t)hal_get_cycles();
    240 if( (DEBUG_HAL_TXT_RX < rx_cycle) && (type == TXT_READ) )
    241 printk("\n[DBG] %s : thread %x exit after RX / cycle %d\n",
    242 __FUNCTION__ , CURRENT_THREAD , rx_cycle );
    243 #endif
    244 
    245 #if DEBUG_HAL_TXT_TX
    246 tx_cycle = (uint32_t)hal_get_cycles();
    247 if( (DEBUG_HAL_TXT_TX < tx_cycle) && (type == TXT_WRITE) )
    248 printk("\n[DBG] %s : thread %x exit after TX / cycle %d\n",
    249 __FUNCTION__ , CURRENT_THREAD , tx_cycle );
    250 #endif
    251237
    252238#if (DEBUG_SYS_READ & 1)
     
    453439#if DEBUG_HAL_TXT_RX
    454440if( DEBUG_HAL_TXT_RX < rx_cycle )
    455 printk("\n[DBG] %s : read character %c from TXT%d\n", __FUNCTION__, byte, channel );
     441printk("\n[DBG] %s : put character <%c> to TXT%d_RX fifo\n",
     442__FUNCTION__, byte, channel );
    456443#endif
    457444                // store byte into FIFO
     
    496483#if DEBUG_HAL_TXT_TX
    497484if( DEBUG_HAL_TXT_TX < tx_cycle )
    498 printk("\n[DBG] %s : write character %c to TXT%d\n", __FUNCTION__, byte, channel );
     485printk("\n[DBG] %s : get character <%c> from TXT%d_TX fifo\n",
     486__FUNCTION__, byte, channel );
    499487#endif
    500488                // update TX_FIFO state
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