Index: trunk/hal/tsar_mips32/core/hal_gpt.c
===================================================================
--- trunk/hal/tsar_mips32/core/hal_gpt.c	(revision 570)
+++ trunk/hal/tsar_mips32/core/hal_gpt.c	(revision 587)
@@ -132,9 +132,11 @@
     xptr_t     page_xp;
 
+    thread_t * this = CURRENT_THREAD;
+
 #if DEBUG_HAL_GPT_CREATE
-uint32_t cycle = (uint32_t)hal_get_cycles;
+uint32_t cycle = (uint32_t)hal_get_cycles();
 if( DEBUG_HAL_GPT_CREATE < cycle )
-printk("\n[DBG] %s : thread %x enter / cycle %d\n", 
-__FUNCTION__, CURRENT_THREAD, cycle );
+printk("\n[DBG] %s : thread[%x,%x] enter / cycle %d\n", 
+__FUNCTION__, this->process->pid, this->trdid, cycle );
 #endif
 
@@ -152,5 +154,6 @@
 	if( page == NULL ) 
     {
-        printk("\n[ERROR] in %s : cannot allocate memory for PT1\n", __FUNCTION__ );
+        printk("\n[PANIC] in %s : no memory for PT1 / process %x / cluster %x\n",
+        __FUNCTION__, this->process->pid, local_cxy );
         return ENOMEM;
     }
@@ -162,8 +165,8 @@
 
 #if DEBUG_HAL_GPT_CREATE
-cycle = (uint32_t)hal_get_cycles;
+cycle = (uint32_t)hal_get_cycles();
 if( DEBUG_HAL_GPT_CREATE < cycle )
-printk("\n[DBG] %s : thread %x exit / cycle %d\n", 
-__FUNCTION__, CURRENT_THREAD, cycle );
+printk("\n[DBG] %s : thread[%x,%x] exit / cycle %d\n", 
+__FUNCTION__, this->process->pid, this->trdid, cycle );
 #endif
 
@@ -188,8 +191,9 @@
 
 #if DEBUG_HAL_GPT_DESTROY
-uint32_t cycle = (uint32_t)hal_get_cycles;
+uint32_t   cycle = (uint32_t)hal_get_cycles();
+thread_t * this  = CURRENT_THREAD;
 if( DEBUG_HAL_GPT_DESTROY < cycle )
-printk("\n[DBG] %s : thread %x enter / cycle %d\n", 
-__FUNCTION__, CURRENT_THREAD, cycle );
+printk("\n[DBG] %s : thread[%x,%x] enter / cycle %d\n", 
+__FUNCTION__, this->process->pid, this->trdid, cycle );
 #endif
 
@@ -230,5 +234,5 @@
                 pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
                 xptr_t base_xp = ppm_ppn2base( pt2_ppn );
-                pt2 = (uint32_t *)GET_PTR( base_xp );
+                pt2     = GET_PTR( base_xp );
 
                 // scan the PT2 to release all entries VALID and USER if reference cluster
@@ -261,8 +265,8 @@
 
 #if DEBUG_HAL_GPT_DESTROY
-cycle = (uint32_t)hal_get_cycles;
+cycle = (uint32_t)hal_get_cycles();
 if( DEBUG_HAL_GPT_DESTROY < cycle )
-printk("\n[DBG] %s : thread %x exit / cycle %d\n", 
-__FUNCTION__, CURRENT_THREAD, cycle );
+printk("\n[DBG] %s : thread[%x,%x] exit / cycle %d\n", 
+__FUNCTION__, this->process->pid, this->trdid, cycle );
 #endif
 
@@ -309,5 +313,5 @@
                 pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
                 xptr_t base_xp = ppm_ppn2base ( pt2_ppn );
-                pt2 = (uint32_t *)GET_PTR( base_xp );
+                pt2     = GET_PTR( base_xp );
 
                 // scan the PT2
@@ -330,19 +334,20 @@
 
 
-///////////////////////////////////////
-error_t hal_gpt_set_pte( gpt_t   * gpt,
+//////////////////////////////////////////
+error_t hal_gpt_set_pte( xptr_t    gpt_xp,
                          vpn_t     vpn,
-                         uint32_t  attr,     // generic GPT attributes
+                         uint32_t  attr,     // GPT attributes
                          ppn_t     ppn )
 {
-    uint32_t          * pt1;                 // PT1 base addres
-	uint32_t          * pte1_ptr;            // pointer on PT1 entry
-	uint32_t            pte1;                // PT1 entry value
+    cxy_t               gpt_cxy;             // target GPT cluster
+    gpt_t             * gpt_ptr;             // target GPT local pointer
+    uint32_t          * pt1_ptr;             // local pointer on PT1
+	xptr_t              pte1_xp;             // extended pointer on PT1 entry
+	uint32_t            pte1;                // PT1 entry value if PTE1
 
 	ppn_t               pt2_ppn;             // PPN of PT2
-	uint32_t          * pt2;                 // PT2 base address
+	uint32_t          * pt2_ptr;             // PT2 base address
 
 	uint32_t            small;               // requested PTE is for a small page
-    bool_t              success;             // exit condition for while loop below
 
 	page_t            * page;                // pointer on new physical page descriptor
@@ -354,9 +359,15 @@
     uint32_t            tsar_attr;           // PTE attributes for TSAR MMU
 
-#if DEBUG_HAL_GPT_ACCESS
-uint32_t cycle = (uint32_t)hal_get_cycles;
-if( DEBUG_HAL_GPT_ACCESS < cycle )
-printk("\n[DBG] %s : thread %x enter / vpn %x / attr %x / ppn %x / cycle %d\n", 
-__FUNCTION__, CURRENT_THREAD, vpn, attr, ppn, cycle );
+    thread_t * this = CURRENT_THREAD;
+
+    // get cluster and local pointer on GPT
+    gpt_cxy = GET_CXY( gpt_xp );
+    gpt_ptr = GET_PTR( gpt_xp );
+
+#if DEBUG_HAL_GPT_SET_PTE
+uint32_t cycle = (uint32_t)hal_get_cycles();
+if( DEBUG_HAL_GPT_SET_PTE < cycle )
+printk("\n[DBG] %s : thread[%x,%x] enter / vpn %x / attr %x / ppn %x / cluster %x / cycle %d\n", 
+__FUNCTION__, this->process->pid, this->trdid, vpn, attr, ppn, gpt_cxy, cycle );
 #endif
 
@@ -365,119 +376,108 @@
     ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
 
-    pt1   = gpt->ptr;
-	small = attr & GPT_SMALL;
+    pt1_ptr = hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) );
+	small   = attr & GPT_SMALL;
 
     // compute tsar attributes from generic attributes
     tsar_attr = gpt2tsar( attr );
 
-#if (DEBUG_HAL_GPT_ACCESS & 1)
-if( DEBUG_HAL_GPT_ACCESS < cycle )
-printk("\n[DBG] %s : thread %x / vpn %x / &pt1 %x / tsar_attr %x\n", 
-__FUNCTION__, CURRENT_THREAD, vpn, pt1, tsar_attr );
-#endif
-
-    // get pointer on PT1[ix1]
-	pte1_ptr  = &pt1[ix1];
-
-    // PTE1 (big page) are only set for the kernel vsegs, in the kernel init phase.
-    // There is no risk of concurrent access.
-	if( small == 0 ) 
-    {
-        // get current pte1 value
-        pte1 = *pte1_ptr;
-
+    // build extended pointer on PTE1 = PT1[ix1]
+	pte1_xp = XPTR( gpt_cxy , &pt1_ptr[ix1] );
+
+    // get current pte1 value
+    pte1 = hal_remote_l32( pte1_xp );
+
+	if( small == 0 )     // map a big page in PT1 
+    {
         assert( (pte1 == 0) ,
 		"try to set a big page in a mapped PT1 entry / PT1[%d] = %x\n", ix1 , pte1 );
       
-        // set the PTE1 
-		*pte1_ptr = (tsar_attr  & TSAR_MMU_PTE1_ATTR_MASK) | 
-                    ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK);
+        // set the PTE1 value in PT1
+        pte1 = (tsar_attr  & TSAR_MMU_PTE1_ATTR_MASK) | ((ppn >> 9) & TSAR_MMU_PTE1_PPN_MASK);
+        hal_remote_s32( pte1_xp , pte1 );
 		hal_fence();
+
+#if DEBUG_HAL_GPT_SET_PTE
+if( DEBUG_HAL_GPT_SET_PTE < cycle )
+printk("\n[DBG] %s : thread[%x,%x] map PTE1 / cxy %x / ix1 %x / pt1 %x / pte1 %x\n", 
+__FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, pte1 );
+#endif
+
 		return 0;
 	}
-
-    // From this point, the requested PTE is a PTE2 (small page)
-
-    // loop to access PTE1 and get pointer on PT2
-    success = false;
-    do
-    {
-        // get current pte1 value
-        pte1 = *pte1_ptr;
-        
-#if (DEBUG_HAL_GPT_ACCESS & 1)
-if( DEBUG_HAL_GPT_ACCESS < cycle )
-printk("\n[DBG] %s : thread %x / vpn %x / current_pte1 %x\n", 
-__FUNCTION__, CURRENT_THREAD, vpn, pte1 );
-#endif
-        
-        // allocate a PT2 if PT1 entry not valid
-        if( (pte1 & TSAR_MMU_MAPPED) == 0 )             // PT1 entry not valid
-   	    {
-            // allocate one physical page for the PT2
-	        kmem_req_t req;
-	        req.type  = KMEM_PAGE;
-	        req.size  = 0;                       // 1 small page 
-	        req.flags = AF_KERNEL | AF_ZERO;
-            page = (page_t *)kmem_alloc( &req );
+    else                 // map a small page in PT1 & PT2
+    {
+        if( (pte1 & TSAR_MMU_MAPPED) == 0 )    // PT1 entry unmapped => map it
+        {
+            // allocate one physical page for PT2
+            if( gpt_cxy == local_cxy )
+            {
+	            kmem_req_t req;
+	            req.type  = KMEM_PAGE;
+	            req.size  = 0;                     // 1 small page 
+	            req.flags = AF_KERNEL | AF_ZERO;
+	            page = (page_t *)kmem_alloc( &req );
+            }
+            else
+            {
+                rpc_pmem_get_pages_client( gpt_cxy , 0 , &page );
+            }
+
             if( page == NULL )
             {
-		        printk("\n[ERROR] in %s : cannot allocate PT2\n", __FUNCTION__ );
+                printk("\n[PANIC] in %s : no memory for GPT PT2 / process %x / cluster %x\n",
+                __FUNCTION__, this->process->pid, gpt_cxy );
                 return ENOMEM;
             }
 
             // get the PT2 PPN
-            page_xp = XPTR( local_cxy , page );        
+            page_xp = XPTR( gpt_cxy , page );        
             pt2_ppn = ppm_page2ppn( page_xp );
 
-            // try to atomicaly set the PT1 entry 
+            // build PTD1 value
             pte1 = TSAR_MMU_MAPPED | TSAR_MMU_SMALL | pt2_ppn;
-		    success = hal_atomic_cas( pte1_ptr , 0 , pte1 );
-
-            // release allocated PT2 if PT1 entry modified by another thread
-            if( success == false ) ppm_free_pages( page );
+
+            // set the PTD1 value in PT1
+            hal_remote_s32( pte1_xp , pte1 );
+
+#if DEBUG_HAL_GPT_SET_PTE
+if( DEBUG_HAL_GPT_SET_PTE < cycle )
+printk("\n[DBG] %s : thread[%x,%x] map PTD1 / cxy %x / ix1 %d / pt1 %x / ptd1 %x\n", 
+__FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, pte1 );
+#endif
         }
-        else                                           // PT1 entry is valid
+        else                                   // pt1 entry mapped => use it
         {
-            // This valid entry must be a PTD1
-            assert( (pte1 & TSAR_MMU_SMALL) ,
-            "try to set a small page in a big PT1 entry / PT1[%d] = %x\n", ix1 , pte1 );
-
-            success = true;
+
+#if DEBUG_HAL_GPT_SET_PTE
+if( DEBUG_HAL_GPT_SET_PTE < cycle )
+printk("\n[DBG] %s : thread[%x,%x] get PTD1 / cxy %x / ix1 %d / pt1 %x / ptd1 %x\n", 
+__FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix1, pt1_ptr, pte1 );
+#endif
+
         }
 
         // get PT2 base from pte1 
 	    pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
-	    pt2     = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) );
-
-#if (DEBUG_HAL_GPT_ACCESS & 1)
-if( DEBUG_HAL_GPT_ACCESS < cycle )
-printk("\n[DBG] %s : thread %x / vpn %x / pte1 %x / &pt2 %x\n", 
-__FUNCTION__, CURRENT_THREAD, vpn, pte1, pt2 );
-#endif
-        
+	    pt2_ptr = GET_PTR( ppm_ppn2base( pt2_ppn ) );
+
+        // set PTE2 in PT2 (in this order)
+	    hal_remote_s32( XPTR( gpt_cxy , &pt2_ptr[2 * ix2 + 1] ) , ppn );
+	    hal_fence();
+	    hal_remote_s32( XPTR( gpt_cxy , &pt2_ptr[2 * ix2] ) , tsar_attr );
+	    hal_fence();
+
+#if DEBUG_HAL_GPT_SET_PTE
+if( DEBUG_HAL_GPT_SET_PTE < cycle )
+printk("\n[DBG] %s : thread[%x,%x] map PTE2 / cxy %x / ix2 %x / pt2 %x / attr %x / ppn %x\n", 
+__FUNCTION__, this->process->pid, this->trdid, gpt_cxy, ix2, pt2_ptr, tsar_attr, ppn );
+#endif
+
+  	    return 0;
     }
-    while (success == false);
-
-    // set PTE2 in this order
-	pt2[2 * ix2 + 1] = ppn;
-	hal_fence();
-	pt2[2 * ix2]     = tsar_attr;
-	hal_fence();
-
-#if DEBUG_HAL_GPT_ACCESS
-cycle = (uint32_t)hal_get_cycles;
-if( DEBUG_HAL_GPT_ACCESS < cycle )
-printk("\n[DBG] %s : thread %x exit / vpn %x / pte2_attr %x / pte2_ppn %x / cycle %d\n", 
-__FUNCTION__, CURRENT_THREAD, vpn, pt2[2 * ix2], pt2[2 * ix2 + 1], cycle );
-#endif
-
-	return 0;
-
 } // end of hal_gpt_set_pte()
 
-
-/////////////////////////////////////
-void hal_gpt_get_pte( gpt_t    * gpt,
+////////////////////////////////////////
+void hal_gpt_get_pte( xptr_t     gpt_xp,
                       vpn_t      vpn,
                       uint32_t * attr,
@@ -490,30 +490,42 @@
     ppn_t      pt2_ppn;
 
+    // get cluster and local pointer on GPT
+    cxy_t   gpt_cxy = GET_CXY( gpt_xp );
+    gpt_t * gpt_ptr = GET_PTR( gpt_xp );
+
+    // compute indexes in PT1 and PT2
     uint32_t   ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
     uint32_t   ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
 
-    // get PTE1 value
-	pt1  = gpt->ptr;
-    pte1 = pt1[ix1];
-
+    // get PT1 base
+    pt1 = (uint32_t *)hal_remote_lpt( XPTR( gpt_cxy , &gpt_ptr->ptr ) );
+    
+    // get pte1
+    pte1 = hal_remote_l32( XPTR( gpt_cxy , &pt1[ix1] ) );
+
+    // check PTE1 mapped
 	if( (pte1 & TSAR_MMU_MAPPED) == 0 )   // PT1 entry not present
 	{
 		*attr = 0;
 		*ppn  = 0;
+        return;
 	}
 
+    // access GPT
 	if( (pte1 & TSAR_MMU_SMALL) == 0 )     // it's a PTE1
 	{
+        // get PPN & ATTR from PT1
 		*attr = tsar2gpt( TSAR_MMU_ATTR_FROM_PTE1( pte1 ) );
         *ppn  = TSAR_MMU_PPN_FROM_PTE1( pte1 ) | (vpn & ((1<<TSAR_MMU_IX2_WIDTH)-1));
 	}
-    else                              // it's a PTD1
+    else                                  // it's a PTD1
     {
         // compute PT2 base address
         pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
-        pt2     = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) );
-
-	    *ppn  = pt2[2*ix2+1] & ((1<<TSAR_MMU_PPN_WIDTH)-1);
-	    *attr = tsar2gpt( pt2[2*ix2] );
+        pt2     = GET_PTR( ppm_ppn2base( pt2_ppn ) );
+
+        // get PPN & ATTR from PT2
+        *ppn  = hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2+1] ) ) & ((1<<TSAR_MMU_PPN_WIDTH)-1);
+        *attr = tsar2gpt( hal_remote_l32( XPTR( gpt_cxy , &pt2[2*ix2] ) ) );
     }
 } // end hal_gpt_get_pte()
@@ -528,6 +540,4 @@
     ppn_t      pt2_ppn;     // PPN of PT2 
     uint32_t * pt2;         // PT2 base address
-
-    ppn_t      ppn;         // PPN of page to be released
 
     // get ix1 & ix2 indexes
@@ -546,7 +556,4 @@
 	if( (pte1 & TSAR_MMU_SMALL) == 0 )      // it's a PTE1
 	{
-        // get PPN 
-        ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 );
-
         // unmap the big page
         pt1[ix1] = 0;
@@ -559,11 +566,8 @@
         // compute PT2 base address
         pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
-        pt2 = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) );
+        pt2     = GET_PTR( ppm_ppn2base( pt2_ppn ) );
         
-        // get PPN
-	    ppn = TSAR_MMU_PPN_FROM_PTE2( pt2[2*ix2+1] );
-
         // unmap the small page
-	    pt2[2*ix2]   = 0;            // only attr is reset
+	    pt2[2*ix2]   = 0;          
 	    hal_fence();        
 
@@ -623,5 +627,5 @@
         page_xp = XPTR( local_cxy , page );
         pt2_ppn = ppm_page2ppn( page_xp );
-        pt2     = (uint32_t *)GET_PTR( ppm_page2base( page_xp ) );
+        pt2     = GET_PTR( ppm_page2base( page_xp ) );
 
         // try to set the PT1 entry
@@ -643,5 +647,5 @@
             // get the PT2 base address
 			pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 );
- 			pt2     = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) );
+ 			pt2     = GET_PTR( ppm_ppn2base( pt2_ppn ) );
 		}
 	}
@@ -660,5 +664,5 @@
 
         // compute pointer on PT2 base
-	    pt2 = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) );
+	    pt2 = GET_PTR( ppm_ppn2base( pt2_ppn ) );
     }
     
@@ -720,5 +724,5 @@
     // get pointer on PT2 base
     pt2_ppn = TSAR_MMU_PPN_FROM_PTE1( pte1 );
-    pt2     = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) );
+    pt2     = GET_PTR( ppm_ppn2base( pt2_ppn ) );
  
     // get pointer on PTE2
@@ -762,5 +766,5 @@
     uint32_t   * dst_pt2;   // local pointer on DST PT2
 
-	kmem_req_t   req;       // for dynamic PT2 allocation
+	kmem_req_t   req;       // for PT2 allocation
 
     uint32_t     src_pte1;
@@ -776,14 +780,19 @@
     ppn_t        dst_pt2_ppn;
 
-#if DEBUG_HAL_GPT_ACCESS
-uint32_t cycle = (uint32_t)hal_get_cycles;
-if( DEBUG_HAL_GPT_ACCESS < cycle )
-printk("\n[DBG] %s : thread %x enter / vpn %x / cycle %d\n", 
-__FUNCTION__, CURRENT_THREAD, vpn, cycle );
-#endif
-
     // get remote src_gpt cluster and local pointer
     src_cxy = GET_CXY( src_gpt_xp );
-    src_gpt = (gpt_t *)GET_PTR( src_gpt_xp );
+    src_gpt = GET_PTR( src_gpt_xp );
+
+#if DEBUG_HAL_GPT_COPY
+uint32_t   cycle = (uint32_t)hal_get_cycles();
+thread_t * this  = CURRENT_THREAD;
+if( DEBUG_HAL_GPT_COPY < cycle )
+printk("\n[DBG] %s : thread[%x,%x] enter / vpn %x / src_cxy %x / dst_cxy %x / cycle %d\n", 
+__FUNCTION__, this->process->pid, this->trdid, vpn, src_cxy, local_cxy, cycle );
+#endif
+
+    // get remote src_gpt cluster and local pointer
+    src_cxy = GET_CXY( src_gpt_xp );
+    src_gpt = GET_PTR( src_gpt_xp );
 
     // get remote src_pt1 and local dst_pt1
@@ -837,9 +846,9 @@
         // get pointer on src_pt2
         src_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( src_pte1 );
-        src_pt2     = (uint32_t *)GET_PTR( ppm_ppn2base( src_pt2_ppn ) );
+        src_pt2     = GET_PTR( ppm_ppn2base( src_pt2_ppn ) );
 
         // get pointer on dst_pt2
         dst_pt2_ppn = (ppn_t)TSAR_MMU_PTBA_FROM_PTE1( dst_pte1 );
-        dst_pt2     = (uint32_t *)GET_PTR( ppm_ppn2base( dst_pt2_ppn ) );
+        dst_pt2     = GET_PTR( ppm_ppn2base( dst_pt2_ppn ) );
 
         // get attr and ppn from SRC_PT2
@@ -867,9 +876,9 @@
             *ppn    = src_pte2_ppn;
         
-#if DEBUG_HAL_GPT_ACCESS
+#if DEBUG_HAL_GPT_COPY
 cycle = (uint32_t)hal_get_cycles;
-if( DEBUG_HAL_GPT_ACCESS < cycle )
-printk("\n[DBG] %s : thread %x exit / copy done for vpn %x / cycle %d\n", 
-__FUNCTION__, CURRENT_THREAD, vpn, cycle );
+if( DEBUG_HAL_GPT_COPY < cycle )
+printk("\n[DBG] %s : thread[%x,%x] exit / copy done for vpn %x / cycle %d\n", 
+__FUNCTION__, this->process->pid, this->trdid, vpn, cycle );
 #endif
 
@@ -884,9 +893,9 @@
     *ppn    = 0;
    
-#if DEBUG_HAL_GPT_ACCESS
+#if DEBUG_HAL_GPT_COPY
 cycle = (uint32_t)hal_get_cycles;
-if( DEBUG_HAL_GPT_ACCESS < cycle )
-printk("\n[DBG] %s : thread %x exit / nothing done for vpn %x / cycle %d\n", 
-__FUNCTION__, CURRENT_THREAD, vpn, cycle );
+if( DEBUG_HAL_GPT_COPY < cycle )
+printk("\n[DBG] %s : thread[%x,%x] exit / nothing done for vpn %x / cycle %d\n", 
+__FUNCTION__, this->process->pid, this->trdid, vpn, cycle );
 #endif
 
@@ -921,5 +930,5 @@
     // compute PT2 base address
     pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
-    pt2     = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) );
+    pt2     = GET_PTR( ppm_ppn2base( pt2_ppn ) );
 
     // get pte2_attr
@@ -955,5 +964,5 @@
     // compute PT2 base address
     pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
-    pt2     = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) );
+    pt2     = GET_PTR( ppm_ppn2base( pt2_ppn ) );
 
     // get pte2_attr
@@ -989,5 +998,5 @@
     // get GPT cluster and local pointer
     gpt_cxy = GET_CXY( gpt_xp );
-    gpt_ptr = (gpt_t *)GET_PTR( gpt_xp );
+    gpt_ptr = GET_PTR( gpt_xp );
 
     // get local PT1 pointer
@@ -1008,5 +1017,5 @@
             // compute PT2 base address
             pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
-            pt2     = (uint32_t*)GET_PTR( ppm_ppn2base( pt2_ppn ) );
+            pt2     = GET_PTR( ppm_ppn2base( pt2_ppn ) );
 
             assert( (GET_CXY( ppm_ppn2base( pt2_ppn ) ) == gpt_cxy ),
@@ -1050,5 +1059,5 @@
     // get cluster and local pointer on remote GPT
     cxy_t   gpt_cxy = GET_CXY( gpt_xp );
-    gpt_t * gpt_ptr = (gpt_t *)GET_PTR( gpt_xp );
+    gpt_t * gpt_ptr = GET_PTR( gpt_xp );
 
     // compute indexes in PT1 and PT2
@@ -1070,9 +1079,5 @@
     // get PT2 base from PTE1 
     pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
-    pt2     = (uint32_t *)GET_PTR( ppm_ppn2base( pt2_ppn ) );
-
-    // reset PTE2
-	hal_remote_s32( XPTR( gpt_cxy, &pt2[2 * ix2]     ) , 0 );
-	hal_fence();
+    pt2     = GET_PTR( ppm_ppn2base( pt2_ppn ) );
 
     // set PTE2 in this order
