Changeset 624 for trunk/hal/tsar_mips32/core/hal_gpt.c

Timestamp:

Mar 12, 2019, 1:37:38 PM (5 years ago)

Author:

alain

Message:

Fix several bugs to use the instruction MMU in kernel mode
in replacement of the instruction address extension register,
and remove the "kentry" segment.

This version is running on the tsar_generic_iob" platform.

One interesting bug: the cp0_ebase defining the kernel entry point
(for interrupts, exceptions and syscalls) must be initialized
early in kernel_init(), because the VFS initialisation done by
kernel_ini() uses RPCs, and RPCs uses Inter-Processor-Interrup.

File:

• trunk/hal/tsar_mips32/core/hal_gpt.c (modified) (3 diffs)

trunk/hal/tsar_mips32/core/hal_gpt.c

@@ -174 +174 @@
 } // end hal_gpt_create()
 
-
 ///////////////////////////////////
 void hal_gpt_destroy( gpt_t * gpt )
@@ -334 +333 @@
 
 
-/////////////////////////////////////////////////////////////////////////////////////
-// FOr the TSAR architecture, this function allocates a first level PT1 (8 Kbytes),
-// and maps one single big page for the kerne code segment in slot[0].
-/////////////////////////////////////////////////////////////////////////////////////
-void hal_gpt_build_kpt( cxy_t   cxy,
-                        gpt_t * gpt )
-{
-    error_t error;
-
-    // allocate memory for one gpt
-    error = hal_gpt_create( gpt );
-
-    if( error )
-    {
-        printk("\n[PANIC] in %s : cannot allocate kernel GPT in cluster %x\n",
-        __FUNCTION__ , cxy );
-        hal_core_sleep();
-    }
-
-    // compute attr and ppn for one PTE1
-    uint32_t attr  = 0xCA800000;           // bits : V,T,C,X,G
-    uint32_t ppn   = (cxy << 20) >> 9;
-
-    // set PTE1 
-    error = hal_gpt_set_pte( XPTR( cxy , gpt ) , 0 , attr , ppn );
-
-    if( error )
-    {
-        printk("\n[PANIC] in %s : cannot initialize kernel GPT in cluster %x\n",
-        __FUNCTION__ , cxy );
-        hal_core_sleep();
-    }
-}
-
 //////////////////////////////////////////
 error_t hal_gpt_set_pte( xptr_t    gpt_xp,
@@ -617 +582 @@
 }  // end hal_gpt_reset_pte()
 
+
+/* unused until now (march 2019) [AG]
+
+//////////////////////////////////////
+void hal_gpt_reset_range( gpt   * gpt,
+                          vpn_t   vpn_min,
+                          vpn_t   vpn_max )
+{
+    vpn_t      vpn;         // current vpn
+
+    uint32_t * pt1;         // PT1 base address
+    uint32_t   pte1;        // PT1 entry value
+
+    ppn_t      pt2_ppn;     // PPN of PT2 
+    uint32_t * pt2;         // PT2 base address
+
+    uint32_t   ix1;         // index in PT1
+    uint32_t   ix2;         // index in PT2
+
+    // get PT1
+    pt1 = gpt->ptr;
+
+    // initialize current index
+    vpn = vpn_min;
+
+    // loop on pages
+    while( vpn <= vpn_max )
+    {
+        // get ix1 index from vpn
+        ix1 = TSAR_MMU_IX1_FROM_VPN( vpn );
+
+        // get PTE1
+        pte1 = pt1[ix1]
+
+            if( (pte1 & TSAR_MMU_MAPPED) == 0 )     // PT1[ix1] unmapped 
+        {
+            // update vpn (next big page)
+            (vpn = ix1 + 1) << 9;
+        }
+            if( (pte1 & TSAR_MMU_SMALL) == 0 )      // it's a PTE1 (big page)
+            {
+            // unmap the big page
+            pt1[ix1] = 0;
+                hal_fence();
+            
+            // update vpn (next big page)
+            (vpn = ix1 + 1) << 9;
+        }
+        else                                    // it's a PTD1 (small page)
+        {
+            // compute PT2 base address
+            pt2_ppn = TSAR_MMU_PTBA_FROM_PTE1( pte1 );
+            pt2     = GET_PTR( ppm_ppn2base( pt2_ppn ) );
+
+            // get ix2 index from vpn
+            ix2 = TSAR_MMU_IX2_FROM_VPN( vpn );
+
+            // unmap the small page
+            pt2[2*ix2]   = 0;          
+            hal_fence();        
+
+            // update vpn (next small page)
+            vpn++;
+        }
+    }
+}  // hal_gpt_reset_range()
+*/
+
 //////////////////////////////////////
 error_t hal_gpt_lock_pte( gpt_t * gpt,