Changeset 686 for trunk/hal/tsar_mips32/core/hal_gpt.c
- Timestamp:
- Jan 13, 2021, 12:47:53 AM (3 years ago)
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trunk/hal/tsar_mips32/core/hal_gpt.c
r679 r686 2 2 * hal_gpt.c - implementation of the Generic Page Table API for TSAR-MIPS32 3 3 * 4 * Author Alain Greiner (2016,2017,2018,2019 )4 * Author Alain Greiner (2016,2017,2018,2019,2020) 5 5 * 6 6 * Copyright (c) UPMC Sorbonne Universites … … 37 37 38 38 //////////////////////////////////////////////////////////////////////////////////////// 39 // The Page Table for the TSAR-MIPS32 MMU is defined as a two levels radix tree. 40 // 41 // It defines two page sizes : 4 Kbytes pages, and 2 Mbytes pages. 42 // The virtual address space size is 4 Gbytes (32 bits virtual addresses). 43 // The physical address space is limited to 1 Tbytes (40 bits physical addresses). 44 // - For a 4 Kbytes page, the VPN uses 20 bits, and the PPN requires 28 bits. 45 // - For a 2 Mbytes page, the PPN uses 11 bits, and the PPN requires 19 bits. 46 // 47 // The first level array (PT1) contains 2048 entries, each entry contains 4 bytes, 48 // and this array is aligned on a 8K bytes boundary. 49 // 50 // The second level array (PT2) contains 512 entries, each entry contains 8 bytes, 51 // and this array is ligned on a 4K bytes boundary. 52 //////////////////////////////////////////////////////////////////////////////////////// 53 54 55 //////////////////////////////////////////////////////////////////////////////////////// 39 56 // This define the masks for the TSAR MMU PTE attributes (from TSAR MMU specification) 40 57 //////////////////////////////////////////////////////////////////////////////////////// … … 152 169 153 170 // check page size 154 assert( __FUNCTION__, (CONFIG_PPM_PAGE_SIZE == 4096) , "the TSAR page size must be 4 Kbytes\n" ); 155 156 // allocates 2 physical pages for PT1 157 kmem_req_t req; 158 req.type = KMEM_PPM; 159 req.order = 1; // 2 small pages 160 req.flags = AF_KERNEL | AF_ZERO; 161 base = kmem_alloc( &req ); 171 assert( __FUNCTION__, (CONFIG_PPM_PAGE_SIZE == 4096) , 172 "the TSAR page size must be 4 Kbytes\n" ); 173 174 // allocates 8 Kbytes for PT1 175 base = kmem_alloc( 13 , AF_ZERO ); 162 176 163 177 if( base == NULL ) … … 197 211 uint32_t * pt2; 198 212 uint32_t attr; 199 kmem_req_t req;200 213 201 214 thread_t * this = CURRENT_THREAD; … … 241 254 } 242 255 243 // release the page allocated for the PT2 244 req.type = KMEM_PPM; 245 req.ptr = pt2; 246 kmem_free( &req ); 256 // release the 4K bytes allocated for the PT2 257 kmem_free( pt2 , 12 ); 247 258 } 248 259 } 249 260 } 250 261 251 // release the PT1 252 req.type = KMEM_PPM; 253 req.ptr = pt1; 254 kmem_free( &req ); 262 // release the 8K bytes allocated for PT1 263 kmem_free( pt1 , 13 ); 255 264 256 265 #if DEBUG_HAL_GPT_DESTROY … … 272 281 xptr_t pte1_xp; // extended pointer on PT1[x1] entry 273 282 uint32_t pte1; // value of PT1[x1] entry 274 275 kmem_req_t req; // kmem request fro PT2 allocation276 277 283 uint32_t * pt2; // local pointer on PT2 base 278 284 ppn_t pt2_ppn; // PPN of page containing PT2 … … 334 340 hal_disable_irq( &sr_save ); 335 341 336 req.type = KMEM_PPM; 337 req.order = 0; 338 req.flags = AF_ZERO | AF_KERNEL; 339 pt2 = kmem_remote_alloc( gpt_cxy , &req ); 342 // allocate a 4K bytes PT2 343 pt2 = kmem_remote_alloc( gpt_cxy , 12 , AF_ZERO ); 340 344 341 345 if( pt2 == NULL ) … … 863 867 uint32_t * dst_pt2; // local pointer on DST PT2 864 868 865 kmem_req_t req; // for PT2 allocation866 867 869 uint32_t src_pte1; 868 870 uint32_t dst_pte1; … … 917 919 if( (dst_pte1 & TSAR_PTE_MAPPED) == 0 ) 918 920 { 919 // allocate one physical page for a new PT2 920 req.type = KMEM_PPM; 921 req.order = 0; // 1 small page 922 req.flags = AF_KERNEL | AF_ZERO; 923 dst_pt2 = kmem_alloc( &req ); 921 // allocate one 4K bytes physical page for a new PT2 922 dst_pt2 = kmem_alloc( 12 , AF_ZERO ); 924 923 925 924 if( dst_pt2 == NULL )
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