Changeset 89 for trunk/hal/x86_64/core

Timestamp:

Jun 29, 2017, 9:54:01 AM (7 years ago)

Author:

max@…

Message:

Parse the IOAPIC structure in ACPI, map the IOAPIC, and enable
the keyboard interrupt. Its queue is not flushed yet.

Location:

trunk/hal/x86_64/core

Files:

• hal_acpi.c (modified) (1 diff)
• hal_acpi.h (modified) (1 diff)
• hal_apic.c (modified) (2 diffs)
• hal_apic.h (modified) (1 diff)
• hal_kentry.S (modified) (4 diffs)
• hal_segmentation.h (modified) (1 diff)
• hal_trap.c (modified) (1 diff)

trunk/hal/x86_64/core/hal_acpi.c

@@ -109 +109 @@
 /* -------------------------------------------------------------------------- */
 
+static void hal_acpi_parse_ioapic(madt_ioapic_t *ioapic)
+{
+        extern paddr_t ioapic_pa;
+        ioapic_pa = ioapic->Address;
+        x86_printf("-> IOAPIC address: %Z\n", ioapic_pa);
+}
+
 static void hal_acpi_parse_madt(madt_t *madt)
 {
+        void *ptr, *end;
+        subheader_t *sub;
+
         extern paddr_t lapic_pa;
         lapic_pa = (paddr_t)madt->Address;
+
+        ptr = (void *)(madt + 1);
+        end = (void *)madt + madt->Header.Length;
+
+        while (ptr < end) {
+                sub = (subheader_t *)ptr;
+                if (sub->Type == ACPI_MADT_TYPE_IO_APIC) {
+                        hal_acpi_parse_ioapic((madt_ioapic_t *)sub);
+                }
+                // XXX: handle lapic override
+                ptr += sub->Length;
+        }
+
         x86_printf("-> LAPIC address: %Z\n", lapic_pa);
 }

trunk/hal/x86_64/core/hal_acpi.h

@@ -179 +179 @@
         uint64_t Address;  /* APIC physical address */
 } __packed;
-typedef struct acpi_madt_local_apic_override madt_lapic_override;
+typedef struct acpi_madt_local_apic_override madt_lapic_override_t;
 
+struct acpi_madt_io_apic {
+        subheader_t Header;
+        uint8_t Id;             /* I/O APIC ID */
+        uint8_t Reserved;       /* Reserved - must be zero */
+        uint32_t Address;       /* APIC physical address */
+        uint32_t GlobalIrqBase; /* Global system interrupt where INTI lines start */
+} __packed;
+typedef struct acpi_madt_io_apic madt_ioapic_t;
+

trunk/hal/x86_64/core/hal_apic.c

@@ -50 +50 @@
         out8(PIC1_DATA, 0xff);
         out8(PIC2_DATA, 0xff);
+}
+
+/* -------------------------------------------------------------------------- */
+
+paddr_t ioapic_pa __in_kdata = 0;
+vaddr_t ioapic_va __in_kdata = 0;
+
+#define IRQ_TIMER       0x00
+#define IRQ_KEYBOARD    0x01
+#define IRQ_COM2        0x03
+#define IRQ_COM1        0x04
+#define IRQ_FLOPPY      0x06
+#define IRQ_ATA0        0x0e
+#define IRQ_ATA1        0x0f
+
+#define IOREGSEL        0x00
+#define IOWIN   0x10
+
+#define IOAPICID        0x00
+#define IOAPICVER       0x01
+#define IOAPICARB       0x02
+#define IOREDTBL        0x10
+
+#define IOENTRY_DISABLE 0x10000
+
+void hal_ioapic_write(uint8_t reg, uint32_t val)
+{
+        *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg;
+        *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN)) = val;
+}
+
+uint32_t hal_ioapic_read(uint8_t reg)
+{
+        *((volatile uint32_t *)((uint8_t *)ioapic_va + IOREGSEL)) = reg;
+        return *((volatile uint32_t *)((uint8_t *)ioapic_va + IOWIN));
+}
+
+void hal_ioapic_set_entry(uint8_t index, uint64_t data)
+{
+        hal_ioapic_write(IOREDTBL + index * 2, (uint32_t)(data & 0xFFFFFFFF));
+        hal_ioapic_write(IOREDTBL + index * 2 + 1, (uint32_t)(data >> 32));
+}
+
+static void hal_ioapic_init()
+{
+        size_t i, pins;
+        uint32_t ver;
+
+        ioapic_va = hal_gpt_bootstrap_valloc(1); // XXX: should be shared
+
+        hal_gpt_enter(ioapic_va, ioapic_pa, PG_V|PG_KW|PG_NX|PG_N);
+
+        ver = hal_ioapic_read(IOAPICVER);
+        pins = ((ver >> 16) & 0xFF) + 1;
+
+        /* Explicitly disable (mask) each vector */
+        for (i = 0; i < pins; i++) {
+                hal_ioapic_set_entry(i, IOENTRY_DISABLE);
+        }
+
+        /* Now, enable the keyboard */
+        hal_ioapic_set_entry(IRQ_KEYBOARD, IOAPIC_KEYBOARD_VECTOR);
 }
 
@@ -122 +184 @@
         /* Enable the LAPIC */
         hal_lapic_init();
+
+        /* Enable the IOAPIC */
+        hal_ioapic_init();
 }
 

trunk/hal/x86_64/core/hal_apic.h

@@ -27 +27 @@
 #define LAPIC_SPURIOUS_VECTOR   LAPICVEC_MIN
 #define LAPIC_TIMER_VECTOR      (LAPICVEC_MIN + 1)
+#define IOAPIC_KEYBOARD_VECTOR  (LAPICVEC_MIN + 2)
 
 #define LAPIC_ID                0x020   /* ID. RW */

trunk/hal/x86_64/core/hal_kentry.S

@@ -36 +36 @@
         .globl  hal_trap_entry
         .globl  hal_timer_intr
+        .globl  hal_keyboard_intr
         .type   hal_trap_entry, @function
         .type   hal_timer_intr, @function
+        .type   hal_keyboard_intr, @function
 
         /*
@@ -119 +121 @@
 
         /*
-         * LAPIC interrupts.
+         * APIC interrupts.
          */
 ASM_ENTRY(x86_lapic_spurious)
@@ -131 +133 @@
         movq    %rsp,%rdi
         call    hal_timer_intr
+
+        movq    lapic_va(%rip),%rax
+        movl    $0,LAPIC_EOI(%rax)
+
+        INTR_RESTORE_REGS
+        addq    $16,%rsp
+        iretq
+
+ASM_ENTRY(x86_ioapic_keyboard)
+        pushq   $0
+        pushq   $T_ASTFLT
+        INTR_SAVE_REGS
+
+        movq    %rsp,%rdi
+        call    hal_keyboard_intr
 
         movq    lapic_va(%rip),%rax
@@ -182 +199 @@
         .quad   x86_lapic_spurious
         .quad   x86_lapic_timer
-
+        .quad   x86_ioapic_keyboard
+

trunk/hal/x86_64/core/hal_segmentation.h

@@ -194 +194 @@
 #define CPUVEC_MAX      32      /* reserved entries for CPU exceptions */
 #define LAPICVEC_MIN    CPUVEC_MAX
-#define LAPICVEC_MAX    (LAPICVEC_MIN + 2)
+#define LAPICVEC_MAX    (LAPICVEC_MIN + 3)
 
 #define NIDT    256     /* total number of IDT entries */

trunk/hal/x86_64/core/hal_trap.c

@@ -82 +82 @@
 }
 
+/*
+ * Keyboard interrupt
+ */
+void hal_keyboard_intr(struct trapframe *tf)
+{
+        x86_printf("-> got keyboard: rip=%Z\n", tf->tf_rip);
+        return;
+}
+