source: trunk/hal/x86_64/core

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Diff Rev Age Author Log Message
(edit) @408   4 years alain Fix several bugs in the fork() syscall.
(edit) @407   4 years alain First implementation of fork/exec.
(edit) @406   4 years alain This version executed successfully the user "init" process on a …
(edit) @405   4 years max Remove XXX, it's fine.
(edit) @403   4 years max Sync with TSAR.
(edit) @397   4 years max Use panic().
(edit) @392   4 years max Start handling page faults. Not tested.
(edit) @387   4 years max Handle the return from exception.
(edit) @386   4 years max Implement several GPT functions.
(edit) @383   4 years max Use constant flags.
(edit) @382   4 years max Sync with TSAR.
(edit) @371   4 years max Treat user/kern exceptions differently.
(edit) @370   4 years max Old can be NULL.
(edit) @368   4 years max Switch the VM space, and explicitly disable the FPU.
(edit) @365   4 years max Remove debug function.
(edit) @361   4 years max Pass the function argument to the new thread.
(edit) @360   4 years max Add a panic, for now we are only switching between kernel threads.
(edit) @359   4 years max Synchronize tls_intr between context switches.
(edit) @348   4 years max We don't support irqbase != 0.
(edit) @346   4 years max Hide soclib_iob.
(edit) @345   4 years max Initialize rsp0 (in both the TSS and the TLS).
(edit) @344   4 years max Call core_clock - the computation in this function still needs to be fixed.
(edit) @343   4 years max Mmh, skip tf_trapno and tf_err for iretq.
(edit) @342   4 years max Initialize tf_ss, and don't forget to update tls_thr.
(edit) @341   4 years max Set %eoi earlier for rescheduling interrupts, otherwise the timer …
(edit) @340   4 years max Remove debug code - it's useless anyway.
(edit) @339   4 years max Add support for context switch - not tested yet, due to some other …
(edit) @336   4 years max Rename curcpu -> curtls.
(edit) @335   4 years max Separate the CPU context from the trap frame.
(edit) @329   4 years max Initialize %rbp.
(edit) @327   4 years max Clean up, and fix several SMP-related issues. The LAPIC timer is still …
(edit) @323   4 years max Clean up, and define strstr() in libk.
(edit) @320   4 years max Remove unused.
(edit) @319   4 years max Don't forget to unmap the region below the kernel. Useful to detect …
(edit) @316   4 years max Synchronize with Alain's changes. Still several issues.
(edit) @315   4 years alain Redefine the fuctions ppm_base2page() / ppm_page2base() / …
(edit) @314   4 years max Add hal_remote_memset.
(edit) @312   4 years max Add a --no-smp option.
(edit) @311   4 years max Introduce hal_cpu_context_switch.
(edit) @310   4 years max Use pause().
(edit) @309   4 years max Add clts/stts.
(edit) @308   4 years max Add a basic syscall entry.
(edit) @307   4 years max Forgot to commit this yesterday.
(edit) @299   4 years max The uspace strcpy function is allowed to fail (not implemented yet).
(edit) @298   4 years max Sync with TSAR.
(edit) @293   4 years max Fix previous. Still don't know where the race comes from…
(edit) @292   4 years max Use different stacks for NMIs and Double Faults.
(edit) @290   4 years max Define prototype.
(edit) @285   4 years max Must be reg_t.
(edit) @283   4 years max horror
(edit) @280   4 years max sync
(edit) @276   4 years max update
(edit) @275   4 years max Add a SRAT parser. For some reason, QEMU does not want to enable the …
(edit) @274   4 years max Add tls_tf.
(edit) @272   4 years max Use local_cxy for GET_PTR, instead of the triple map. This fixes a …
(edit) @261   5 years max Hide soclib_dma.
(edit) @259   5 years max Hide soclib_nic.
(edit) @257   5 years max Hide soclib_mmc.
(edit) @256   5 years max Remove the IRQ line. It will have to be enabled somewhere in the HAL.
(edit) @255   5 years max Don't route the IRQ for IMPL_TXT_RS2, it is multiplexed in software.
(edit) @254   5 years max Use IMPL_TXT_RS2.
(edit) @252   5 years max Hide IMPL_PIC_.
(edit) @250   5 years max Remove XCU on x86; not sure if it's still useful on TSAR…
(edit) @247   5 years max Rename soclib_tty->txt_rs232.
(edit) @245   5 years max Hide soclib_tty.
(edit) @243   5 years max Mmh, some CPUs can boot with the cache disabled, so explicitly enable it.
(edit) @242   5 years max add a dumb lock for the console
(edit) @241   5 years max some LAPICs can be disabled
(edit) @240   5 years max Make the secondary CPUs jump into kernel_init().
(edit) @237   5 years max Attach the secondary CPUs, and for now route the keyboard irq to cpu1 …
(edit) @236   5 years max Launch the secondary CPUs. For now, they all say hello and enter an …
(edit) @235   5 years max Start adding some code for SMP support
(edit) @234   5 years max style
(edit) @233   5 years max Push the context entirely for an exception.
(edit) @226   5 years max add HAL_32BIT/HAL_64BIT
(edit) @225   5 years max implement hal_gpt_create
(edit) @224   5 years max Create a (virtual) copy of the local cluster in 0xffffe00000000000, …
(edit) @220   5 years max use the asm entry point to save the context
(edit) @216   5 years max dispatch 'impl' in the hal
(edit) @215   5 years max rename the ATA driver
(edit) @213   5 years max hide soclib_bdv
(edit) @209   5 years max add hal_remote_strcpy
(edit) @203   5 years max start moving the APIC code into the PIC driver
(edit) @202   5 years max register the ATA IRQs
(edit) @199   5 years max map the LAPIC and IOAPIC in a separate function
(edit) @198   5 years max mmh, mistakenly removed this
(edit) @197   5 years max rename soclib->apic
(edit) @196   5 years max sync
(edit) @195   5 years max add IOC (ATA)
(edit) @193   5 years max build the context
(edit) @192   5 years max initialize pic
(edit) @190   5 years max hide soclib
(edit) @189   5 years max sync
(edit) @187   5 years max count the number of IOAPICs
(edit) @169   5 years max remove unused var
(edit) @168   5 years max make the TLS initialization per-cpu
(edit) @167   5 years max define the TLS in hal_segmentation.h
(edit) @166   5 years max identify the cpu features
(edit) @165   5 years max put the per-cpu structures into one structure
(edit) @164   5 years max we're gonna use an array of TSSs
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