Changes between Version 33 and Version 34 of io_operations


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Timestamp:
Nov 22, 2017, 5:51:50 PM (5 years ago)
Author:
alain
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a

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  • io_operations

    v33 v34  
    102102== G) Interrupts Routing ==
    103103
    104 The completion of an I/O operation is signaled by the involved hardware device using an interrupt. This interrupt must be handled by the core running the server thread that launched the I/O operation. Therefore, the interrupt must be routed to the cluster containing the device descriptor involved in the I/O operation. ALMOS-MKH makes the assumption that interrupt routing (from peripherals to cores) is done by a dedicated hardware device, called PIC (Programmable Interrupt Controller). The main service provide by the PIC device is to allow the OS to route any IRQ (generated by a given peripheral channel to any core.
     104The completion of an I/O operation is signaled by the involved hardware device using an interrupt. In ALMOS-MKH,  this interrupt is handled by the core running the server thread that launched the I/O operation. Therefore, the interrupt must be routed to the cluster containing the device descriptor involved in the I/O operation.
    105105
    106 This generic PIC device is supposed to be implemented by a ''distributed'' hardware infrastructure containing two types of hardware components:
    107  * The IOPIC component (one single component in I/O cluster) interfaces the externals peripheral IRQs (one IPQ per channel) to the PIC infrastructure
     106ALMOS-MKH makes the assumption that interrupt routing (from peripherals to cores) is done by a dedicated hardware device, called '''PIC''' (Programmable Interrupt Controller). This hardware device also helps the the kernel interrupt
     107handler, running on the selected core, to select the relevant ISR (Interrupt Service Routine) to be executed.
     108
     109This PIC device handles the four following types of interrupts:
     110 1.  '''EXT_IRQ''' (External IRQ) generated by the external (shared) peripherals.
     111 1. '''INT_IRQ''' (Internal IRQ) generated by the internal (replicated) peripherals.
     112 1. '''TIM_IRQ''' (Timer IRQ) generated by the timers (one timer per core).
     113 1. '''IPI_IRQ''' (Inter Processor IRQ) generated by software (one IPI per core).
     114
     115This generic PIC device is supposed to be implemented as a ''distributed'' hardware infrastructure containing two types of hardware components:
     116 * The IOPIC component (one single component in I/O cluster) interfaces the externals IRQs (one IRQ per channel) to the PIC infrastructure
    108117 * The LAPIC components (one component per cluster) interfaces the PIC infrastructure to the local cores in a given cluster.
    109118
    110 Each external IRQ (IRQ generated by a given external device channel) is identified by a '''irq_id''' index, used as an identifier by the kernel. For a given hardware architecture, this '''irq_id''' index is defined by the ''arch_info'' file describing the architecture, and is registered by the kernel in the '''iopic_input''' structure, that is a global variable replicated in all clusters.
     119=== 1) EXT_IRQ ===
    111120
    112 The actual interrupt routing is defined during the PIC device initialization, by the architecture specific PIC driver, as defined below.
     121Each external IRQ is identified by an '''irq_id''' index, used as an identifier by the kernel. For a given hardware architecture, this index is defined - for each external device channel - by the ''arch_info'' file describing the architecture, and is registered by the kernel in the '''iopic_input''' structure, that is a global variable replicated in all clusters, allocated in the ''kernel_init.c'' file.
    113122
    114 === TSAR_MIPS32 architecture ===
     123The actual interrupt routing is statically defined during the PIC device initialization, by the architecture specific PIC driver,
     124using the ''dev_pic_bind_irq()'' function. This function statically links the EXT_IRQ identified by its irq_id to the core running the server thread associated to the external device channel that is the source of the EXT_IRQ.
    115125
    116 The IOPIC external controller provides two services:
    117  1. It translate each IRQ identified by its '''irq_id''' to a write transactions to a specific mailbox contained in a local LAPIC controller, for a given core in a given cluster. as explained below.
     126=== 2) INT_IRQ ===
     127
     128Each internal IRQ is identified by an '''irq_id''' index, used as an identifier by the kernel. For a given hardware architecture, this  index is defined - for each internal device channel - by the ''arch_info'' file describing the architecture, and is registered by the kernel in the '''lapic_input''' structure, that is a global variable defined in all clusters.
     129
     130The actual interrupt routing is local : For an internal peripheral, the server thread is always placed on a local core. The INT_IRQ, identified by its irq_id, is statically linked to the local core running the server thread by the ''dev_pic_bind_irq()'' function. 
     131
     132=== 3) TIM_IRQ ===
     133
     134The timers generating the interrupts used for context switch are supposed to be implemented in the local LAPIC component. There is one timer, and one timer IRQ per local core, identified by an '''irq_id''' index, used as an identifier by the kernel.
     135
     136The TIM_IRQ identified by its '''irq_id''' is statically linked to the local core that has the same local index value.
     137
     138=== 4) IPI IRQ ===
     139
     140To reduce various synchronisation mechanisms, ALMOS-MKH uses IPIs (Inter Processor Interrupt) : Any kernel instance, running on any corein any cluster can send an IPI to any other core in the architecture. An IPI is handled as a special interrupt by the target core, and simply forces a scheduling on the target core.
     141
     142== H) Implementations ==
     143
     144=== - TSAR_MIPS32 architecture ===
     145
     146In the TASR_MIPS32 architecture, the IOPIC external controller provides two services:
     147 1. It translate each IRQ identified by its '''irq_id''' to a write transactions to a specific mailbox contained in a local LAPIC controller, for a given core in a given cluster.
    118148 1. It allows the kernel to selectively enable/disable any external IRQ identified by its '''irq_id''' index.
    119149
    120 The LAPIC controller (called XCU) is replicated in all clusters containing at least one core. It handle three types of IRQs:  The '''HWI''' (HardWare Interrupts) are generated by local internal peripherals, and connected to the local XCU, to be routed to a given local core. The '''WTI''' ( Write Triggered Interrupts) are actually mailboxes implemented in the local XCU. They are used to implement both software IPIs (Inter-Processor-Interrupts),
    121 or to register the external IRQs (write transactions) generated by the IOPIC controller. Finally the '''PTI''' (Programmable Timer Interrupts) are actually timers contained contained in the LAPIC,programmed by the kernel,
    122 and routed to a local core to implement context switches (TICK event). The numbers of interrupts of each type in a given cluster are defined in the XCU_CONFIG register of the XCU component, and cannot be larger than the
    123 SOCLIB_MAX_HWI, SOCLIB_MAX_WTI, SOCLIB_MAX_PTI constants defined in the '' soclib_pic.h'' file.
     150The LAPIC controller (called XCU) is replicated in all clusters containing at least one core. It handle three types of event:
     151 1. A '''HWI''' (HardWare Interrupt) is generated by local internal peripherals. This type implements the internal interrupts.(INT_IRQs).
     152 1. A '''PTI''' (Programmable Timer Interrupt) is generated by a software programmable timer implemented in the XCU controller. This type is used to implement the timer interrupts required for context switch.
     153 1. A '''WTI''' (Write Triggered Interrupts) is actually a mailbox implemented in the local XCU. They are used to implement both inter-processor interrupts, or to register the external interrupts generated by the IOPIC controller. The first WTI mailboxes are used for IPI_IRQ (one IPI per local core). The other WTI mailboxes are used for EXT_IRQs.
    124154
    125 The actual IRQ routing policy implemented by the SOCLIB_PIC driver depends on the IRQ type. For the external IRQs, the routing is done by the soclib_pic_bind_irq() function.
    126 
    127  * ''Local Hardware Interrupt''' : There is only two local peripherals. The MMC device is the L2 cache configuration
    128  * '''PTI''' : There is one PTI per local core, and the PTI index is equal to the core local index.
    129  * '''IPI''' : There is one IPI per local core. Each IPI is implemented as a WTI mailbox.
    130  * '''External Hardware Interrupt''' : each external IRQ is translated to a WTI event,
    131 
    132  The LAPIC controller provides three main services:
    133  1. It allows the kernel to selectively enable/disable any IRQ (identified by its type and index) for a given core. It is the kernel responsibility to enable a given IRQ for a single core as a given IRQ event should be handled by only one core.
    134  *   2) It makes a global OR between all enabled IRQs for a given core, to interrupt
    135  *      the core when at least one enabled IRQ is active.
    136  *   3) It is capable to return the highest priority active IRQ of each type.
    137  *      For each type, the lowest index have the highest priority.
     155The actual numbers of events of each type supported by a given XCU component are defined in the XCU_CONFIG register of the XCU component, and cannot be larger than the SOCLIB_MAX_HWI, SOCLIB_MAX_WTI, SOCLIB_MAX_PTI constants defined in the '' soclib_pic.h'' file.
    138156
    139157===  X86_64 architecture ===