Changes between Version 34 and Version 35 of io_operations


Ignore:
Timestamp:
Nov 22, 2017, 6:10:02 PM (5 years ago)
Author:
alain
Comment:

--

Legend:

Unmodified
Added
Removed
Modified
  • io_operations

    v34 v35  
    107107handler, running on the selected core, to select the relevant ISR (Interrupt Service Routine) to be executed.
    108108
    109 This PIC device handles the four following types of interrupts:
     109This PIC device handles four types of interrupts detailed below :
    110110 1.  '''EXT_IRQ''' (External IRQ) generated by the external (shared) peripherals.
    111111 1. '''INT_IRQ''' (Internal IRQ) generated by the internal (replicated) peripherals.
    112  1. '''TIM_IRQ''' (Timer IRQ) generated by the timers (one timer per core).
    113  1. '''IPI_IRQ''' (Inter Processor IRQ) generated by software (one IPI per core).
     112 1. '''TIM_IRQ''' (Timer IRQ) used for context switch by the timers (one timer per core).
     113 1. '''IPI_IRQ''' (Inter Processor IRQ) forced remote scheduling (one IPI per core).
    114114
    115115This generic PIC device is supposed to be implemented as a ''distributed'' hardware infrastructure containing two types of hardware components:
    116  * The IOPIC component (one single component in I/O cluster) interfaces the externals IRQs (one IRQ per channel) to the PIC infrastructure
     116 * The IOPIC component (one single component in I/O cluster) interfaces the externals IRQs (one IRQ per channel) to the PIC infrastructure.
    117117 * The LAPIC components (one component per cluster) interfaces the PIC infrastructure to the local cores in a given cluster.
    118118
     
    121121Each external IRQ is identified by an '''irq_id''' index, used as an identifier by the kernel. For a given hardware architecture, this index is defined - for each external device channel - by the ''arch_info'' file describing the architecture, and is registered by the kernel in the '''iopic_input''' structure, that is a global variable replicated in all clusters, allocated in the ''kernel_init.c'' file.
    122122
    123 The actual interrupt routing is statically defined during the PIC device initialization, by the architecture specific PIC driver,
    124 using the ''dev_pic_bind_irq()'' function. This function statically links the EXT_IRQ identified by its irq_id to the core running the server thread associated to the external device channel that is the source of the EXT_IRQ.
     123The interrupt routing is statically defined during the PIC device initialization, by the architecture specific PIC driver,
     124using the ''dev_pic_bind_irq()'' function. This function statically links the EXT_IRQ identified by its irq_id to the core running the server thread associated to the external device channel that is the source of the EXT_IRQ. As the external devices server threads are distributed on all cores in all clusters, the corresponding IRQs are routed to all relevant clusters.
    125125
    126126=== 2) INT_IRQ ===
    127127
    128 Each internal IRQ is identified by an '''irq_id''' index, used as an identifier by the kernel. For a given hardware architecture, this  index is defined - for each internal device channel - by the ''arch_info'' file describing the architecture, and is registered by the kernel in the '''lapic_input''' structure, that is a global variable defined in all clusters.
     128Each internal IRQ is identified by an '''irq_id''' index, used as an identifier by the kernel. For a given hardware architecture, this  index is defined - for each internal device channel - by the ''arch_info'' file describing the architecture, and is registered by the kernel in the local '''lapic_input''' structure, that is a global variable defined in each cluster.
    129129
    130 The actual interrupt routing is local : For an internal peripheral, the server thread is always placed on a local core. The INT_IRQ, identified by its irq_id, is statically linked to the local core running the server thread by the ''dev_pic_bind_irq()'' function. 
     130The interrupt routing is local : For an internal peripheral, the server thread is always placed on a local core. The INT_IRQ, identified by its irq_id, is statically linked to the local core running the server thread by the ''dev_pic_bind_irq()'' function. 
    131131
    132132=== 3) TIM_IRQ ===
     
    138138=== 4) IPI IRQ ===
    139139
    140 To reduce various synchronisation mechanisms, ALMOS-MKH uses IPIs (Inter Processor Interrupt) : Any kernel instance, running on any corein any cluster can send an IPI to any other core in the architecture. An IPI is handled as a special interrupt by the target core, and simply forces a scheduling on the target core.
     140To reduce various synchronisation mechanisms, ALMOS-MKH uses IPIs (Inter Processor Interrupt) : Any kernel instance, running on any corein any cluster can send an IPI to any other core in the architecture, using a remote write access to the relevant register in the PIC infrastructure. An IPI is handled as a special interrupt by the target core, and simply forces a scheduling on the target core.
    141141
    142142== H) Implementations ==
    143143
    144 === - TSAR_MIPS32 architecture ===
     144=== 1. TSAR_MIPS32 architecture ===
    145145
    146146In the TASR_MIPS32 architecture, the IOPIC external controller provides two services:
    147  1. It translate each IRQ identified by its '''irq_id''' to a write transactions to a specific mailbox contained in a local LAPIC controller, for a given core in a given cluster.
     147 1. It translate each EXT_IRQ identified by its '''irq_id''' to a write transactions to a specific mailbox contained in a local LAPIC controller, for a given core in a given cluster.
    148148 1. It allows the kernel to selectively enable/disable any external IRQ identified by its '''irq_id''' index.
    149149
     
    155155The actual numbers of events of each type supported by a given XCU component are defined in the XCU_CONFIG register of the XCU component, and cannot be larger than the SOCLIB_MAX_HWI, SOCLIB_MAX_WTI, SOCLIB_MAX_PTI constants defined in the '' soclib_pic.h'' file.
    156156
    157 ===  X86_64 architecture ===
     157===  2. X86_64 architecture ===
    158158
    159159