Changes between Version 3 and Version 4 of wti_box_attribution
- Timestamp:
- Aug 1, 2016, 4:06:48 PM (8 years ago)
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wti_box_attribution
v3 v4 31 31 32 32 == External peripheral's I/O operation progress == 33 Each external peripheral is protected by a global lock, to execute an I/O operation with one of this peripheral we firstly have to the lock.33 Each external peripheral is protected by a global lock, to execute an I/O operation with one of this peripheral we firstly have to get the lock. 34 34 35 We decided that before to take the peripheral's lock the core should assure that it got a mailbox. Indeed, it is easier to get a mailbox because the y are 12 by cluster. Moreover, they are shared only by the cores of the same cluster. //A contrario//, the peripheral are unique so all the architecture's corecompete for their access.35 We decided that before to take the peripheral's lock the core should assure that it got a mailbox. Indeed, it is easier to get a mailbox because there are 12 by cluster. Moreover, they are shared only by the cores of the same cluster. //A contrario//, the peripheral are unique so all the architecture's cores compete for their access. 36 36 37 37 Once the mailbox and the lock got we have to configure the Iopic 38 38 39 After the interrupt ion's reception the peripheral's lock and the mailbox will be released.39 After the interrupt's reception the peripheral's lock and the mailbox will be released. 40 40 41 Moreover, the Iopic will be un-configure , that is if the peripheral sends an interrup it will bein a special mailbox : `DEV_NULL`.41 Moreover, the Iopic will be un-configured, that is if the peripheral sends an interrupt it will be received in a special mailbox : `DEV_NULL`. 42 42 43 43 The `DEV_NULL` mailbox is the first free mailbox of the cluster 0's Xicu, its ISR is executed by the core 0 of this cluster. 44 44 45 The ISR linked to this specific mailbox only prints a error message which points that an unwanted interrupt was received. This mec anism was implemented to protect the operation system against peripheral's potential dysfunction.45 The ISR linked to this specific mailbox only prints a error message which points that an unwanted interrupt was received. This mechanism was implemented to protect the operation system against peripheral's potential dysfunction. 46 46 47 47 In the first figure, the core P1 begins an I/O operation with the disk. In addition to configure the disk, the core also configures the IOPIC so that the disk can write in the local Xicu's fifth mailbox. 48 48 49 When the disk will end its I/O operation, it will ord oer the IOPIC to write in the fifth mailboxso the core P1 will execute the disk's ISR.49 When the disk will end its I/O operation, it will order the IOPIC to write in the fifth mailbox of the local Xicu so the core P1 will execute the disk's ISR. 50 50 51 51 == Mailboxes' attribution API == 52 To set up this mec anism we wrote anPI, it is composed of a structure and 3 functions.52 To set up this mechanism we wrote an API, it is composed of a structure and 3 functions. 53 53 54 54 The two main functions of this API are `get_configure_mailbox` and `put_mailbox`. Indeed, they can be used for future drivers' writing. … … 59 59 * an array of mailboxes' state 60 60 61 Each entry 62 Chaque case du tableau represents the mailbox's state, those different states are : 61 Each entry represents the mailbox's state, those different states are : 63 62 * IPI : The box is used for IPI, it can not be used for WTI. The ''n'' first mailboxes are reserved for IPI (''n'' is the cluster's number of core). 64 63 * FREE : The box is free an can be used for WTI. 65 * The id of proprietary core.64 * The id of the proprietary core. 66 65 67 66 === `void mbox_m_init(struct mbox_manager *mbox_m)` === … … 70 69 === `void get_configure_mailbox(struct mbox_manager *mbox_m, struct device_s *dev)` === 71 70 This function allocate a mailbox of the mbox_manager `mbox_m` to the device `dev`, then it configures the Xicu's mask and link the `dev`'s ISR to the allocated mailbox. 72 This functions blocks while no box ewas found.71 This functions blocks while no box was found. 73 72 74 73 === `int put_mailbox(uint_t wti_index, struct mbox_manager *mbox_m)` === … … 77 76 78 77 == API's advantages and disadvantages == 79 The use of this API permits a certain flexibility. Indeed, thanks to this API it will be possible to use all the peripheral even if we have an Xicu with only one mailbox (of course the different cores will have to shared the mailbox so il will have sequentiality).78 The use of this API permits a certain flexibility. Indeed, thanks to this API it will be possible to use all the peripherals even if we have an Xicu with only one mailbox (of course the different cores will have to shared the mailbox so there will be sequentiality). 80 79 81 80 Thanks to "polluter-payer" politic the cores' caches are not spoiled by the ISR of a neighbour core.
