source: anr/coach_objectifs.txt

Embedded systems (SoC and MPSoC) became an inevitable evolution in the microelectronic industry.  Due to the exploding fabrication costs, the ASIC technology (Application Specific Integrated Circuit) is not an option for SMEs (Small and Medium Enterprises).  Fortunately, the new FPGA (Field Programmable Gate Array) components, such as the Virtex5 family from \xilinx, or the Stratix4 family from \altera can implement a complete multi-processor architecture on a single device.  But the design of embedded system is a long and complex task that requires expertise in software, software/hardware partionning, operating system, hardware design, VHDL/Verilog modeling. Only very few SMEs have these multiple expertises and are present on the embedded system market.

The major objective of COACH is to provide to SMEs an open-source framework to design embedded systems on FPGA devices. This framework will be dedicated to system-level designer.

The second objective of COACH is HPC.  In HPC (High Performance Computing), the targeted application is running on a PC. The COACH framework will help the system designer to accelerate an HPC applcation by migrating critical parts into a SoC embedded into an FPGA device plugged to the PC PCI/X bus.  This will allow SMEs to enter HPC market for applications that cannot be accelerated by he current GPU based solutions.

To reach these objectives, the key scientific and technical issues are :

1) Design Space Exploration by Virtual Prototyping

The COACH environment will allow to easily map a parallel application (described as an abstract process network Model of Computation) on a shared-memory, MPSoC architecture.  COACH will permit the system designer to explore the design space, and to define the best hardware/software partitioning of the application.

2) Integration of system-level modeling and HLS tools

COACH will support the automated generation of hardware accelerators when required by using High-Level Synthesis (HLS) tools. These HLS tools will be fully integrated into the system-level design environment.  Moreover, COACH will support both data and control dominated applications, and the HLS tools of COACH will support a common language and coding style to avoid re-engineering by the designer.

3) High-level code transformation

COACH will allow to optimize the memory usage, to enhance the parallelism through loop transformations and parallelization. The challenge is to identify the coarse grained parallelism and to generate, from a sequential algorithm, applications containing multiple communicating tasks. Coach will adapt techniques which were developed in the 1990 for the construction of distributed programs. However, in the context of HLS, there are several original problems to be solved, related to the  FIFO communication channels and with memory optimization.  COACH will support code transformation by providing a source to source C2C tool.

4) Unified Hardware/Software communication middleware

COACH will rely on he SoCLib experience to implement an unified hardware/software communication infrastructure and communication APIs (Application Programming Interface), to support  communications between software tasks running on embedded processors and dedicated hardware coprocessors. The main issue here is to support easy migration
from a software implementation to an hardware implementation. 

5) Processor customization

ASIP (Application Specific Instruction Processor) design will be addressed by the COACH project. COACH will allow system designers to explore the various level of interactions between the original CPU micro-architecture and its extension. It will also allow to retarget the compiler instruction-selection pass. Finally, COACH will integrate ASIP synthesis in a complete System-level design framework.