Changeset 21


Ignore:
Timestamp:
Dec 31, 2009, 8:27:21 AM (14 years ago)
Author:
coach
Message:
 
Location:
anr
Files:
4 added
2 deleted
8 edited

Legend:

Unmodified
Added
Removed

  • anr/Makefile

    r14 r21  
    66                        section-4.1.tex \
    77                        architecture-csg.pdf architecture-hls.pdf architecture-hpc.pdf \
    8                         dependence-dev.pdf dependence-test.pdf \
     8                        dependence-task-h.pdf \
    99                        section-4.2.tex
    1010

  • anr/anr.tex

    r20 r21  
    1515\geometry{verbose,a4paper,tmargin=3cm,bmargin=2cm,lmargin=2cm,rmargin=3cm}
    1616
     17\usepackage{anr}
     18
    1719%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    1820\def\xcoach{\texttt{xcoach}\xspace}
     21\def\xcoachplus{\texttt{xcoach+}\xspace}
    1922\def\backbone{backbone\xspace}
    2023
    … …  
    2629\definecolor{rouge}{rgb}{1.0,0.2,0.2}
    2730\def\mustbecompleted#1{}
     31
     32%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     33\def\coussy{Philippe Coussy\xspace}
     34\def\irisa{IRI\xspace}
     35\def\citi{CITI\xspace}
     36\def\lip{LIP\xspace}
     37\def\tima{TIMA\xspace}
     38\def\ubs{UBS\xspace}    % LAB-STICC
     39\def\upmc{LIP6\xspace}
     40\def\bull{BULL\xspace}
     41\def\thales{THALES\xspace}
     42\def\zied{ZIED\xspace}
     43
     44\def\alllabs{\irisa \citi \lip \tima \ubs \upmc}
     45\def\allcompagnies{\bull \thales \zied\xspace}
     46
     47%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     48\def\ST{sub-task\xspace}
     49% FIXME \def\taskresponsable#1#2#3{\ifvmode\else\\\fi
     50% FIXME The coordinator of this task is #1 member of #2.
     51% FIXME The partners collaborating in this task are #3.\\}
    2852
    2953%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    … …  
    174198\end{itemize}}
    175199
    176 \subsubsection{Task 1}
     200\subsubsection{Task 0}
    177201%\input{task-0}
    178202
    179 \subsubsection{Task 2}
     203\subsubsection{Task 1: \textit{\backbone}}
    180204\input{task-1}
    181 
    182205
    183206\subsection{Tasks schedule, deliverables and milestones}

  • anr/architecture-csg.fig

    r12 r21  
    1 #FIG 3.2  Produced by xfig version 3.2.5-alpha5
     1#FIG 3.2  Produced by xfig version 3.2.5
    22Landscape
    33Center
    … …  
    13136 4397 1798 4861 2262
    14141 4 0 2 0 7 50 -1 -1 0.000 1 0.0000 4629 2030 217 217 4412 2030 4846 2030
    15 4 0 0 50 -1 2 12 0.0000 4 135 225 4515 2099 T0\001
     154 0 0 50 -1 2 12 0.0000 4 150 240 4515 2099 T0\001
    1616-6
    17176 4217 2372 5192 2732
    … …  
    28282 4 0 2 0 7 50 -1 -1 0.000 0 0 7 0 0 5
    2929         5507 2792 3907 2792 3907 1141 5507 1141 5507 2792
    30 4 0 0 50 -1 2 12 0.0000 4 135 225 4139 1498 T1\001
    31 4 0 0 50 -1 2 12 0.0000 4 135 225 5068 1498 T2\001
     304 0 0 50 -1 2 12 0.0000 4 150 240 4139 1498 T1\001
     314 0 0 50 -1 2 12 0.0000 4 150 240 5068 1498 T2\001
    3232-6
    33336 1359 1177 3159 2752
    34342 4 0 2 0 7 50 -1 -1 6.000 0 0 7 0 0 5
    3535         2934 2527 2934 1402 1584 1402 1584 2527 2934 2527
    36 4 1 0 50 -1 2 14 0.0000 4 165 705 2259 1852 initilal\001
     364 1 0 50 -1 2 14 0.0000 4 165 720 2259 1852 initilal\001
    37374 1 0 50 -1 2 14 0.0000 4 225 1185 2259 2152 application\001
    3838-6
    39396 3945 135 5505 890
    40 4 1 0 50 -1 2 14 0.0000 4 165 1305 4725 300 architecture\001
    41 4 1 0 50 -1 2 14 0.0000 4 210 1110 4725 470 parameter\001
     404 1 0 50 -1 2 14 0.0000 4 165 1275 4725 300 architecture\001
     414 1 0 50 -1 2 14 0.0000 4 225 1080 4725 470 parameter\001
    42424 1 0 50 -1 2 14 0.0000 4 120 135 4715 640 +\001
    43 4 1 0 50 -1 2 14 0.0000 4 240 1560 4725 830 hw/sw mapping\001
    44 -6
    45 6 7215 2150 8550 3080
    46 2 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
    47          7230 2165 8535 2165 8535 3065 7230 3065 7230 2165
    48 4 1 0 50 -1 2 14 0.0000 4 165 855 7905 2435 harware\001
    49 4 1 0 50 -1 2 14 0.0000 4 210 1170 7905 2690 component\001
    50 4 1 0 50 -1 2 14 0.0000 4 165 900 7890 2960 libraries\001
     434 1 0 50 -1 2 14 0.0000 4 225 1650 4725 830 hw/sw mapping\001
    5144-6
    52456 6255 3275 7905 4205
    53462 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
    5447         6270 3290 7890 3290 7890 4190 6270 4190 6270 3290
    55 4 1 0 50 -1 2 14 0.0000 4 165 1305 7080 3560 architecture\001
    56 4 1 0 50 -1 2 14 0.0000 4 225 960 7080 3815 template\001
     484 1 0 50 -1 2 14 0.0000 4 165 1275 7080 3560 architecture\001
     494 1 0 50 -1 2 14 0.0000 4 225 915 7080 3815 template\001
    57504 1 0 50 -1 2 14 0.0000 4 225 735 7125 4085 library\001
    5851-6
    … …  
    6154         6540 1085 7880 1085 7880 1565 6540 1565 6540 1085
    62554 1 0 50 -1 2 16 0.0000 4 195 585 7220 1415 CSG\001
    63 -6
    64 6 5850 2150 6795 3095
    65 2 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
    66          5865 2165 6780 2165 6780 3080 5865 3080 5865 2165
    67 4 1 0 50 -1 2 14 0.0000 4 165 600 6345 2435 micro\001
    68 4 1 0 50 -1 2 14 0.0000 4 165 705 6345 2690 kernel\001
    69 4 1 0 50 -1 2 14 0.0000 4 225 735 6330 2960 library\001
    7056-6
    71572 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
    … …  
    10591        0 0 2.00 120.00 240.00
    10692         9767 2310 9767 3210
    107 4 1 0 50 -1 2 14 0.0000 4 165 1020 9810 1445 bitstream\001
    108 4 1 0 50 -1 2 14 0.0000 4 165 645 9810 1205 FPGA\001
    109 4 1 0 50 -1 2 16 0.0000 4 195 570 7185 425 HLS\001
    110 4 1 0 50 -1 2 16 0.0000 4 195 135 7425 905 2\001
    111 4 1 0 50 -1 2 14 0.0000 4 120 990 9810 3470 measures\001
     932 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
     94         7230 2165 8535 2165 8535 3065 7230 3065 7230 2165
     952 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
     96         5865 2165 6780 2165 6780 3080 5865 3080 5865 2165
     974 1 0 50 -1 2 14 0.0000 4 165 1005 9810 1445 bitstream\001
     984 1 0 50 -1 2 14 0.0000 4 165 660 9810 1205 FPGA\001
    112994 1 0 50 -1 2 14 0.0000 4 165 1005 9795 2110 simulator\001
     1004 1 0 50 -1 2 14 0.0000 4 225 1140 7905 2690 component\001
     1014 1 0 50 -1 2 14 0.0000 4 165 885 7890 2960 libraries\001
     1024 1 0 50 -1 2 14 0.0000 4 165 1005 7905 2435 hardware\001
     1034 1 0 50 -1 2 14 0.0000 4 165 315 6345 2565 OS\001
     1044 1 0 50 -1 2 14 0.0000 4 225 735 6330 2835 library\001
     1054 1 0 50 -1 2 14 0.0000 4 225 1320 9810 3470 performance\001
     1064 1 0 50 -1 2 14 0.0000 4 225 825 9810 3770 analysis\001
     1074 1 0 50 -1 2 16 0.0000 4 195 585 7185 425 HAS\001

  • anr/architecture-hls.fig

    r12 r21  
    1 #FIG 3.2  Produced by xfig version 3.2.5-alpha5
     1#FIG 3.2  Produced by xfig version 3.2.5
    22Landscape
    33Center
    … …  
    1818-6
    1919-6
    20 6 6550 225 9715 1575
    21 6 8140 225 9715 1575
    22 6 8583 645 9318 1170
    23 4 1 0 50 -1 2 14 0.0000 4 225 735 8950 1110 library\001
    24 4 1 0 50 -1 2 14 0.0000 4 165 420 8950 810 cell\001
     206 4680 -855 6120 -270
     212 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
     22         4725 -810 6075 -810 6075 -315 4725 -315 4725 -810
     234 0 0 50 -1 2 14 0.0000 4 165 990 4857 -480 front-end\001
     24-6
     256 4905 405 5895 1395
     262 4 1 2 0 7 50 -1 -1 6.000 0 0 7 0 0 5
     27         5847 1350 5847 450 4947 450 4947 1350 5847 1350
     284 1 0 50 -1 2 14 0.0000 4 165 705 5397 945 xcoach\001
     29-6
     306 9617 1003 12792 1470
     312 1 0 2 0 7 50 -1 -1 0.000 0 0 7 1 0 2
     32        0 0 2.00 120.00 240.00
     33         9632 1165 10302 1165
     342 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
     35        0 0 2.00 120.00 240.00
     36         10747 1175 11377 1175
     372 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
     38         10300 1018 10750 1018 10750 1243 10300 1243 10300 1018
     394 0 0 50 -1 2 16 0.0000 4 225 1335 11457 1410 component\001
     404 0 0 50 -1 2 16 0.0000 4 195 825 11427 1225 VHDL\001
     41-6
     426 6435 -1140 8010 210
     436 6878 -720 7613 -195
     444 1 0 50 -1 2 14 0.0000 4 225 735 7245 -255 library\001
     454 1 0 50 -1 2 14 0.0000 4 165 360 7245 -555 cell\001
    2546-6
    26472 4 1 2 0 7 50 -1 -1 6.000 0 0 7 0 0 5
    27          9490 1350 9490 450 8365 450 8365 1350 9490 1350
    28 -6
    29 2 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
    30          7240 540 7690 540 7690 765 7240 765 7240 540
    31 2 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
    32          7240 990 7690 990 7690 1215 7240 1215 7240 990
    33 2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
    34         0 0 2.00 120.00 240.00
    35          8365 765 7690 630
    36 2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
    37         0 0 2.00 120.00 240.00
    38          8320 990 7690 1125
    39 2 1 0 2 0 7 50 -1 -1 6.000 0 0 7 1 1 2
    40         0 0 2.00 120.00 240.00
    41         0 0 2.00 120.00 240.00
    42          6565 1080 7240 1080
    43 2 1 0 2 0 7 50 -1 -1 6.000 0 0 7 1 1 2
    44         0 0 2.00 120.00 240.00
    45         0 0 2.00 120.00 240.00
    46          6565 630 7240 630
    47 -6
    48 6 7150 1755 7690 2970
    49 2 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
    50          7195 1800 7645 1800 7645 2025 7195 2025 7195 1800
    51 2 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
    52          7195 2250 7645 2250 7645 2475 7195 2475 7195 2250
    53 2 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
    54          7195 2700 7645 2700 7645 2925 7195 2925 7195 2700
    55 -6
    56 6 7150 -1170 7690 45
    57 2 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
    58          7195 -1125 7645 -1125 7645 -900 7195 -900 7195 -1125
    59 2 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
    60          7195 -675 7645 -675 7645 -450 7195 -450 7195 -675
    61 2 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
    62          7195 -225 7645 -225 7645 0 7195 0 7195 -225
     48         7785 -15 7785 -915 6660 -915 6660 -15 7785 -15
    6349-6
    64502 2 0 2 0 7 50 -1 -1 6.000 0 0 7 0 0 5
    … …  
    71572 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
    7258        0 0 2.00 120.00 240.00
    73          4252 1262 4932 802
    74 2 1 1 2 0 7 50 -1 -1 6.000 0 0 7 0 0 2
    75          4947 900 5847 900
    76 2 4 1 2 0 7 50 -1 -1 6.000 0 0 7 0 0 5
    77          5847 1350 5847 450 4947 450 4947 1350 5847 1350
    78 2 1 2 2 0 7 50 -1 -1 4.500 0 0 -1 0 0 2
    79          4947 225 8275 225
    80 2 1 2 2 0 7 50 -1 -1 4.500 0 0 7 0 0 2
    81          4947 1575 9565 1577
    82 2 1 2 2 0 7 50 -1 -1 4.500 0 0 7 0 0 3
    83          8320 225 8320 0 9445 0
    84 2 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 2
    85          6527 -1028 6527 2802
     59         4252 1262 4905 900
    86602 1 0 2 0 7 50 -1 -1 6.000 0 0 7 1 1 2
    8761        0 0 2.00 120.00 240.00
    8862        0 0 2.00 120.00 240.00
    89          6527 2802 7197 2802
    90 2 1 0 2 0 7 50 -1 -1 6.000 0 0 7 1 1 2
    91         0 0 2.00 120.00 240.00
    92         0 0 2.00 120.00 240.00
    93          6527 2352 7197 2352
    94 2 1 0 2 0 7 50 -1 -1 6.000 0 0 7 1 1 2
    95         0 0 2.00 120.00 240.00
    96         0 0 2.00 120.00 240.00
    97          6527 1912 7197 1912
    98 2 1 0 2 0 7 50 -1 -1 6.000 0 0 7 1 1 2
    99         0 0 2.00 120.00 240.00
    100         0 0 2.00 120.00 240.00
    101          6527 -108 7197 -108
    102 2 1 0 2 0 7 50 -1 -1 6.000 0 0 7 1 1 2
    103         0 0 2.00 120.00 240.00
    104         0 0 2.00 120.00 240.00
    105          6527 -558 7187 -548
    106 2 1 0 2 0 7 50 -1 -1 6.000 0 0 7 1 1 2
    107         0 0 2.00 120.00 240.00
    108         0 0 2.00 120.00 240.00
    109          6527 -1008 7197 -1008
    110 2 1 0 2 0 7 50 -1 -1 6.000 0 0 7 1 1 2
    111         0 0 2.00 120.00 240.00
     63         5355 -358 5355 450
     642 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
     65         6660 540 7875 540 7875 1170 6660 1170 6660 540
     662 1 0 2 0 7 50 -1 -1 0.000 0 0 7 1 0 2
    11267        0 0 2.00 120.00 240.00
    11368         5847 900 6565 900
     692 1 0 2 0 7 50 -1 -1 0.000 0 0 7 1 0 2
     70        0 0 2.00 120.00 240.00
     71         7872 900 8590 900
     722 4 1 2 0 7 50 -1 -1 6.000 0 0 7 0 0 5
     73         9585 1395 9585 450 8550 450 8550 1395 9585 1395
    114742 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
    11575        0 0 2.00 120.00 240.00
    116          7662 1932 8292 1932
     76         10747 652 11377 652
     772 1 0 2 0 7 50 -1 -1 0.000 0 0 7 1 0 2
     78        0 0 2.00 120.00 240.00
     79         9632 642 10302 642
     802 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
     81         10260 495 10710 495 10710 720 10260 720 10260 495
    117822 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
    11883        0 0 2.00 120.00 240.00
    119          7642 2362 8272 2362
     84         10767 1662 11397 1662
     852 2 1 2 0 7 50 -1 -1 6.000 0 0 -1 0 0 5
     86         10300 1530 10750 1530 10750 1755 10300 1755 10300 1530
     872 1 0 2 0 7 50 -1 -1 0.000 0 0 7 1 0 2
     88        0 0 2.00 120.00 240.00
     89         5475 1635 10302 1642
     902 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
     91         5505 1620 5505 1350
     922 1 0 2 0 7 50 -1 -1 0.000 0 0 -1 0 0 2
     93         9045 1395 9045 1650
    120942 1 0 2 0 7 50 -1 -1 6.000 0 0 -1 1 0 2
    12195        0 0 2.00 120.00 240.00
    122          7642 2812 8272 2812
    123 4 1 0 50 -1 2 14 0.0000 4 165 735 3690 1125 xcoach\001
     96         7249 -8 7245 540
     974 1 0 50 -1 2 14 0.0000 4 165 705 3690 1125 xcoach\001
    124984 1 0 50 -1 2 14 0.0000 4 165 645 3690 1425 driver\001
    125 4 1 0 50 -1 2 14 0.0000 4 180 360 3690 630 gcc\001
    126 4 1 0 50 -1 2 14 0.0000 4 165 735 5397 735 xcoach\001
    127 4 1 0 50 -1 2 16 0.0000 4 150 165 5382 1215 +\001
    128 4 0 0 50 -1 2 14 0.0000 4 165 1005 5082 -480 front-end\001
    129 4 0 0 50 -1 2 14 0.0000 4 165 750 5127 2430 drivers\001
    130 4 0 0 50 -1 2 14 0.0000 4 165 975 8480 275 back-end\001
    131 4 0 0 50 -1 2 16 0.0000 4 225 1335 8352 3047 component\001
    132 4 0 0 50 -1 2 16 0.0000 4 195 825 8322 2862 VHDL\001
    133 4 0 0 50 -1 2 16 0.0000 4 255 1065 8292 2312 SystemC\001
    134 4 0 0 50 -1 2 16 0.0000 4 195 735 8312 2537 model\001
    135 4 0 0 50 -1 2 16 0.0000 4 195 990 8322 2032 C model\001
     994 1 0 50 -1 2 14 0.0000 4 180 330 3690 630 gcc\001
     1004 1 0 50 -1 2 14 0.0000 4 165 840 9042 945 xcoach+\001
     1014 0 0 50 -1 2 16 0.0000 4 255 1065 11397 602 SystemC\001
     1024 0 0 50 -1 2 16 0.0000 4 195 735 11417 827 model\001
     1034 0 0 50 -1 2 16 0.0000 4 195 990 11427 1762 C model\001
     1044 0 0 50 -1 2 14 0.0000 4 165 945 6795 945 back-end\001

  • anr/architecture-hpc.fig

    r12 r21  
    1 #FIG 3.2  Produced by xfig version 3.2.5-alpha5
     1#FIG 3.2  Produced by xfig version 3.2.5
    22Landscape
    33Center
    … …  
    991200 2
    10106 3375 1485 4725 2160
    11 4 1 0 50 -1 2 14 0.0000 4 165 1140 4050 1710 FPGA SoC\001
    12 4 1 0 50 -1 2 14 0.0000 4 210 450 4050 2010 part\001
     114 1 0 50 -1 2 14 0.0000 4 165 1155 4050 1710 FPGA SoC\001
     124 1 0 50 -1 2 14 0.0000 4 225 450 4050 2010 part\001
    1313-6
    14146 3825 -90 4275 585
    15154 1 0 50 -1 2 14 0.0000 4 165 315 4050 135 PC\001
    16 4 1 0 50 -1 2 14 0.0000 4 210 450 4050 435 part\001
     164 1 0 50 -1 2 14 0.0000 4 225 450 4050 435 part\001
    1717-6
    18186 5580 1530 7020 2070
    19 4 1 0 50 -1 2 14 0.0000 4 165 1395 6300 1710 comunication\001
     194 1 0 50 -1 2 14 0.0000 4 165 1410 6300 1710 comunication\001
    20204 1 0 50 -1 2 14 0.0000 4 225 735 6300 2010 library\001
    2121-6
    … …  
    23232 4 0 2 0 7 50 -1 -1 6.000 0 0 7 0 0 5
    2424         2250 1575 2250 450 900 450 900 1575 2250 1575
    25 4 1 0 50 -1 2 14 0.0000 4 165 705 1575 900 initilal\001
     254 1 0 50 -1 2 14 0.0000 4 165 720 1575 900 initilal\001
    26264 1 0 50 -1 2 14 0.0000 4 225 1185 1575 1200 application\001
    2727-6
    … …  
    7373        0 0 2.00 120.00 240.00
    7474         8432 470 8432 1370
    75 4 1 0 50 -1 2 14 0.0000 4 225 945 6300 360 compiler\001
     754 1 0 50 -1 2 14 0.0000 4 225 915 6300 360 compiler\001
    76764 1 0 50 -1 2 14 0.0000 4 165 165 6300 90 C\001
    77 4 1 0 50 -1 2 14 0.0000 4 165 1155 8460 270 executable\001
    78774 1 0 50 -1 2 16 0.0000 4 195 135 2925 1125 1\001
    79784 1 0 50 -1 2 16 0.0000 4 195 135 4050 1125 2\001
    80 4 1 0 50 -1 2 14 0.0000 4 120 990 8475 1630 measures\001
    81794 1 0 50 -1 2 16 0.0000 4 195 135 8655 900 3\001
     804 1 0 50 -1 2 14 0.0000 4 225 825 8505 1920 analysis\001
     814 1 0 50 -1 2 14 0.0000 4 225 1320 8505 1620 performance\001
     824 1 0 50 -1 2 14 0.0000 4 165 1005 8460 270 simulator\001

  • anr/section-1.tex

    r16 r21  
    11% les objectifs globaux,
    2 An embedded system is an application integrated into one or several chips
    3 in order to accelerate it or to embedd it into a small device such as a
    4 personal digital assistant (PDA). This topic is investigated since 80s
    5 using Applications Specific Integrated Circuits (ASIC), Digital Signal
    6 Processing (DSP) and parallel computing on multiprocessor machines or
    7 networks.  More recently, since end of 90s, other technologies appeared
    8 like Very Large Instruction Word (VLIW), Application Specific Instruction
    9 Processors (ASIP), System on Chip (SoC), Multi-Processors SoC (MPSoC).
     2A digital system is an application integrated into one or several chips.
     3These chips can be embedded in devices such as a personal digital assistant
     4(PDA), ambiant computing component, wireless sensor network (WSN). They can
     5also be used on a board connected to a PC to accelerate an application like
     6in High-Performance Computing (HPC) and in High-Speed Signal Processing (HSSP).
     7Digital system design has  been investigated since eighties by using Applications
     8Specific Integrated Circuits (ASIC), Digital Signal Processing (DSP) and parallel computing on
     9multiprocessor machines or networks.  More recently, since the end of nineties,
     10other technologies appeared like Very Large Instruction Word (VLIW), Application
     11Specific Instruction Processors (ASIP), System on Chip (SoC), Multi-Processors
     12SoC (MPSoC).
    1013\\
    11 During these last decades embedded system was reserved to major industrial
    12 companies targeting high volume market due to the design and fabrication
    13 costs.
     14During these last decades, digital systems are more and more reserved
     15to major companies targeting high volume market due to the design and fabrication
     16costs of ASIC technologies due to increasing NRE (Non Recurring-Engineering) charges.
    1417Nowadays Field Programmable Gate Arrays (FPGA), like Virtex5 from Xilinx
    15 and Stratix4 from Altera, can implement a SoC with multiple processors and
    16 several coprocessors for less than 10K euros per item.
    17 In addition, High Level Synthesis (HLS) becomes more mature and allows to
     18and Stratix4 from Altera, can implement a complete SoC with multiple processors and
     19several coprocessors for less than 10K euros per device.
     20In addition, Electronic System Level (ESL) design methodologies (Virtual Prototyping,
     21Co-design, High-Level Synthesis...) become mature and allow to
    1822automate design and to drastically decrease its cost in terms of man power.
    19 Thus, both FPGA and HLS tend to spread over HPC for small companies
    20 targeting low volume markets.
     23Thus, coupling both FPGA and ESL methodologies will soon allow small and medium
     24enterprises (SMEs) to get into new and low-volume markets, to design highly innovative devices,
     25to prototype complete complex embedded systems, to realize HPC or HSSP applications.
    2126\par
    22 To get an efficient embedded system, designer has to take into account
    23 application characteristics when it chooses one of the former technologies.
    24 This choice is not easy and in most cases designer has to try different
    25 technologies to retain the most adapted one.
    26 \\
    27 The first objective of COACH is to provide a framework to
    28 design embedded system on FPGA device.
    29 COACH framework allows designer to explore various software/hardware
    30 partitions of the target application, to run timing and functional
     27The objective of COACH is to provide an environment to design emmbedded systems and
     28HPC applications on FPGA devices. The COACH framework will allow designer to explore various
     29software/hardware partitioning scenario of the target application through timing and functional
    3130simulations and to generate automatically both the software and the
    32 synthesizable description of the hardware.
    33 The main topics of the project are:
     31synthesizable description of the hardware. Exploration and design are mainly
     32driven by throughput, latency and/or power consumption criteria.
     33The main contributions of the project are:
    3434\begin{itemize}
    35 \item Design space exploration: It consists in analysing the application
    36 runnig on FPGA, defining the target technology (SoC, MPSoC, ASIP, ...) and
    37 hardware/software partitioning of tasks depending on technology choice.
    38 This exploration is driven basically by throughput, latency and power
    39 consumption criteria.
    40 \item Micro-architectural exploration: When hardware components are
    41 required, the HLS tools of the framework generate them automatically. At
    42 this stage the framework provides various HLS tools allowing the
    43 micro-architectural space design exploration. The exploration criteria are
    44 also throughput, latency and power consumption.
    45 % FIXME
    46 %CA At this stage, preliminary source-level transformations will be
    47 %CA required to improve the efficiency of the target component.
    48 %CA COACH will also provide such facilities, such as automatic parallelization
    49 %CA and memory optimisation.
    50 \item Performance measurement: For each point of design space exploration,
    51 metrics of criteria are available such as throughput, latency, power
    52 consumption, area, memory allocation and data locality.
    53 They are evaluated using virtual prototyping, estimation or analysing
    54 methodologies.
    55 \item Targeted hardware technology: The COACH description of system is
    56 independent of the FPGA family.
    57 Every point of the design exploration space can be implemented on any FPGA
    58 having the required resources.
    59 Basically, COACH handles both Altera and Xilinx FPGA families and supports
    60 3 generic target architectures:
    61 the COACH architecture based on the MIPS of the TSAR ANR project and a VCI ring bus,
    62 the Altera architecture based on the NIOS and AVALON bus,
    63 the Xilinx architecture based on the MICROBLAZE and OPB bus.
     35\item Targeted hardware architecture and technology:
     36COACH will handle both Altera and Xilinx FPGA technologies. COACH will define
     37architectural templates that can be customized by additional dedicated coprocessors and ASIPs.
     38The parameters of the architectural templates will be the number of CPU, the operating  system... 
     39%the coprocessors, the number and the size of the FIFO communication channels
     40Basically, the 3 following architectural templates will be provided:
     41A COACH architectural template based on the MIPS of the TSAR ANR project and a VCI ring bus,
     42An Altera architectural template based on the NIOS and the AVALON bus,
     43%FIXME
     44% The following point has to be confirmed by XILINX
     45% Microblaze+OPB => ARM+Amba ???
     46A Xilinx architectural template based on the MICROBLAZE and the OPB bus.
     47Moreover, the specification of the application will be independant of both the template
     48architecture and the selected technology.
     49\item Design space exploration: The COACH environment will allow to select and parametrize
     50the target architecture, to define hardware/software partitioning and to profile the application.
     51For each point of design space exploration, metrics such as throughput, latency, power consumption,
     52area, memory allocation and data locality will be provided.
     53This criteria will be evaluated by using virtual prototyping and high-level estimation methodologies.
     54\item Hardware accelerators synthesis (HAS): COACH will allow to generate automatically hardware accelerators
     55when required. Hence, High-Level Synthesis (HLS) tools, ASIP design environement and
     56source-level transformations (loop transformations and memory optimisation) will be provided.
     57This will allow to further explore the micro-architectural design space.
    6458\end{itemize}
    65 As an extension of embedded system design, COACH deals also with High
    66 Performance Computing (HPC).
    67 In HPC, the kind of targeted application is an existing one running on PC.
    68 COACH helps designer to accelerate it by migrating critical parts into a
    69 SoC implemented on a FPGA plugged to the PC bus.\\
    70 Finally COACH will be developped under the General Public Licence for the software,
    71 and USAGE LIBRE NON COMMERCIAL for the COACH architecture.
     59%In HPC, the kind of targeted application is an existing one running on PC.
     60%COACH helps designer to accelerate it by migrating critical parts into a
     61%SoC implemented on a FPGA plugged to the PC bus.\\
     62%FIXME licence a speficier
     63The COACH environment will be designed to abstract the hardware as much as possible to the end user.
     64It will thus be mainly dedicated to system designers.
     65Finally COACH will be developped under the General Public Licence for the software tools.
     66and USAGE LIBRE NON COMMERCIAL for the COACH arhitecture.
     67%The COACH architectural templates will be freely distributed.
    7268%
    7369% verrous scientifiques et techniques
    7470\mbox{}\vspace*{.9ex}\par
    75 System design is a very complicated task and in this project we try to simplify it
    76 as much as possible. For this purpose we have to deal with the following scientific
    77 and technological barriers.
     71System design is a very complex task this project will simplify as much as possible.
     72For this purpose the following scientific and technological barriers will be addressed:
    7873\begin{itemize}
    79 \item The run frequency of the coprocessors generated by the HLS must respect
    80 accurately the system frequency given bt the processors and bus.
    81 \item HLS tools are sensitive to the style in which the algorithm is written
    82 and the domain they target. The HLS tools of COACH must have a common language
    83 and style to avoid engineering work to the designer.
    84 \item The main problem in HPC is in the communication between the PC and the SoC
    85 firstly at the efficiency level and secondly to eliminate enginnering effort to
    86 implement it.
     74\item The clock frequency of the coprocessors generated by the HLS must respect
     75the frequency of the processors and the system bus.
     76\item HLS tools are sensitive to the coding style of the input specification
     77and the domain they target (control vs. data dominated). The HLS tools of COACH must have a
     78common language and coding style to avoid engineering work to the designer.
     79\item The main problem in HPC comes from timing performance and implementation of the communication
     80between the PC and the FPGA.
     81%FIXME: a completer loop tranfrom?, ASIP?, ...
    8782\end{itemize}
    8883%
    … …  
    9186COACH is the result of the will of several laboratories to unify their know
    9287hows and skills in the following domains: Operating system and hardware
    93 communication (TIMA, SITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
    94 HLS (LIP6, Lab-STIC and LIP).
    95 So COACH does not starts from scratch but it relies
    96 on SocLib~\cite{soclib} with the MUTEX and DNA/OS operating system for
    97 system prototyping,
    98 on BEE~\cite{bee}, GAUT~\cite{gaut08}, ROMA~\cite{roma}, SYNTOL~\cite{syntol}
    99 and UGH~\cite{ugh08} for HLS.
    100 The project objective is to integrate and enhance these various tools into
    101 a unique free framework masking as much as possible these domains and its
    102 different tools to the system designer.  The main steps of this projects are:
    103 1) Definition of the designer input as set of communicating tasks, each
    104 task beeing described in C++ language.
    105 2) Definition of the xhls format, an internal format for representing a
    106 task.
    107 3) Developping a GCC addon for generating the xhls date from a C++ task
    108 description.
    109 4) Adapting the existing HLS tools to read and write xhls format and
    110 enhancing them. This allows to swap from one tool to the other and
    111 chain them.
    112 5) Modifying the Design System Explorator of SocLib to let the designer
    113 to explore the design space and then to generate the bitstream to
    114 the target FPGA.
     88communication (TIMA and CITI), SoC and MPSoC (LIP6 and TIMA), ASIP (IRISA) and
     89HLS (LIP6 and Lab-STICC)  and loop tranformations (LIP).
     90COACH does not start from scratch but relies
     91on the SocLib platform~\cite{soclib} with the MUTEX and DNA/OS operating system for
     92SoC and MPSoC prototyping, on GAUT~\cite{gaut08} and UGH~\cite{ugh08} for HLS, on
     93ROMA~\cite{roma} for ASIP, on SYNTOL~\cite{syntol} and BEE~\cite{bee} for loop tranformations.
     94The project objective is to enhance and seamlessly integrate these tools into
     95a unique open source framework.
     96%masking these domains and its different tools to the system designer.
     97The main steps of this project are:
     981) Definition of the user inputs: application description as set of communicating tasks, each
     99task beeing described in C++ language; architectural template with its parameters; design constraints.
     1002) Definition of the internal \xcoach format for representing a task.
     1013) Development of a GCC pluggin for generating the \xcoach representation of a C++ task.
     1024) Adaptation of the existing HLS tools to read and write the \xcoach format. This will allow to
     103swap from one tool to an other one and to chain them.
     1045) Modification of the Design System eXplorator DSX of the SocLib platform to let the user
     105explore the design space and then to generate the bitstream.
     106%FIXME : a completer
    115107\par
    116 The role of the industrials BUL, THALES, XXX, XXX is to provide real
    117 benchmark to guide the design of framework and prove that COACH is
     108The role of the industrial partners BULL, THALES, XXX is to provide real
     109benchmarks to guide the design of the framework and to prove that COACH is
    118110usuable and cover a large spectrum of applications.
    119111%
    120112% les retombées scientifiques, techniques et économiques
    121113\vspace*{.9ex}\par
    122 The main scientific contributions of the project are
    123 firstly to make high level synthesis an elementary tool of system design,
    124 seconly to unify various synthesis techniques (same input and output formats)
     114The main scientific contributions of the project are:
     115to make high-level synthesis an elementary tool of system design,
     116to unify various synthesis techniques (same input and output formats)
    125117allowing the designer to swap from one to an other and even to chain them
    126118without rewritting effort,
    127 and finally to provide a system description independent of the target
    128 architecture and the FPGA family.
     119to provide a system description independent of the target architecture and
     120the FPGA family.
    129121\par
    130122The market of embedded system and HPC is about 4,600 M\$ today and is
    … …  
    133125by major companies that can support the very high Non Recurring Engineering (NRE)
    134126costs involved in designing such system.
    135 Small companies can only be present in this market with GPUs based solutions that have
     127Small and medium companies can only be present in this market with GPUs based solutions that have
    136128low NRE costs but limit the application domains.\\
    137129COACH reduces the NRE costs to the design costs (the FPGA device being only a few
    … …  
    142134that will be able to propose embedded system and accelerating solutions for standard
    143135software applications with acceptable prices.\\
    144 The two major FPGA companies Altera and Xilinx expect thus by supporting
     136The two major FPGA companies Altera and Xilinx expect this by supporting
    145137and participating in this project.
    146138

  • anr/section-4.1.tex

    r12 r21  
    11\begin{figure}\leavevmode\center
    22\includegraphics[width=.8\linewidth]{architecture-csg}
    3 \caption{\label{archi-csg} software architecture for embedded system generation}
     3\caption{\label{archi-csg} software architecture for digital system generation}
    44%\end{figure}\begin{figure}\leavevmode\center
    55\mbox{}\vspace*{1ex}\\
    6 \includegraphics[width=.8\linewidth]{architecture-hls}
    7 \caption{\label{archi-hls} software architecture of HLS}
     6\includegraphics[width=1.0\linewidth]{architecture-hls}
     7\caption{\label{archi-hls} software architecture of hardware accellerator synthesis}
    88%\end{figure}\begin{figure}\leavevmode\center
    99\mbox{}\vspace*{1ex}\\
    … …  
    1515summarize the software architecture of COACH framework we plan to develop.
    1616In figures, the dotted boxes are the softwares or formats that COACH
    17 has to provide or define.
     17has to provide.
    1818\vspace*{.75ex}\par
    19 For the system genration presented figure~\ref{archi-csg}, the conductor is
    20 the program \verb!CSG! (COACH System Generator). Its inputs are a process
    21 network and miscellaneaous generation parameters.
    22 The main parameters are the template of the target hardware architecture
     19For the system genration presented in figure~\ref{archi-csg}, the conductor
     20is the tool \verb!CSG! (COACH System Generator). Its inputs are a process
     21network describing the application to design and the synthesis parameters.
     22The main parameters are the target hardware architectural template
    2323with its instanciation parameters, the hardware/software mapping of the
    24 tasks and the FPGA device.
    25 From these inputs \verb!CSG! can generate the system (software \& hardware) as
    26 a SystemC simulator to prototype and explore quickly the system design
    27 space and/or as a bitstream directly downloadable on the FPGA device.
    28 For processing, \verb+CSG+ requires 1) a hardware template found into the
    29 architecture library, 2) a micro-kernel, it chooses among
    30 two in the micro kernel library, 3) the system hardware components that
    31 are taken from the SystemC model library for the simulator and from the
    32 VHDL component library for the FPGA bitstream. 
    33 For generating the coprocessor of a task mapped as harware, \verb+CSG+
    34 controls the HLS tools described below.
     24tasks, the FPGA device and design constraints.
     25\verb+CSG+ thus requires an architectural template library, a operating system
     26library, two system hardware component (CPU, memories, BUS...) libraries
     27(one for synthesis, one for simulation).
     28For generating the coprocessor of a task mapped as hardware, \verb+CSG+
     29controls the HAS tools described below.
     30From these inputs \verb!CSG! can generate the entire system (both software \&
     31hardware) either as a SystemC simulator to prototype and explore quickly the
     32design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
     33launch the Xilinx or Altera RTL synthesis tools.} directly downloadable on the
     34FPGA device.
    3535\\
    36 To proove CSG that COACH is open and CSG is really configurable, COACH will
    37 basically support 3 architecture template (the COACH template based on a
    38 MIPS processors and a VCI token ring, the Altera template based on the NIOS
    39 and AVALON bus, the Xilinx template based on the MICROBLAZE and OPB bus)
    40 and 2 operating systems (DNA/OS and MUTEK). Furthermore, thus is enforced
    41 by the \mustbecompleted{FIXME:zied} contribution that consists in
    42 implementing an other hardware target.
    43 \\
    44 Finally, it is important to notice that this work is a strong
    45 enhancement of the SocLib software.
     36%To proove CSG that COACH is open and CSG is really configurable, COACH will
     37%basically support 3 architecture template (the COACH template based on a
     38%MIPS processors and a VCI token ring, the Altera template based on the NIOS
     39%and AVALON bus, the Xilinx template based on the MICROBLAZE and OPB bus)
     40%and 2 operating systems (DNA/OS and MUTEK). Furthermore, thus is enforced
     41%by the \mustbecompleted{FIXME:zied} contribution that consists in
     42%implementing an other hardware target.
     43%\\
     44%Finally, it is important to notice that this work is a strong
     45%enhancement of the SocLib software.
    4646\vspace*{.75ex}\par
    47 The software architecture for HLS is presented figure~\ref{archi-hls}.
    48 The input is a task of the process network. The HLS tools do not work
     47The software architecture for HAS is presented in figure~\ref{archi-hls}.
     48The input is a single task of the process network. The HAS tools do not work
    4949directly on the C++ task description but on an internal format called
    5050\xcoach generated by a the GNU C compiler (GCC) tainted by a COACH
    5151driver. This allows on the one hand to insure that all the tools will
    5252accept the same C++ description and on the other hand to make possible
    53 to chain them. The front-end tools read a \xcoach description and writes
    54 a new \xcoach description that exibits possible parallelism or implement
    55 specific instruction for ASIP. The back-end tools read a \xcoach
    56 description and generates a \xcoach+ description that is a \xcoach
    57 description anotated with hardware information to let work the VHDL systemC
    58 drivers. Furthermore, the back-end tools uses a macro-cell library.
     53their chaining. The front-end tools read a \xcoach description and generate
     54a new \xcoach description that exibits more parallelism or implement
     55specific instructions for ASIP. The back-end tools read a \xcoach
     56description and generate a \xcoachplus description. This is a \xcoach
     57description anotated with hardware information (scheduling, binding) required by
     58the VHDL and systemC drivers.
     59Furthermore, the back-end tools uses a macro-cell library (functional and memory
     60unit).
    5961\vspace*{.75ex}\par
    60 The software architecture for HPC is presented figure~\ref{archi-hpc}.
    61 \mustbecompleted{FIXME Miss HPC description\\\ldots\\\ldots\\\ldots\\\ldots.}
     62In addition to digital system design, HPC requires a supplementary
     63partitioning step presented in figure~\ref{archi-hpc}. The designer
     64splits the initial application (tag 1) in two parts: one still on the PC and the
     65other running in a FPGA plugged on the PCI/X PC bus. The two parts exchange data
     66through communication primitives (tag 2) implemented in a library.
     67To evaluate if the relevance of the partitioning, the designer can build a
     68simulator. Once the partitioning is validated, the design of the FPGA part
     69is done through \verb!CSG! (figure~\ref{archi-csg}).
    6270\vspace*{.75ex}\par
    6371The project is splitted into 8 tasks numbered from 0 to 7.
    … …  
    6573the dissemination the other task are listed below:
    6674\begin{enumerate}
    67 \item\textbf{\backbone:} This task groups the critical issues of the
    68         project. They consist of the definition of COACH inputs, the \xcoach
    69         format that is mandatory to develop the HLS tools and the HLS drivers
    70         that are mandatory for testing the HLS tools.
    71 \item\textbf{system generation:} This task groups \verb+CSG+s and the components
    72         required to generate the system simulator and bitstream except the HLS
    73         tools that belong to the task 3 and 4. These components are the
    74         operating systems, the VHDL description and SystemC models of the
    75         target hardware achitectures.
    76 \item\textbf{HLS front-end:} This task groups the 4 HLS front-head. Those
    77         are a tool that exhibits fine grain parallelism using polyedric
    78         transformation, a tool that exhibits coarse grain parallelism,
    79         a tool that minimizes the memory usage and a tool that implement ASIP.
    80 \item\textbf{HLS back-end:} This task groups two HLS back-end tool, one
    81         for treating the data oriented description, the second for treating the
    82         control dominated description. This task contains also a the
    83         development of a frequency adaptator that will allow the coprocessor
    84         to respect the processor \& bus frequency.
    85 \item\textbf{Communication software PC/FPGA-SoC:} This task groups all what is mandatorythe critical issues of the
    86 \item\textbf{Demonstrator:} This task groups the demostrators of the COACH project.
     75\item\textbf{\backbone:} This task tackles the fundamental points of the
     76        project such as the defintion of the COACH inputs and outputs,
     77    the internal formats (e.g. \xcoach), the architectural templates and
     78    the design flow.
     79\item\textbf{system generation:} This task addresses the prototyping and
     80    the generation of digital system. Apart from HAS that belong to the task 3
     81    and 4, its components are those presented figure~\ref{archi-csg}
     82    (e.g.  \verb!CSG!, operating systems).
     83\item\textbf{HAS front-end:} This task mainly focusses on four functionalities:
     84    optimization of the memory usage, parallelism enhancement through loop
     85    transformations, coarse grain parallelization and ASIP generation.
     86\item\textbf{HAS back-end:} This task groups two functionalities:
     87    High-Level Synthesis of data dominated description and HLS of control
     88    dominated description.
     89    This task contains also the development of a frequency adaptator
     90    that will allow the coprocessors to respect the processor \& the bus
     91    frequency.
     92\item\textbf{Communication between PC \& FPGA-SoC:}
     93    This task pools the features dedicated to HPC. The main are the
     94    partitioning validation (see figure~\ref{archi-hpc}, the sytem drivers for
     95    both PC and FPGA-SoC sides, the hardware communication components.
     96\item\textbf{Demonstrator:}
     97    This task groups the demostrators of the COACH project.
     98    \mustbecompleted{FIXME}
    8799\end{enumerate}
    88 This task division offers the avantage that tasks except for the "\backbone" and
    89 "demonstrator" task are almost independent at the development level as shown
    90 figure~\ref{dependence-dev}. The dependence at the validation level is
    91 presented figure~\ref{dependence-test}. It is more critical but the
    92 redundance in the tasks "HLS front-end", "HLS back-end" and "demonstrators"
    93 reduces this inter-dependence.\\
    94 So if the first phasis of "\backbone" task is sucessfully conduced, most of the
    95 projet delivrables will be carry through, even if some delivrable are lated
    96 or missing.
     100%
    97101\begin{figure}\leavevmode\center
    98 \begin{minipage}[t]{.4\linewidth}
    99 \includegraphics[width=1\linewidth]{dependence-dev}
    100 \caption{\label{dependence-dev}Dependence graph at development level}
    101 \end{minipage}\hfill\begin{minipage}[t]{.4\linewidth}
    102 \includegraphics[width=1\linewidth]{dependence-test}
    103 \caption{\label{dependence-test}Dependence graph at validation level}
    104 \end{minipage}
     102%\includegraphics[width=.4\linewidth]{dependence-task}
     103\includegraphics[width=0.70\linewidth]{dependence-task-h}
     104\caption{\label{dependence-task}Task dependencies}
    105105\end{figure}
     106Figure~\ref{dependence-task} presents the dependencies between the tasks.
     107"$task-N \longrightarrow task-M$" means that $task-N$ requires $task-M$
     108to work and be demonstrated. The more bold is the arrow, the more important is
     109the dependency.
     110The graph shows:
     111\begin{itemize}
     112\item Even that $T3$ and $T4$ functionalities are complementary, their
     113developments are independent (thanks to \xcoach internal format).
     114\item $T2$ depends slightly from $T3$ and $T4$. Indeed, $T2$ may works
     115without $T3$ and $T4$ if we limit to digital systems without hardware
     116accellerators.
     117\item $T5$  strongly depends on $T2$ but, $T2$ does not depend at all on
     118$T5$. So demonstrators ($T6$) of embedded system would not be impacted if
     119$T5$ would fail. 
     120\item $T1$ drives all the tasks ($T2$, $T3$, $T4$, $T5$) at the heart of
     121the COACH project.
     122\item $T7$ and $T0$ respectively depends on and impacts all the other tasks.
     123\end{itemize}
     124So this organisation offers enough robustness for insure the success of the
     125project except for the specification task $T1$. However, the partners meet
     12610 times (a one day meeting per month) during the last years to prepare the
     127specification and the project proposal.

  • anr/task-1.tex

    r12 r21  
     1%\def\TBresp{\coussy}
     2%\def\TBresplab{\labsticc}
     3%\def\TBpartner{\alllabs,\allcompagnies}
     4
     5\begin{taskinfo}
     6\let\UPMC\leader
     7\let\ALL\enable
     8\end{taskinfo}
     9%
     10\begin{objectif}
     11This task relies to the main features for embedded system.
     12Its objective consists of the specification of designer input, of the
     13definition of the hardware architectural templates and of all the features
     14that the HAS tools share.
     15\end{objectif}
     16%
     17\begin{workpackage}{T1}
     18\item This \ST specifies COACH for the system designer. At this
     19    level COACH is a black box. The deliverable is a document allowing the system
     20    designers to use COACH: feeding it (inputs), how to use it (design flow),
     21    what COACH can generate (definition of the generic architecture of the
     22    MPSoC and its 3 targets hardware mapping).
     23    \begin{livrable}
     24    \item{-1-V1}{0}{6}{d}{LIP6}{user manual}
     25        The first milestone of the document for allowing demonstration
     26        \ST to start.
     27    \item{-1-V1}{6}{18}{d}{LIP6}{user manual}
     28        The second milestone takes into account the missing features
     29        the demonstrators rise.
     30    \item{-1-VF}{18}{30}{d}{LIP6}{user manual}
     31        Final release.
     32    \end{livrable}
     33\item This \ST specifies the software COACH structure. The deliverable is a
     34    document listing all the COACH software components and how they cooperate.
     35    \begin{livrable}
     36    \item{}{0}{6}{d}{LIP6}{decription of software architecture}
     37        It contains the software list and the data flow among them.
     38    \end{livrable}
     39\item This \ST specifies the \xcoach format.
     40    \begin{livrable}
     41    \item{-1-V1}{0}{6}{d x}{LIP}{specification of \xcoach format}
     42        First release of the XML specification of the \xcoach format
     43        and its associated documentation allowing to start HLS tools development.
     44    \item{-1-V2}{6}{12}{d x}{LIP}{specification of \xcoach format}
     45        Second release of XML specification of the \xcoach format
     46        taking into account the corrections and modifications that the
     47        developers of HLS tools rise.
     48    \item{-1-VF}{12}{18}{d x}{LIP}{C++ to \xcoach format}
     49        Release of XML specification of the \xcoach format enhanced with
     50        the expression of loop potential.
     51    \item{-2-V1}{0}{12}{x x}{\ubs}{C++ to/from \xcoach format}
     52        The first executable generates a \xcoach description
     53        version \taskname-3-V1 from a C++ description of a task defined in \ST
     54        \taskname-1.
     55        The second program regenerates a C description from a \xcoach
     56        description.
     57    \item{-2-VF}{12}{18}{x x}{\ubs}{C++ to/from \xcoach format}
     58        The same programs as the former but for \xcoach format version \name-3-V2.
     59    \item{-3-V1}{0}{18}{x}{LIP6}{\xcoach format to SystemC}
     60        The first release of a program that translates \xcoach description to CABA
     61        and TLM-DT SystemC.
     62    \item{-3-VF}{18}{24}{x}{LIP6}{\xcoach format to SystemC}
     63        The \name-3-V1 deliverable without bugs reported by the demonstrators.
     64    \item{-4-V1}{0}{18}{x}{\ubs}{\xcoach format to VHDL}
     65        The first release of a program that translates \xcoach description to
     66        synthesizable VHDL description.
     67    \item{-4-VF}{18}{24}{x}{\ubs}{\xcoach format to VHDL}
     68        The \name-4-V1 deliverable without bugs reported by the demonstrators.
     69    \end{livrable}
     70\item Backend HLS tools use a characterized macro-cell library to build the
     71    micro-architecture of a coprocessor. The characterisation of a cell dépends
     72    on the target device. The role of this \ST is to define the macro-cells and
     73    to provite a tool that characterizes them automatically by synthesizing them
     74    and by extracting their delays. This is done by using RTL synthesis.
     75    \begin{livrable}
     76    \item{-1-VF}{0}{6}{d}{\ubs}{macro-cell definition}
     77        The document define the macro cell and the file format describing them.
     78    \item{-2-VF}{0}{12}{x}{\ubs}{macro-cell library generator}
     79        A progam that generates automatically the characterized macro-cell library
     80        for a FPGA device.
     81    \end{livrable}
     82\end{workpackage}
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