Changeset 255

Timestamp:

Feb 17, 2010, 4:39:19 PM (14 years ago)

Author:

coach

Message:

UBS

File:

• anr/section-4.1.tex (modified) (2 diffs)

anr/section-4.1.tex

@@ -29 +29 @@
 For generating the coprocessor of a task mapped as hardware, \verb+CSG+
 controls the HAS tools described below.
-From these inputs \verb!CSG! can generate the entire system (both software \&
+From these inputs \verb!CSG! can generate the entire system (both software and
 hardware) either as a SystemC simulator (cycla accurate and/or TLM) to prototype and explore quickly the
 design space or as a bitstream\footnote{COACH generates synthesizable VHDL, and
@@ -80 +80 @@
     dominated description.
     This task contains also the development of a frequency adaptator
-    that will allow the coprocessors to respect the processor \& the bus
+    that will allow the coprocessors to respect the processor and the bus
     frequency.
 \item[Task-6: \textit{PC/FPGA communication middleware}]