Changeset 383


Ignore:
Timestamp:
Feb 22, 2011, 11:02:52 AM (13 years ago)
Author:
coach
Message:

ia: qq maj et mise en page finale.

Location:
anr
Files:
14 edited

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  • anr/anr.sty

    r361 r383  
    3131
    3232%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    33 %\AtBeginDocument{
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    5051
    5152
    … …  
    252253  \fontsize{11.0pt}{10pt}\selectfont%
    253254  \let\ia@description\description%
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     255  \def\description{\vspace*{-0.0ex}\ia@description\itemsep=1pt\topsep2pt\parskip0pt}%
    255256  %\let\ia@enddescription\enddescription%
    256257  %\newenvironment{description}{%

  • anr/anr.tex

    r356 r383  
    107107% FIN CONFIG
    108108%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
     109\sloppy
    109110
    110111%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%

  • anr/section-1.tex

    r382 r383  
    22The market of digital systems is about 4,600 M\$ today and is estimated to 5,600 M\$ in 2012. However the ever growing applications complexity involves integration of heterogeneous technologies and requires the design of complex Multi-Processors System on Chip (MPSoC). During the last decade, the use of ASICs appeared to be more and more reserved to high volume markets, because the design and fabrication costs of such components exploded, due to increasing NRE (Non Recurring-Engineering) costs. Fortunately, recent FPGA components, such as the Virtex5-6 family from XILINX or the Stratix4 family from ALTERA, can nowadays implement a complete MPSoC with multiple processors and several dedicated coprocessors for a few Keuros per device.
    33\parlf
    4 Many applications are initially captured algorithmically in High-Level Languages (HLLs) such as C/C++. This has led to growing interest in tools that can provide an implementation path directly from HLLs to hardware. Thus, Electronic System Level (ESL) design methodologies (Virtual Prototyping, Co-design, High-Level Synthesis...) are now mature and allow the automation of a system-level design flow.%
    5 %ceci semble vouloir dire que le problÚme de la HLS est résolu pour les ASIC, et que ce que COACH veut faire c'est adapter aux
    6 %FPGAs. Ca me paraît à la fois faux et dangereux. Paul
     4Many applications are initially captured algorithmically in High-Level Languages
     5(HLLs) such as C/C++. This has led to growing interest in tools that can provide
     6an implementation path directly from HLLs to hardware. Thus, Electronic System
     7Level (ESL) design methodologies (Virtual Prototyping, Co-design, High-Level
     8Synthesis...) are now mature and but don’t allow still the full automation of a
     9system-level design flow.
    710Unfortunately, ESL tool development today has primarily focused on the design of
    811hardwired devices i.e. ASICs and ASSPs (Application Specific Standard Product).

  • anr/section-dissemination.tex

    r382 r383  
    1818Pour les projets academiques, l'accord de consortium n'est pas obligatoire
    1919mais fortement conseille.}
    20 
     20%
    2121\subsection{Dissemination}
    2222
    … …  
    2525automatic parallelization, etc. These results will be published in relevant International
    2626Conferences, for instance DATE, DAC, or ICCAD.
    27 \\
    2827More generally, the COACH infrastructure and the design flow supported by the COACH
    2928tools and libraries will be promoted by proposing tutorials on FPGA oriented system level synthesis
    … …  
    3635The COACH project will be an open infrastructure, and the COACH tools and libraries will be available via
    3736a WEB server. This server will be maintained by the UPMC/LIP6 laboratory.
    38 \\
    3937On the standardization side, some effort will be made for analysing how the work around IP-XACT
    4038could be donated for the evolution of the IEEE 1685 standard. \mds is board member of
    … …  
    6260\item
    6361The synthesizable VHDL models supporting the neutral architectural template
    64 (corresponding to the SocLib IP cores library), will have two modes of dissemination.
    65 A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains
    66 also general purpose, reusable components, such as processor cores, memory controllers
    67 optimised cache controllers, peripheral controllers, or bus controllers.
     62(corresponding to the SocLib IP cores library: processor core, memory
     63controllers, ...), will have two modes of dissemination.
     64%A typical MPSoC contains not only dedicated, synthesized coprocessors. It contains
     65%also general purpose, reusable components, such as processor cores, memory controllers
     66%optimised cache controllers, peripheral controllers, or bus controllers.
    6867For non commercial use (i.e. research or education in an academic context, 
    69 or feasibility study in an industrial context), the synthesizable VHDL models will be freely available.
     68or feasibility study in an industrial context), the synthesizable VHDL models
     69will be freely available.
    7070For commercial use, commercial licenses will be negotiated between the owners and the customers.
    7171\item
    … …  
    8080customer framework and will generate service business.
    8181\end{itemize}
    82 
    83 This general approach is supported by a large number (\letterOfInterestNb) of SMEs, as
    84 demonstrated by the "letters of interest" that have been collected during the preparation
     82%
     83A large number (\letterOfInterestNb) of SMEs support this general approach
     84as demonstrated by the "letters of interest" that have been collected during the preparation
    8585of the project and presented in annexe~\ref{lettre-soutien}.
    8686
    … …  
    172172\letterOfInterest{EADS-ASTRIUM}{lettres-2011/Astrium.pdf}.
    173173\letterOfInterest{CONTINENTAL}{lettres-2011/Continental.pdf}.
     174\letterOfInterest{CONTINENTAL}{lettres-2011/Continental.pdf}.
     175\letterOfInterest{CONTINENTAL}{lettres-2011/Continental.pdf}.
     176\letterOfInterest{CONTINENTAL}{lettres-2011/Continental.pdf}.
     177\letterOfInterest{CONTINENTAL}{lettres-2011/Continental.pdf}.
    174178%\letterOfInterest{ADACSYS}{lettres-2011/Coach_ADACSYS_lettre_interet},
    175179%\letterOfInterest{ATEME}{lettres-2011/ATEME.pdf},

  • anr/section-etat-de-art.tex

    r382 r383  
    9393Designers can then only generate a synthesized netlist, VHDL/Verilog simulation test
    9494bench and custom software library that reflect the hardware configuration.
    95 
    96 Consequently, a designer developing an embedded system needs to master four different
     95\\
     96Consequently, a designer developing an embedded system needs to master four
    9797design environments:
    9898\begin{enumerate}
    … …  
    156156 would be valuable in the
    157157context of a System Level design exploration tool.
    158 \par
     158\\
    159159In this context, ASIP design based on Instruction Set Extensions (ISEs) has
    160160received a lot of interest~\cite{NIOS2}, as it makes micro-architecture synthesis
    … …  
    1671672.5x), since ISEs performance is generally limited by I/O constraints as
    168168they generally rely on the main CPU register file to access data.
    169 
    170 % (
    171 %automaticcaly extraction ISE candidates for application code \cite{CODES04},
    172 %performing efficient instruction selection and/or storage resource (register)
    173 %allocation \cite{FPGA08}). 
     169\\
    174170To cope with this issue, recent approaches~\cite{DAC09,CODES08,TVLSI06} advocate the use of
    175171micro-architectural ISE models in which the coupling between the processor micro-architecture
    … …  
    178174point of view and do not address the problem of generating synthesizable representations for
    179175these models.
    180 
     176\\
    181177We therefore strongly believe that there is a need for an open-framework which
    182178would allow researchers and system designers to :
    … …  
    201197data structures. Dependences (exact or conservative) are checked to guarantee
    202198the legality of the transformation.
    203 
     199\\
    204200This has lead to the invention of many loop transformations (loop fusion,
    205201loop splitting, loop skewing, loop interchange, loop unrolling, ...)
    … …  
    209205\cite{FP:96,DRV:2000}, in which the combination of two transformations is
    210206simply a matrix product.
    211 
     207\\
    212208Since hardware is inherently parallel, finding parallelism in sequential
    213209programs in an important prerequisite for HLS. The large FPGA chips of
    … …  
    215211The polyhedral model is the ideal tool for finding more parallelism in
    216212loops.
    217 
     213\\
    218214As a side effect, it has been observed that the polyhedral model is a useful
    219215tool for many other optimization, like memory reduction and locality

  • anr/section-objectif.tex

    r377 r383  
    4545the bitstream on an FPGA and running the executable on a PC.
    4646\end{description}
    47  
    48 % l'avancee scientifique attendue. Preciser l'originalite et le caractere
    49 % ambitieux du projet.
    50 %FIXME == {NON ceci n'est pas une contribution scientifique. A re-ecrire}
    51 
    52 %The main scientific contribution of the project is to unify various synthesis techniques
    53 %(same input and output formats) allowing the user to swap without engineering effort
    54 %from one to another and even to chain them. For instance, it will be possible to run loop transformations before synthesis.
    55 %Another advantage of this framework is to provide different abstraction levels from
    56 %a single description.
    57 %Finally, this description is device family independent and its hardware implementation
    58 %is automatically generated.
    59 
    6047% Detailler les verrous scientifiques et techniques a lever par la realisation du projet.
    6148Hardware/Software co-design is a very complex task. To simplify it, COACH will address the
    … …  
    9885    in a complete System-level design framework.
    9986\end{description}
    100 
    10187%Presenter les resultats escomptes en proposant si possible des criteres de reussite
    10288%et d'evaluation adaptes au type de projet, permettant d'evaluer les resultats en

  • anr/section-position.tex

    r378 r383  
    8787    On the HPC application side, we also hope to benefit from the experience in
    8888    hardware acceleration of bioinformatic algorithms/workfows gathered by the
    89     CAIRN group in the context of the ANR BioWic project (2009-2011), so as to
     89    CAIRN group (ANR BioWic project 2009-2011), so as to
    9090    be able to validate the framework on real-life HPC applications.
    9191
    … …  
    104104
    105105  \item[SoftSoC]
    106      TIMA and MDS are involved in this project, which aims at the standard definition and generation of Hardware Dependent Software layers of a system.
    107      Crucial extensions of the IP-XACT standard will be reused from this project, as well as code generation techniques based on them. 
     106     TIMA and MDS are involved in this project which aims at the
     107     definition and generation of Hardware Dependent Software layers of a
     108     system.
     109     Crucial extensions of the IP-XACT standard will be reused from this
     110     project, as well as code generation techniques based on them.
    108111
    109112\end{description}

  • anr/section-project-description.tex

    r379 r383  
    6767unit).
    6868\parlf
    69 \label{HPC:howto}
     69\label{HPC:howto}%
    7070In addition to digital system design, HPC requires a supplementary
    7171partitioning step presented in figure~\ref{archi-hpc}. The designer
    … …  
    7777is done through \verb!CSG! (figure~\ref{archi-csg}).
    7878\parlf
    79 The project is split into 8 tasks numbered from 1 to 8. They are described
     79The project is split into 8 tasks. They are described
    8080in short below and in detail in section \ref{task-description}.
    8181\begin{description}
    … …  
    108108    Most of them are industrial applications that will be developed within
    109109    the COACH framework.
    110     Others consist in integrating the COACH framework as a driver of
     110    Others consist in integrating the COACH framework into
    111111    industrial proprietary design tools.
    112112\item[Task 8: \textit{Dissemination}]

  • anr/section-project-management.tex

    r356 r383  
    1919
    2020\item[Scientific and Technical Reports]
    21 For every yearly review, a written progress report for each deliverable has to be
    22 provided by the task leader to the coordinator for integration in the contractual reports.
     21For every yearly review, the task leader will provide a written progress report
     22for each deliverable to the coordinator for integration in the contractual reports.
    2323
    2424\item[Management of knowledge, Intellectual Property Right (IPR) and Results Exploitation]
    … …  
    5050the public Authority. The partners will construct mailing lists for
    5151day-to-day communication.
    52 
     52\parlf
    5353The first task will be the redaction of a Consortium Agreement,
    5454dealing mainly with all aspects of the relations

  • anr/section-project-task-schedule.tex

    r380 r383  
    7979    4) GAUT enhancements are not available.
    8080\item[Final Release ($T0+36$)]
    81 
    8281\end{description}
    8382This organisation allows the project to globally progress step by step mixing
    … …  
    8584Hence, demonstrator feed-back will arrive early and so the risk to point out
    8685incompatibility at the integration phase is significantly reduced.
    87 \par
    8886The risks that have been identified at the beginning of the project are the following:
    8987\begin{description}

  • anr/section-ressources.tex

    r382 r383  
    5151        \item[Travel]
    5252            The travel costs are associated to project meeting as well as participation to
    53             conferences. The travel costs are estimated to #4\% of the total requested ANR funding.
     53            conferences. The travel costs are estimated to \textbf{#4\%} of the total requested ANR funding.
    5454        \item[Expenses for inward billing]
    5555            \def\cont{#5}
    … …  
    8080%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%%
    8181
    82 The global effort is \mustbecompleted{XXXXXXXX 358} \hommemois (\hommemoislong),
    83 the part of academic partners is 236 \hommemois (66\% of the global effort)
    84 and the part of the industrial partners is 122 \hommemois (\textbf{34\%} of the
     82The global effort is \textbf{367} \hommemois (\hommemoislong),
     83the part of academic partners is \textbf{245} \hommemois (\textbf{67\%} of the global effort)
     84and the part of the industrial partners is 122 \hommemois (\textbf{33\%} of the
    8585global effort).
    8686The tables in annexe~\ref{effort:by:livrable} gives this global effort by deliverables,
    … …  
    101101  \mds employees involved in the project are permanent managers, engineers and PhD graduates.
    102102  The manpower detail in \hommemois by deliverables is given in
    103   annexe~\ref{table-livrables-mds} (page \pageref{table-livrables-mds}).
    104   and a summary by task in the following table.
     103  annexe~\ref{table-livrables-mds} (page \pageref{table-livrables-mds})
     104  and a summary by tasks in the following table.
    105105  }
    106106  {3.5}
    … …  
    167167  {}
    168168  { The man power detail in \hommemois by deliverables is given in
    169     annexe~\ref{table-livrables-bull} (page \pageref{table-livrables-bull}).
    170     and a summary by task in the following table.
     169    annexe~\ref{table-livrables-bull} (page \pageref{table-livrables-bull})
     170    and a summary by tasks in the following table.
    171171    \bull employees involved in the project are a manager for 9 \hommemois
    172172    and an engineer  for 27 \hommemois.}
    … …  
    185185  { The man power detail in \hommemois by deliverables is given in
    186186    annexe~\ref{table-livrables-thales} (page \pageref{table-livrables-thales})
    187     and a summary by task in the following table.
     187    and a summary by tasks in the following table.
    188188    \thales employees involved in the project are a manager for 7 \hommemois,
    189189    an engineer  for 8 \hommemois and a PHD candidate for 21 \hommemois}

  • anr/task-demonstrator.tex

    r381 r383  
    6666\subtask{SPEAR-DE adaptation for COACH}
    6767    \thales will use its internal software environment tool SPEAR DE to describe the
    68     application. The tool is able to partition and to generate the code for the target. \\
    69 %%%%
    70 %%%% j'avai cru comprendre que ce serait le contraire, et que TRT souhaitait récupérer le
    71 %%%% découpage en processus (D430) comme entrée de SPEAR-DE. Paul
    72 %%%%
    73 
     68    application. The tool is able to partition and to generate the code for the target.
     69    \\
    7470    In this task, we will adapt SPEAR DE to generate the application description input of
    7571    COACH framework. We will also describe the three templates of architecture in order to

  • anr/task-dissemination.tex

    r364 r383  
    1212The main objective is to prepare the further industrial exploitation of the results.
    1313The deliverables to reach these goals will be:
    14 \begin{itemize}
    15   \item The packaging of COACH milestones and final release and their associated
     14%\begin{itemize}
     15%  \item The packaging of COACH milestones and final release and their associated
     16%        installation manuals.
     17%        Two versions will be packaged (one open source, one commercial in the
     18%        Magillem environment).
     19%  \item A tutorial.
     20%  \item The user reference manuals.
     21%\end{itemize}
     22  \textbf{1)} The packaging of COACH milestones and final release and their associated
    1623        installation manuals.
    1724        Two versions will be packaged (one open source, one commercial in the
    1825        Magillem environment).
    19   \item A tutorial.
    20   \item The user reference manuals.
    21 \end{itemize}
     26  \textbf{2)} A tutorial.
     27  \textbf{3)} The user reference manuals.
    2228\end{objectif}
    2329%
    … …  
    4046    \begin{livrable}
    4147    \itemV{6}{12}{d+x}{\Supmc}{Tutorial}
    42         It will illustrate the features that the T0+12 milestone provides especially:
     48        It will illustrate the features of T0+12 milestone, especially:\hfill
    4349        \begin{description}
    4450        \item[HPC] This tutorial section shows how an application can be split into
    45         two communicating parts, the PC part and FPGA-SoC part, and how to
    46         measure the quality of this partition.
     51        two communicating parts (PC part and FPGA-SoC part) and how to
     52        measure the partition quality.
    4753        \item[SoC] This tutorial section shows how FPGA-SoC part can be described as
    48         communicating task graph. The tutorial also describes how a promising
    49         task graph can be obtained.
     54        communicating task graph and how a promising task graph can be obtained.
    5055        \end{description}
    5156    \itemL{30}{36}{d}{\Supmc}{Tutorial}{1.5:0.0:1.0}

  • anr/task-management.tex

    r381 r383  
    77This task relates to the monitoring of the COACH project. Its main objectives are:
    88\begin{itemize}
     9%\setlength{\itemsep}{1pt}\setlength{\parskip}{0pt}\setlength{\parsep}{0pt}
    910\item To ensure the appropriate progress of the project,
    1011\item To coordinate the scientific and technical cooperation between the partners,
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