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Changes between Version 19 and Version 20 of DsxDocumentation

Timestamp:: Feb 20, 2008, 3:43:02 PM (16 years ago)
Author:: Nicolas Pouillon
Comment:: New API

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DsxDocumentation

-                      v19
+                      v20
 Three  platforms are currently supported :
  * Any Linux (or Unix)  workstation  supporting the POSIX threads,
  * MP-SoC architecture using the Mutek/D operation system,
  * MP-SoC architecture using the Mutek/S operating system,
 Mutek/D is an embedded, POSIX compliant, distributed,  operating system for MP-SoCs,
+ * MP-SoC architecture using the Mutek/S operating system (SRL directly implemented on Hexo),
+ * MP-SoC architecture using the Mutek/H operation system (SRL with Posix threads on Hexo),
+Mutek/H is an embedded, POSIX compliant, distributed,  operating system for MP-SoCs,
 while Mutek/S is an optimized version: the performances are improved, and the memory
 footprint is reduced, at the cost of loosing the POSIX compatibility.
 …
 A MWMR communication channel is a memory buffer handled as a software FIFO that can have several producers and several consumers. Each channel is protected by an implicit lock for exclusive access. Any MWMR transaction
 can be decomposed in five memory access:
+.  get the lock protecting the MWMR (READ access).
+.  test the status of the MWMR (READ access).
+.  get the lock protecting the MWMR (LL access).
+.  get the lock protecting the MWMR (SC access).
+.  test the status of the MWMR (3-words READ access).
 .  transfer a burst of data between a local buffer and the MWMR (READ/WRITE access).
+.  update the status of the MWMR (WRITE access).
+.  release the lock (WRITE access).
+.  update the status of the MWMR and release the lock (4-words WRITE access).
 Any data transfer to or from a MWMR channel mut be an integer number of items. The item width is an
 …
 . ''status'' : channel state (number of stored items, read & write pointers)
 . ''buffer'' : channel buffer containing the data
-. ''lock'' : lock protecting exclusive access
 === C3) Synchronization barrier definition ===
 …
 === D1) SoCLib components  ===
-In the current version of DSX, each hardware component must be described by a Python
-class that defines the component interface, and the component parameters.
 The list of available components can be found in SoclibComponents.
+For all components, the instance name is mandatory, but all other parameters have default values and can be skipped:
+{{{
+# creation of a MIPS R3000 processor core
+my_proc = Mips( 'proc' )
+# creation of a cache controler
+my_cache = Xcache( 'cache',
+As it is possible to mix CABA and TLM-T simulation models in the same hardware architecture,
+the system designer can specify the type of simulation model used for each hardware component.
+For all components, the instance name is mandatory.
+{{{
+# definition of the hardware architecture
+archi = soclib.Architecture()
+# instanciation of a MIPS R3000 processor (MIPS ISS in a CABA wrapper), with CPUID = 0
+my_proc = archi.create('caba:iss_wrapper', 'proc', iss_t = 'common:mipsel', ident = 0)
+# instanciation of a CABA cache controler. Both instruction and data caches contain 32 lines of 8 bytes
+my_cache = archi.create('caba:vci_xcache', 'cache',
                         dcache_lines = 32,
                         dcache_words = 8,
 …
 c1.a // c2.b
 }}}
 Depending on the component type, the port designation can vary:
+ * When the number of ports is fixed, the ports are attributs : My_Proc0.cache define the cache port of the MIPS processor.
+ * When the number of port is not fixed (typivally for interconnect component, the ports are allocated through a dedicated method : the getTarget() method of the !LocalCrossbar component allocates a VCI target port, the getInit() method allocates an VCI Initiator port.
+ * When the port is alone, the port is an attribute : My_Proc0.dcache define the data cache port of the processor.
+ * When the number of ports is fixed, the ports are in a array : My_Proc0.irq[3] define the 4th irq line of the processor.
+ * When the number of port in a port array is not fixed (typically for interconnect component), the ports are allocated through a dedicated method on the port array : the new() method on !Vgmn.from_initiator allocates a VCI target port.
 The following example describes asimple system with two processor and on e embedded memory:
 {{{
 # components instanciacion
+my_proc0 = Mips( 'proc0' )
+my_cache0 = Xcache( 'cache0' )
+my_proc1 = Mips( 'proc1' )
+my_cache1 = Xcache( 'cache1' )
+my_ram = MultiRam( 'ram' )
+my_crossbar = LocalCrossbar( 'crossbar' )
+my_proc0 = archi.create('caba:iss_wrapper', 'proc0', iss_t = 'common:mipsel', ident = 0)
+my_cache0 = archi.create('caba:vci_xcache', 'cache0',
+                        dcache_lines = 32,
+                        dcache_words = 8,
+                        dcache_lines = 32,
+                        dcache_words = 8)
+my_proc1 = archi.create('caba:iss_wrapper', 'proc1', iss_t = 'common:mipsel', ident = 1)
+my_cache1 = archi.create('caba:vci_xcache', 'cache1',
+                        dcache_lines = 32,
+                        dcache_words = 8,
+                        dcache_lines = 32,
+                        dcache_words = 8)
+my_ram = archi.create('caba:vci_ram', 'ram' )
+my_vgmn = archi.create('caba:vci_vgmn', 'vgmn' )
 # components connexion
+my_proc0.cache // my_cache0.cache
+my_proc1.cache // my_cache1.cache
+my_crossbar.getTarget() // my_cache0.vci
+my_crossbar.getTarget() // my_cache1.vci
+my_crossbar.getInitiator() // my_cache0.vci
+my_proc0.dcache // my_cache0.dcache
+my_proc0.icache // my_cache0.icache
+my_proc1.dcache // my_cache1.dcache
+my_proc1.icache // my_cache1.icache
+my_vgmn.from_initiator.new() // my_cache0.vci
+my_vgmn.from_initiator.new() // my_cache1.vci
+my_vgmn.to_target.new() // my_ram.vci
 }}}
 === D3) Address space segmentation ===
-All hardware components defining the hardware architecture should be grouped in a single object.
-As any MP-SoC architecture build with the SoCLib library uses a VCI interconnect hardware component,
-this component must be declared as the ''root'' of the architecture :
-{{{
-my_architecture = Hardware( vgmn )
-}}}
 In any shared memory architecture, the address space is a shared resource.  This resource is structured in several segments. A segment has a name, a base address, a size
 …
 The DSX/L language allows the system designer to define the various segments used by a given application,
 and to link those segments to the hardware components.
+The base address and the segment size are optional parameters :
+{{{
+# segments definition
+seg_data1 = Segment( 'seg1', Cached )
+seg_data2 = Segment( 'seg2', Uncached )
+seg_reset = Segment( 'reset', Cached, addr = 0xBFC00000 )
+# Instanciating a VCI target hardware component
+# and assigning  the segments to this component
+my_ram = MultiRam ( 'ram', seg_data1, seg_data2, seg_reset )
+{{{
+my_ram = archi.create('caba:vci_ram', 'ram' )
+my_ram.addSegment('cram0', 0x40000, 0x320)
+my_ram.addSegment('mipsel_reset', 0xbfc00000, 0x100)
 }}}
 …
 {{{
 # mapping table construction
+my_mt = MappingTable()
+# mapping table initialisation
+my_hardware.setConfig( 'maptab', my_mt )
+my_mt = archi.create('common:mapping_table', 'mt', [4], [4], 0xc00000)
 }}}
 …
 As DSX/L is based on Python, it is possible to define generic, parametrized architectutes, that can
+be reused for various applications. Those reusable architectures are derived classes
+from the basic '''Architecture''' class. The implementation is defined in the architecture() method.
+As an example we define a parameterized multi-processors architecture, called !MultiProc, and containing
+a variable number of processors. The parameter(s) must be named, and the actual parameter value is defined
+when the architecture is instanciated. The parameter is referenced with the ''getParam()'' method, and it
+is possible to define a default value.
+be reused for various applications. Those reusable architectures are functions.
 {{{
 #################################
 # generic architecture definition
 #################################
+class MultiProc(Architecture) :
+    defaults = { ’nbcpu’ : 2 }
+    def architecture(self):
+        # segments definition
+        self.reset = Segment( ’reset’, address = 0xbfc00000, type = Cached )
+        self.code = Segment( ’code’, type = Cached )
+        self.data = Segment( ’data’, type = Uncached )
+        # components instanciation and connexion
+        self.vgmn = Vgmn( ’vgmn’ )
+        self.ram = MultiRam( ’ram’, self.reset, self.code, self.data )
+        # processors and caches
+        self.cpus = []
+        for i in self.getParam( ’nbcpu’ ):
+            m = Mips( ’mips%d’%i )
+            self.cpus.append( m )
+            c = Xcache( ’cache%d’%i )
+            g:c.cache // m.cache )
+            c.vci // self.vgmn.getTarget() )
+        self.vgmn.getTarget() // self.c1
+        self.vgmn.getTarget() // self.c2
+        self.vgmn.getInit() // self.ram
+        # base definition
+        self.setBase( self.vgmn )
+        # segment table initialization
+        self.setConfig(’mapping_table’, MappingTable() )
+def MultiProc(nbcpu = 2):
+    archi = soclib.Architecture()
+    vgmn = archi.create('caba:vci_vgmn', 'vgmn' )
+    for i in range(nbcpu):
+        proc = archi.create('caba:iss_wrapper', 'proc%d'%i, iss_t = 'common:mipsel', ident = i)
+        cache = archi.create('caba:vci_xcache', 'cache%d'%i,
+                        dcache_lines = 32,
+                        dcache_words = 8,
+                        dcache_lines = 32,
+                        dcache_words = 8)
+        proc.dcache // cache.dcache
+        proc.icache // cache.icache
+    my_ram = archi.create('caba:vci_ram', 'ram' )
+    my_ram.addSegment( ’reset’, 0xbfc00000, true )
+    my_ram.addSegment( ’code’, 0x40000000, true )
+    my_ram.addSegment( ’data0’, 0x20000000, true )
+    my_ram.addSegment( ’data1’, 0x30000000, false )
+    my_vgmn.to_target.new() // my_ram.vci
 ####################################
 # generic architecture instanciation
 ####################################
 my_board = MultiProc( nbcpu = 4 )
+my_architecture = MultiProc( nbcpu = 4 )
 }}}
 …
 As it is possible to define various mapping for a given TCG, and a given architecture, we must define a third object : this ''mapper'' will contain all the mapping directives defined by the system designer.
 {{{
 my_mapper = Mapper( my_tcg, my_architecture )
+my_mapper = Mapper( my_architecture, my_tcg )
 }}}
 === E2) Mapper definition ===
 The mapper has a method ''map()'' that is used to assign a software object to an hardware component.
+The mapper has a method `map()` that is used to assign a software object to an hardware component.
 An hardware component can be a processor, a segment associated to an embedded memory bank,
 or a segment associated to an addressable peripheral.
 {{{
 # Mapper definition
 my_mapper = Mapper( my_tcg, my_architecture )
+my_mapper = Mapper( my_architecture, my_tcg )
-# a segment seg_x is designated by my_architecture.seg_x
 # For a MWMR channel, 4 software elements must be placed
 my_mapper.map( my_channel,
+        lock = my_archi.seg_locks,  # The lock protecting the channel is placed in segment seg_locks
+        status = my_archi.seg_data,  # The channel status is placed in segment seg_data
+        desc = my_archi.segdata, # The channel descriptor is placed in segment seg_readonly
+        buffer = my_archi.sgdata ) # The channel buffer is placed in segment seg_data
+        status = 'data0',  # The channel status is placed in segment seg_data
+        desc = 'data1', # The channel descriptor is placed in segment seg_readonly
+        buffer = 'data1' ) # The channel buffer is placed in segment seg_data
 # for a software task, 4 software objects must be placed
 my_mappe.map( my_task,
         desc = my_archi.seg_data,  # The task descriptor is placed in segment seg_readonly
         status = my_archi.seg_data,  # The task state is placed in segment seg_data
         stack = my_archi.seg_data,   # The private task stack  is placed in segment seg_stack
         run = my_archi.cpu0 )   # task will be running on cpu0
+        desc = 'data0',  # The task descriptor is placed in segment seg_readonly
+        status = 'data1',  # The task state is placed in segment seg_data
+        stack = 'data0',   # The private task stack  is placed in segment seg_stack
+        run = 'proc0' )   # task will be running on processor no 0
 }}}
 …
  * Software only (Tcg object)
   * Posix() for generating native workstation code
  * Software and hardware (Mapper object)
+ * Software and hardware (Mapper object). Those always generate the associated SystemC simulator
   * MutekS() to use Mutek/S as supporting embedded OS
+  * MutekD() to use Mutel/D as supporting embedded OS
+  * any hardware generator (those on next lines), this will create a platform automatically loading the embedded software
+  * MutekH() to use Mutel/H as supporting embedded OS
  * Hardware only (Hardware object)
+  * Caba() to create a CABA netlist (with SoCLib)
+  * Tlmt() to create a TLM-T netlist (with SoCLib)
+User may want to have a convenience Makefile in platform root which would build all code,
+it may be created passing all generators created to generate code to TopMakefile()
+  * soclib.PfDriver() to create a SystemC netlist (with SoCLib)
 Example: Let's create
  * An application mapped on an hardware platform with CABA and TLM-T simulators
+ * An application mapped on an hardware platform with SystemC simulators
  * a corresponding application for the workstation
- * a top Makefile:
 {{{
 soft = Tcg( ... )
 hard = Hardware( ... )
+hard = soclib.Architecture( ... )
 mapping = Mapper( hard, soft )
 …
 muteks_generator = MutekS()
-caba_generator = Caba()
-tlmt_generator = Tlmt()
 posix_generator = Posix()
 …
 # MutekS and simulators (Caba / Tlmt) generates platform and embedded software for a mapping:
 mapping.generate( muteks_generator, caba_generator, tlmt_generator )
+mapping.generate( muteks_generator )
 # Posix generates code for a Tcg
 tcg.generate( posix_generator )
+# TopMakefile takes the used generators:
+TopMakefile( muteks_generator, caba_generator, tlmt_generator, posix_generator )
+}}}
+}}}