Changes between Version 20 and Version 21 of DsxDocumentation

Timestamp:

Feb 20, 2008, 6:06:56 PM (16 years ago)

Author:

alain

Comment:

--

DsxDocumentation

@@ -207 +207 @@
 archi = soclib.Architecture()
 
-# instanciation of a MIPS R3000 processor (MIPS ISS in a CABA wrapper), with CPUID = 0
+# instanciation of a MIPS R3000 processor (MIPS ISS in a CABA wrapper), with processorID = 0
 my_proc = archi.create('caba:iss_wrapper', 'proc', iss_t = 'common:mipsel', ident = 0)
 
@@ -226 +226 @@
 }}}
 
-Depending on the component type, the port designation can vary:
- * When the port is alone, the port is an attribute : My_Proc0.dcache define the data cache port of the processor.
- * When the number of ports is fixed, the ports are in a array : My_Proc0.irq[3] define the 4th irq line of the processor.
- * When the number of port in a port array is not fixed (typically for interconnect component), the ports are allocated through a dedicated method on the port array : the new() method on !Vgmn.from_initiator allocates a VCI target port.
+Depending on the component type, the port designation can vary :
+ * For a single port : My_Proc0.dcache define the data cache port of the processor.
+ * For an array of ports : My_Proc0.irq[3] define the  irq line 0 of the processor.
+ * When the number of port in a port array is not fixed (typically for interconnect component), the ports are allocated through the new() method on the port array. 
 The following example describes asimple system with two processor and on e embedded memory:
 {{{
@@ -285 +285 @@
 
 {{{
-#################################
+#########################
 # generic architecture definition
-#################################
-def MultiProc(nbcpu = 2): 
-    archi = soclib.Architecture()
+
+def MultiProc(nbcpu = 2):              # the argument value is the default value
+archi = soclib.Architecture()
 
     vgmn = archi.create('caba:vci_vgmn', 'vgmn' )
@@ -312 +312 @@
     my_vgmn.to_target.new() // my_ram.vci
 
-####################################
+###########################
 # generic architecture instanciation
-####################################
+
 my_architecture = MultiProc( nbcpu = 4 )  
 }}} 
@@ -325 +325 @@
 === E1) Mapper declaration ===
 
-As it is possible to define various mapping for a given TCG, and a given architecture, we must define a third object : this ''mapper'' will contain all the mapping directives defined by the system designer.
+As it is possible to define various mapping for a given TCG, and a given architecture, we must define a ''mapper'' object. This ''mapper'' will contain all the mapping directives defined by the system designer for a given mapping.
 {{{
 my_mapper = Mapper( my_architecture, my_tcg )