Changes between Version 1 and Version 5 of MjpegCourse/VgmnNoirqMono

Timestamp:

Mar 12, 2008, 9:44:21 AM (16 years ago)

Author:

Nicolas Pouillon

Comment:

--

MjpegCourse/VgmnNoirqMono

@@ -1 @@
-[[Image(vgmn_noirq_mono.png, align=right)]]
+{{{
+import soclib
 
-{{{
-from dsx.hardware import *
-from soclib import *
+def VgmnNoirqMono():
+        pf = soclib.Architecture(cell_size = 4,
+                                                         plen_size = 1,
+                                                         addr_size = 32,
+                                                         rerror_size = 1,
+                                                         clen_size = 1,
+                                                         rflag_size = 1,
+                                                         srcid_size = 8,
+                                                         pktid_size = 1,
+                                                         trdid_size = 1,
+                                                         wrplen_size = 1
+                                                         )
+        pf.create('common:mapping_table',
+                          'mapping_table',
+                          addr_bits = [8],
+                          srcid_bits = [8],
+                          cacheability_mask = 0xc00000)
+        pf.create('common:elf_loader', 'loader')
 
-class VgmnNoirqMono(SoclibGenericArchitecture):
-  def architecture(self):
-                
-# Définition des segments
-                
-    cram0 = Segment("cram0", Cached)
-    uram0 = Segment("uram0", Uncached)
-    cram1 = Segment("cram1", __remplir__)
-    uram1 = Segment("uram1", __remplir__)
-    reset = Segment("reset", Cached, addr = 0xbfc00000)
-    excep = Segment("excep", Cached, addr = __remplir__)
-                
-# Instanciation des composants matériels
-                
-    vgmn = Vgmn("vgmn",__remplir__)
-    xcache = Xcache("xcache", __remplir__)
-    processor = Mips("processor")
-    tty = MultiTty("tty", __remplir__)
-    ram0 = MultiRam("ram0", cram0, uram0, excep)
-    ram1 = MultiRam("ram0", __remplir__)
-    locks = Locks("locks")
-                
-# Définition de la net-list (connexions)
-                
-    processor.cache // xcache.cache
-    xcache.vci // vgmn.getTarget()
-    tty.vci // vgmn.getInit()
-    ram0.vci // __remplir__
-    ram1.vci // __remplir__
-    locks.vci // __remplir__
-    tty.irq[0] // processor.irq[0]
+        vgmn = pf.create('caba:vci_vgmn', 'vgmn0', *** remplir ***)
 
-# Construction architecture et creation mapping table
+        mips = pf.create('caba:iss_wrapper', 'mips0', iss_t='common:mipsel', *** remplir ***)
+        xcache = pf.create('caba:vci_xcache', 'xcache0',
+                                           icache_lines = 16,
+                                           icache_words = 8,
+                                           dcache_lines = 16,
+                                           dcache_words = 8)
+        mips.dcache // xcache.dcache
+        mips.icache // xcache.icache
 
-    self.setBase(vgmn)
+        vgmn.to_initiator.new() // xcache.vci
 
-# Exportation des variables locales
-  
-    self.cram0 = cram0
-    self.uram0 = uram0
-    self.cram1 = cram1
-    self.uram1 = uram1
-    self.reset = reset
-    self.excep = excep
-                
-    self.vgmn = vgmn
-    self.xcache = xcache
-    self.processor = processor
-    self.tty = tty
-    self.locks = locks
-    self.ram0 = ram0
-    self.ram1 = ram1
+        for i in range(2):
+                ram = pf.create('caba:vci_ram', 'ram%d'%i)
+                base = 0x10000000*i+0x10000000
+                ram.addSegment('cram%d'%i, base, 0x100000, True)
+                ram.addSegment('uram%d'%i, base + 0x200000, 0x100000, False)
+                ram.vci // vgmn.to_target.new()
+        ram.addSegment('boot', *** remplir ***) # Mips boot address, 0x100 octets, cacheable
+        ram.addSegment('excep', *** remplir ***) # Mips exception address, 0x100 octets, cacheable
 
+        tty = pf.create('caba:vci_multi_tty', 'tty0', names = ['tty0'])
+        tty.addSegment('tty0', 0x90000000, 0x20, False)
+        tty.vci // vgmn.to_target.new()
+
+        return pf
 }}}