Changes between Version 13 and Version 14 of SoclibComponents

Timestamp:

Feb 23, 2007, 12:16:22 PM (17 years ago)

Author:

Nicolas Pouillon

Comment:

--

SoclibComponents

@@ -1 +1 @@
 [[PageOutline]]
 
-= Vgmn =
+= Interconnects =
+
+== Vgmn ==
 
  * functionality : a generic VCI compliant micro-network
@@ -12 +14 @@
 my_vgmn = Vgmn("my_vgmn", 10)
 }}}
+ * Defined ports:
+   * `getBoth()`, `getInit()` and `getTarget()`: local ports, allocated on demand
 
-= Xcache =
+== LocalCrossbar ==
+
+ * functionality : a VCI compliant crossbar interconnect
+ * Mandatory arguments:
+   * `instance name`
+ * Example:
+{{{
+my_lc = LocalCrossbar("lc0")
+}}}
+ * Defined ports:
+   * `getBoth()`, `getInit()` and `getTarget()`: local ports, allocated on demand
+   * `upstream`, bidirectional port to upper-level interconnect
+
+= VCI Initiators =
+
+== Xcache ==
 
  * functionality: a direct mapping cache controler (separated instruction & data cache)
@@ -31 +50 @@
                    icache_words = 8 )
 }}}
+ * Defined ports:
+   * `cache`: to the CPU cache port
+   * `vci`: to the micro-network
 
-= Mips =
+= Processors =
+
+== Mips ==
 
  * Functionality : a MIPS R3000 micro-processor
@@ -41 +65 @@
 my_proc = Mips("my_proc")
 }}}
+ * Defined ports:
+   * `cache`: to the cache's cache port
+   * `irq[n]`: interrupt line (0 <= n < 6)
 
-= !MultiRam =
+= VCI Targets =
+
+== !MultiRam ==
 
  * !Mandatory arguments:
@@ -52 +81 @@
 my_ram = MultiRam("my_ram", seg1, seg2, seg3)
 }}}
+ * Defined ports:
+   * `vci`: to the micro-network
 
-= !MultiTty =
+== !MultiTty ==
 
  * functionality: a TTY controler (up to  256 TTYs)
@@ -63 +94 @@
 my_tty = MultiTty("my_tty_controler", "TTY0", "TTY1", "TT2")
 }}}
+ * Defined ports:
+   * `vci`: to the micro-network
+   * `irq[n]`: interrupt line (0 <= n < nb of ttys)
 
-= Locks =
+== Locks ==
 
  * functionality : a locks controler
@@ -73 +107 @@
 my_locks = Locks("my_locks_controler")
 }}}
-
+ * Defined ports:
+   * `vci`: to the micro-network