Changes between Version 17 and Version 18 of SoclibComponents
- Timestamp:
- Jan 28, 2008, 4:20:57 PM (16 years ago)
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SoclibComponents
v17 v18 1 1 [[PageOutline]] 2 2 3 = Interconnects =3 = A) Interconnects = 4 4 5 == Vgmn ==5 == A.1) Vgmn == 6 6 7 7 * functionality : a generic VCI compliant micro-network … … 17 17 * `getBoth()`, `getInit()` and `getTarget()`: local ports, allocated on demand 18 18 19 == !LocalCrossbar ==19 == A.2) !LocalCrossbar == 20 20 21 21 * functionality : a VCI compliant crossbar interconnect … … 30 30 * `upstream`, bidirectional port to upper-level interconnect 31 31 32 = VCI Initiators =32 = B) VCI Initiators = 33 33 34 == Xcache ==34 == B.1) Xcache == 35 35 36 36 * functionality: a direct mapping cache controler (separated instruction & data cache) … … 54 54 * `vci`: to the VCI micro-network 55 55 56 = Processors =56 = C) Processors = 57 57 58 == Mips ==58 == C.1) Mips == 59 59 60 60 * Functionality : a MIPS R3000 micro-processor … … 69 69 * `irq[n]`: interrupt line (0 <= n < 6) 70 70 71 = VCI Targets =71 = D) VCI Targets = 72 72 73 == !MultiRam ==73 == D.1) !MultiRam == 74 74 75 75 * !Mandatory arguments: … … 84 84 * `vci`: to the micro-network 85 85 86 == !MultiTty ==86 == D.2) !MultiTty == 87 87 88 88 * functionality: a TTY controler (up to 256 TTYs) … … 98 98 * `irq[n]`: interrupt line (0 <= n < nb of ttys) 99 99 100 == Locks ==100 == D.3) Locks == 101 101 102 102 * functionality : a locks controler
