Changes between Version 19 and Version 20 of SoclibComponents
- Timestamp:
- Mar 10, 2009, 7:19:25 PM (15 years ago)
Legend:
- Unmodified
- Added
- Removed
- Modified
-
SoclibComponents
v19 v20 1 1 [[PageOutline]] 2 2 3 = A) Interconnects = 3 This page is a little excerpt of all available soclib components, please see documentation on [anrsoclib:wiki:Component SoCLib's main site] for a complete list. 4 4 5 == A.1) Vgmn == 5 6 = Interconnects = 7 8 == Vgmn == 6 9 7 10 * functionality : a generic VCI compliant micro-network … … 17 20 * `to_initiator.new()` and `to_target.new()`: local ports, allocated on demand 18 21 19 == A.2)!LocalCrossbar ==22 == !LocalCrossbar == 20 23 21 24 * functionality : a VCI compliant crossbar interconnect … … 29 32 * `to_initiator.new()` and `to_target.new()`: local ports, allocated on demand 30 33 31 = B)VCI Initiators =34 = VCI Initiators = 32 35 33 == B.1)Xcache ==36 == Xcache == 34 37 35 * functionality: a direct mapping cache controler (separated instruction & data cache)38 * functionality: a n-associative cache controler (separated instruction & data cache) wrapping a given ISS, it can be considered as a CPU with an embedded cache. 36 39 * Arguments: 37 40 * `instance name` 38 * `dcache_ lines` : number of lines in data cache41 * `dcache_sets` : number of lines in data cache 39 42 * `dcache_words` : number of words per line in data cache 40 * `icache_lines` : number of lines in instruction cache 43 * `dcache_ways` : associativity of the data cache 44 * `icache_sets` : number of lines in instruction cache 41 45 * `icache_words` : number of words per line in instruction cache 46 * `icache_ways` : associativity of the instruction cache 47 * `iss_t`: type of ISS to be wrapped in the cache, at least "common:mips32el", "common:mips32eb" and "common:ppc405" are supported 48 * `ident`: cpu number 42 49 * Example: 43 50 {{{ 44 my_cache = arch.create('caba:vci_vgmn', "my_cache", 45 dcache_lines = 32, 46 dcache_words = 8, 47 icache_lines = 32, 48 icache_words = 8 ) 51 my_cpu0 = arch.create('caba:vci_xcache_wrapper', 52 'cpu0', 53 ident = 0, 54 icache_ways = 1, 55 icache_sets = 32, 56 icache_words = 8, 57 dcache_ways = 1, 58 dcache_sets = 32, 59 dcache_words = 8, 60 iss_t = "common:mips32el", 61 ) 49 62 }}} 50 63 * Defined ports: 51 * `dcache`: to the CPU 52 * `icache`: to the CPU 64 * `irq[n]`: to the CPU interrupts 53 65 * `vci`: to the VCI micro-network 54 66 55 = C) Processors =67 = VCI Targets = 56 68 57 == C.1) Mips == 58 59 This component is special as it is in fact a wrapped ISS. 60 61 * Functionality : a MIPS R3000 micro-processor 62 * Arguments: 63 * `name` 64 * `ident`: cpu id 65 * Example: 66 {{{ 67 my_proc = arch.create('caba:iss_wrapper', "my_proc", iss_t = 'common:mipsel', ident = 0 ) 68 }}} 69 * Defined ports: 70 * `dcache`: to the cache's dcache port 71 * `icache`: to the cache's icache port 72 * `irq[n]`: interrupt line (0 <= n < 6) 73 74 = D) VCI Targets = 75 76 == D.1) !MultiRam == 69 == !MultiRam == 77 70 78 71 * !Mandatory arguments: … … 87 80 * Arguments: name, base address, size, cacheability 88 81 {{{ 89 my_ram.addSegment( 'boot', 0xbfc00000, 0x100 , true )82 my_ram.addSegment( 'boot', 0xbfc00000, 0x1000, true ) 90 83 }}} 91 84 92 == D.2)!MultiTty ==85 == !MultiTty == 93 86 94 87 * functionality: a TTY controler … … 98 91 * Example: 99 92 {{{ 100 my_tty = arch.create('caba:vci_multi_tty', "my_tty_controler", ["TTY0", "TTY1", "TT2"])93 my_tty = arch.create('caba:vci_multi_tty', "my_tty_controler", names = ["TTY0", "TTY1", "TT2"]) 101 94 }}} 102 95 * Defined ports:
