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source: soft/giet_vm/giet_python/mapping.py @ 326

Last change on this file since 326 was 326, checked in by alain, 10 years ago
Remove hard-coded xml mappings (replaced by genmap tool, for dynamic generation of map.bin / map.xml / hard_config and giet_vsegs.ld files).
Property svn:executable set to ``*
File size: 102.2 KB

Line
1	#!/usr/bin/env python
2
3	import sys
4
5	##########################################################################################
6	# file : giet_mapping.py
7	# date : april 2014
8	# author : Alain Greiner
9	##########################################################################################
10	# This file contains the classes required to define a mapping for the GIET_VM.
11	# - A 'Mapping' contains a set of 'Cluster' (hardware architecture)
12	# a set of 'Vseg' (kernel virtual segments mapping)
13	# a set of 'Vspace' (several user applications).
14	# - A 'Cluster' contains a set of 'Pseg' (all physical segments in cluster)
15	# a set of 'Proc' (processors in cluster)
16	# a set of 'Periph' (peripherals in cluster)
17	# a set of 'Coproc' (coprocessors in cluster)
18	# - A 'Vspace' contains a set of 'Vseg' (user virtual segments mapping)
19	# a set of 'Task' (user tasks mapping)
20	# - A 'Vseg' contains a set of 'Vobj'
21	# - A 'Periph' contains a set of 'Irq' (only for XCU, ICU and PIC types )
22	# - A 'Coproc' contains a set of 'Cpports' (one port per MWMR channel)
23	##########################################################################################
24	# Implementation Note
25	# As described above, the various objects are distributed in the PYTHON structure:
26	# For example the psegs set is split in several subsets (one subset per cluster),
27	# or the tasks set is split in several subsets (one subset per vspace), etc...
28	# In the C binary data structure used by the giet_vm, all objects of same type
29	# are stored in a linear array (one single array for all psegs for example).
30	# For all objects, we compute and store in the PYTHON object itsel a "global index"
31	# corresponding to the index in this global array, and this index can be used as
32	# a pseudo-pointer to identify a specific object of a given type.
33	##########################################################################################
34
35	######################################################################################
36	# These global lists must be consistent with enums in mapping_info.h or irq_handler.h
37	######################################################################################
38	PERIPHTYPES = [
39	'CMA',
40	'DMA',
41	'FBF',
42	'ICU',
43	'IOB',
44	'IOC',
45	'MMC',
46	'MWR',
47	'NIC',
48	'ROM',
49	'SIM',
50	'TIM',
51	'TTY',
52	'XCU',
53	'PIC',
54	]
55
56	PERIPHSUBTYPES = [
57	'BDV',
58	'HBA',
59	'SPI',
60	'NONE',
61	]
62
63	IRQTYPES = [
64	'HWI',
65	'WTI',
66	'PTI',
67	]
68
69	ISRTYPES = [
70	'ISR_DEFAULT',
71	'ISR_TICK',
72	'ISR_TTY_RX',
73	'ISR_TTY_TX',
74	'ISR_BDV',
75	'ISR_TIMER',
76	'ISR_WAKUP',
77	'ISR_NIC_RX',
78	'ISR_NIC_TX',
79	'ISR_CMA',
80	'ISR_MMC',
81	'ISR_DMA',
82	'ISR_SPI',
83	]
84
85	VOBJTYPES = [
86	'ELF',
87	'BLOB',
88	'PTAB',
89	'PERI',
90	'MWMR',
91	'LOCK',
92	'BUFFER',
93	'BARRIER',
94	'CONST',
95	'MEMSPACE',
96	'SCHED',
97	]
98
99	VSEGMODES = [
100	'____',
101	'___U',
102	'__W_',
103	'__WU',
104	'_X__',
105	'_X_U',
106	'_XW_',
107	'_XWU',
108	'C___',
109	'C__U',
110	'C_W_',
111	'C_WU',
112	'CX__',
113	'CX_U',
114	'CXW_',
115	'CXWU',
116	]
117
118	PSEGTYPES = [
119	'RAM',
120	'ROM', # deprecated => use PERI
121	'PERI',
122	]
123
124	CP_PORT_DIRS = [
125	'TO_COPROC',
126	'FROM_COPROC',
127	]
128
129	##########################################################################################
130	class Mapping( object ):
131	##########################################################################################
132	def __init__( self,
133	name, # mapping name
134	x_size, # number of clusters in a row
135	y_size, # number of clusters in a column
136	procs_max, # max number of processors per cluster
137	x_width = 4, # number of bits encoding x coordinate
138	y_width = 4, # number of bits encoding y coordinate
139	paddr_width = 40, # number of bits for physical address
140	coherence = 1, # hardware cache coherence when non-zero
141	irq_per_proc = 1, # number or IRQs from XCU to processor
142	use_ramdisk = False, # use ramdisk when true
143	x_io = 0, # cluster_io x coordinate
144	y_io = 0, # cluster_io y coordinate
145	reset_address = 0xBFC00000 ): # Processor wired boot_address
146
147	self.signature = 0xDACE2014
148	self.name = name
149	self.paddr_width = paddr_width
150	self.coherence = coherence
151	self.x_size = x_size
152	self.y_size = y_size
153	self.x_width = x_width
154	self.y_width = y_width
155	self.irq_per_proc = irq_per_proc
156	self.procs_max = procs_max
157	self.use_ramdisk = use_ramdisk
158	self.x_io = x_io
159	self.y_io = y_io
160	self.reset_address = reset_address
161
162	self.vseg_increment = 0x10000
163
164	self.total_vspaces = 0
165	self.total_globals = 0
166	self.total_psegs = 0
167	self.total_vsegs = 0
168	self.total_vobjs = 0
169	self.total_tasks = 0
170	self.total_procs = 0
171	self.total_irqs = 0
172	self.total_coprocs = 0
173	self.total_cpports = 0
174	self.total_periphs = 0
175
176	self.clusters = []
177	self.globs = []
178	self.vspaces = []
179
180	for x in xrange( self.x_size ):
181	for y in xrange( self.y_size ):
182	cluster = Cluster( x , y )
183	cluster.index = (x * self.y_size) + y
184	self.clusters.append( cluster )
185
186	return
187
188	########################## add a ram pseg in a cluster
189	def addRam( self,
190	name, # pseg name
191	base, # pseg base address
192	size ): # pseg length (bytes)
193
194	# check coordinates (obtained from the base address)
195	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
196	x = cluster_xy >> (self.y_width);
197	y = cluster_xy & ((1 << self.y_width) - 1)
198
199	assert (base & 0xFFF) == 0
200
201	assert (x < self.x_size) and (y < self.y_size)
202
203	cluster_id = (x * self.y_size) + y
204
205	# add one pseg in the mapping
206	pseg = Pseg( name, base, size, x, y, 'RAM' )
207	self.clusters[cluster_id].psegs.append( pseg )
208	pseg.index = self.total_psegs
209	self.total_psegs += 1
210
211	return pseg
212
213	############################## add a peripheral and the associated pseg in a cluster
214	def addPeriph( self,
215	name, # associated pseg name
216	base, # associated pseg base address
217	size, # associated pseg length (bytes)
218	ptype, # peripheral type
219	subtype = 'NONE', # peripheral subtype
220	channels = 1, # number of channels
221	arg = 0 ): # optional argument (semantic depends on ptype)
222
223	# check cluster coordinates (obtained from the base address)
224	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
225	x = cluster_xy >> (self.y_width);
226	y = cluster_xy & ((1 << self.y_width) - 1)
227
228	assert (x < self.x_size) and (y < self.y_size)
229
230	assert (base & 0xFFF) == 0
231
232	assert ptype in PERIPHTYPES
233
234	assert subtype in PERIPHSUBTYPES
235
236	cluster_id = (x * self.y_size) + y
237
238	# add one pseg into mapping
239	pseg = Pseg( name, base, size, x, y, 'PERI' )
240	self.clusters[cluster_id].psegs.append( pseg )
241	pseg.index = self.total_psegs
242	self.total_psegs += 1
243
244	# add one periph into mapping
245	periph = Periph( pseg, ptype, subtype, channels, arg )
246	self.clusters[cluster_id].periphs.append( periph )
247	periph.index = self.total_periphs
248	self.total_periphs += 1
249
250	return periph
251
252	################################ add an IRQ in a peripheral
253	def addIrq( self,
254	periph, # peripheral containing IRQ (PIC or XCU)
255	index, # peripheral input port index
256	isrtype, # ISR type
257	channel = 0 ): # channel for multi-channels ISR
258
259	assert isrtype in ISRTYPES
260
261	assert index < 32
262
263	# add one irq into mapping
264	irq = Irq( 'HWI', index , isrtype, channel )
265	periph.irqs.append( irq )
266	irq.index = self.total_irqs
267	self.total_irqs += 1
268
269	return irq
270
271	########################## add a processor in a cluster
272	def addProc( self,
273	x, # cluster x coordinate
274	y, # cluster y coordinate
275	p ): # processor local index
276
277	assert (x < self.x_size) and (y < self.y_size)
278
279	cluster_id = (x * self.y_size) + y
280
281	# add one proc into mapping
282	proc = Processor( x, y, p )
283	self.clusters[cluster_id].procs.append( proc )
284	proc.index = self.total_procs
285	self.total_procs += 1
286
287	return proc
288
289	############################## add a coprocessor in a cluster
290	def addCoproc( self,
291	name, # associated pseg name
292	base, # associated pseg base address
293	size ): # associated pseg length
294
295	# check cluster coordinates (obtained from the base address)
296	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
297	x = cluster_xy >> (self.y_width);
298	y = cluster_xy & ((1 << self.y_width) - 1)
299
300	assert (x < self.x_size) and (y < self.y_size)
301
302	cluster_id = (x * self.y_size) + y
303
304	# add one pseg into mapping
305	pseg = Pseg( name, base, size, x, y, 'PERI' )
306	self.clusters[cluster_id].psegs.append( pseg )
307	pseg.index = self.total_psegs
308	self.total_psegs += 1
309
310	# add one coproc into mapping
311	periph = Coproc( pseg )
312	self.clusters[cluster_id].coprocs.append( coproc )
313	periph.index = self.total_coprocs
314	self.total_coprocs += 1
315
316	return coproc
317
318	################################## add a port in a coprocessor
319	def addPort( self,
320	coproc, # coprocessor containing the port
321	direction, # direction (TO_COPROC / FROM_COPROC)
322	vspacename, # name of vspace using the coproc
323	mwmrname ): # name of the vobj defining the MWMR channel
324
325	assert direction in CP_PORT_DIRS
326
327	# add one cpport into mapping
328	port = Cpport( direction, vspacename, mwmrname )
329	coproc.ports.append( port )
330	port.index = self.total_cpports
331	self.total_cpports += 1
332
333	return port
334
335	############################ add one (or several) global vseg into mapping
336	def addGlobal( self,
337	name, # vseg name
338	vbase, # virtual base address
339	size, # vobj length (bytes)
340	mode, # CXWU flags
341	vtype, # vobj type
342	x, # destination x coordinate
343	y, # destination y coordinate
344	pseg, # destination pseg name
345	identity = False, # identity mapping required if true
346	replicated = False, # replicated in all clusters if true
347	binpath = '' ): # pathname for binary code
348
349	assert (identity and replicated) == False
350
351	assert mode in VSEGMODES
352
353	assert vtype in VOBJTYPES
354
355	assert (vbase & 0xFFF) == 0
356
357	assert (x < self.x_size) and (y < self.y_size)
358
359	if ( replicated ): # replicated
360	for x_rep in xrange( self.x_size ):
361	for y_rep in xrange( self.y_size ):
362	vbase_rep = vbase + (((x_rep << self.y_width) + y_rep) << 16)
363	name_rep = name + '_%d_%d' % ( x_rep , y_rep )
364
365	# add one vseg [x,y] into mapping
366	vseg = Vseg( name_rep, vbase_rep, mode, x_rep, y_rep, pseg, identity )
367	self.globs.append( vseg )
368	self.total_globals += 1
369	vseg.index = self.total_vsegs
370	self.total_vsegs += 1
371
372	# add one vobj [x,y] in the mapping
373	vobj = Vobj( name_rep, size, vtype, binpath, 0, 0 )
374	vseg.vobjs.append( vobj )
375	vobj.index = self.total_vobjs
376	self.total_vobjs += 1
377
378	else: # single vseg
379	# add one vseg into mapping
380	vseg = Vseg( name, vbase, mode, x, y, pseg, identity )
381	self.globs.append( vseg )
382	self.total_globals += 1
383	vseg.index = self.total_vsegs
384	self.total_vsegs += 1
385
386	# add one vobj into mapping
387	vobj = Vobj( name, size, vtype, binpath, 0, 0 )
388	vseg.vobjs.append( vobj )
389	vobj.index = self.total_vobjs
390	self.total_vobjs += 1
391
392	return
393
394	################################ add a vspace into mapping
395	def addVspace( self,
396	name, # vspace name
397	startname ): # name of vobj containing start_vector
398
399	# add one vspace into mapping
400	vspace = Vspace( name, startname )
401	self.vspaces.append( vspace )
402	vspace.index = self.total_vspaces
403	self.total_vspaces += 1
404
405	return vspace
406
407	################################# add a private vseg and a vobj in a vspace
408	def addVseg( self,
409	vspace, # vspace containing the vseg
410	name, # vseg name
411	vbase, # virtual base address
412	size, # vobj length (bytes)
413	mode, # CXWU flags
414	vtype, # vobj type
415	x, # destination x coordinate
416	y, # destination y coordinate
417	pseg, # destination pseg name
418	binpath = '', # pathname for binary code
419	align = 0, # alignment required
420	init = 0 ): # initial value
421
422	assert mode in VSEGMODES
423
424	assert vtype in VOBJTYPES
425
426	assert (x < self.x_size) and (y < self.y_size)
427
428	# add one vseg into mapping
429	vseg = Vseg( name, vbase, mode, x, y, pseg )
430	vspace.vsegs.append( vseg )
431	vseg.index = self.total_vsegs
432	self.total_vsegs += 1
433
434	# add one vobj into mapping
435	vobj = Vobj( name, size, vtype, binpath, align, init )
436	vseg.vobjs.append( vobj )
437	vobj.index = self.total_vobjs
438	self.total_vobjs += 1
439
440	return vseg
441
442	################################ add a vobj in a private vseg
443	def addVobj( self,
444	vseg, # vseg containing vobj
445	name, # vobj name
446	size, # vobj length (bytes)
447	vtype, # vobj type
448	binpath = '', # pathname to binary
449	align = 0, # alignment constraint
450	init = 0 ): # initial value
451
452	assert vtype in VOBJTYPES
453
454	# add one vobj into mapping
455	vobj = Vobj( name, size, vtype, binpath, align, init )
456	vseg.vobjs.append( vobj )
457	vobj.index = self.total_vobjs
458	self.total_vobjs += 1
459
460	return vobj
461
462	################################ add a task in a vspace
463	def addTask( self,
464	vspace, # vspace containing task
465	name, # task name
466	trdid, # task index in vspace
467	x, # destination x coordinate
468	y, # destination y coordinate
469	lpid, # destination processor local index
470	stackname, # name of vobj containing stack
471	heapname, # name of vobj containing heap
472	startid, # index in start_vector
473	usetty = False, # request a private TTY channel
474	usenic = False, # request a private NIC channel
475	usecma = False, # request a private CMA channel
476	usehba = False, # request a private HBA channel
477	usetim = False ): # request a private TIM channel
478
479	assert (x < self.x_size) and (y < self.y_size)
480
481	assert lpid < self.procs_max
482
483	# add one task into mapping
484	task = Task( name, trdid, x, y, lpid, stackname, heapname, startid,
485	usetty, usenic, usecma, usehba, usetim )
486	vspace.tasks.append( task )
487	task.index = self.total_tasks
488	self.total_tasks += 1
489
490	return task
491
492	#################################
493	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
494
495	byte_stream = bytearray()
496	length = len( s )
497	if length < (nbytes - 1):
498	for b in s:
499	byte_stream.append( b )
500	for x in xrange(nbytes-length):
501	byte_stream.append( '\0' )
502	else:
503	print 'error in str2bytes() string %s too long' % s
504	sys.exit(1)
505
506	return byte_stream
507
508	###################################
509	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
510
511	byte_stream = bytearray()
512	for n in xrange( nbytes ):
513	byte_stream.append( (val >> (n<<3)) & 0xFF )
514
515	return byte_stream
516
517	################
518	def xml( self ): # xml file generation for mapping
519
520	s = '<?xml version="1.0"?>\n\n'
521	s += '<mapping_info signature = "0x%x"\n' % (self.signature)
522	s += ' name = "%s"\n' % (self.name)
523	s += ' x_size = "%d"\n' % (self.x_size)
524	s += ' y_size = "%d"\n' % (self.y_size)
525	s += ' x_width = "%d"\n' % (self.x_width)
526	s += ' y_width = "%d"\n' % (self.y_width)
527	s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc)
528	s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk)
529	s += ' x_io = "%d"\n' % (self.x_io)
530	s += ' y_io = "%d" >\n' % (self.y_io)
531	s += '\n'
532
533	s += ' <clusterset>\n'
534	for x in xrange ( self.x_size ):
535	for y in xrange ( self.y_size ):
536	cluster_id = (x * self.y_size) + y
537	s += self.clusters[cluster_id].xml()
538	s += ' </clusterset>\n'
539	s += '\n'
540
541	s += ' <globalset>\n'
542	for vseg in self.globs: s += vseg.xml()
543	s += ' </globalset>\n'
544	s += '\n'
545
546	s += ' <vspaceset>\n'
547	for vspace in self.vspaces: s += vspace.xml()
548	s += ' </vspaceset>\n'
549
550	s += '</mapping_info>\n'
551	return s
552
553	#########################
554	def cbin( self, verbose ): # C binary structure generation for mapping
555
556	byte_stream = bytearray()
557
558	# header
559	byte_stream += self.int2bytes(4, self.signature)
560	byte_stream += self.int2bytes(4, self.x_size)
561	byte_stream += self.int2bytes(4, self.y_size)
562	byte_stream += self.int2bytes(4, self.x_width)
563	byte_stream += self.int2bytes(4, self.y_width)
564	byte_stream += self.int2bytes(4, self.x_io)
565	byte_stream += self.int2bytes(4, self.y_io)
566	byte_stream += self.int2bytes(4, self.irq_per_proc)
567	byte_stream += self.int2bytes(4, self.use_ramdisk)
568	byte_stream += self.int2bytes(4, self.total_globals)
569	byte_stream += self.int2bytes(4, self.total_vspaces)
570	byte_stream += self.int2bytes(4, self.total_psegs)
571	byte_stream += self.int2bytes(4, self.total_vsegs)
572	byte_stream += self.int2bytes(4, self.total_vobjs)
573	byte_stream += self.int2bytes(4, self.total_tasks)
574	byte_stream += self.int2bytes(4, self.total_procs)
575	byte_stream += self.int2bytes(4, self.total_irqs)
576	byte_stream += self.int2bytes(4, self.total_coprocs)
577	byte_stream += self.int2bytes(4, self.total_cpports)
578	byte_stream += self.int2bytes(4, self.total_periphs)
579	byte_stream += self.str2bytes(32, self.name)
580
581	if ( verbose ):
582	print '\n'
583	print 'name = %s' % self.name
584	print 'signature = %x' % self.signature
585	print 'x_size = %d' % self.x_size
586	print 'y_size = %d' % self.y_size
587	print 'x_width = %d' % self.x_width
588	print 'y_width = %d' % self.y_width
589	print 'x_io = %d' % self.x_io
590	print 'y_io = %d' % self.y_io
591	print 'irq_per_proc = %d' % self.irq_per_proc
592	print 'use_ramdisk = %d' % self.use_ramdisk
593	print 'total_globals = %d' % self.total_globals
594	print 'total_psegs = %d' % self.total_psegs
595	print 'total_vsegs = %d' % self.total_vsegs
596	print 'total_vobjs = %d' % self.total_vobjs
597	print 'total_tasks = %d' % self.total_tasks
598	print 'total_procs = %d' % self.total_procs
599	print 'total_irqs = %d' % self.total_irqs
600	print 'total_coprocs = %d' % self.total_coprocs
601	print 'total_cpports = %d' % self.total_cpports
602	print 'total_periphs = %d' % self.total_periphs
603	print '\n'
604
605	# clusters array
606	index = 0
607	for cluster in self.clusters:
608	byte_stream += cluster.cbin( self, verbose, index )
609	index += 1
610
611	if ( verbose ): print '\n'
612
613	# psegs array
614	index = 0
615	for cluster in self.clusters:
616	for pseg in cluster.psegs:
617	byte_stream += pseg.cbin( self, verbose, index, cluster )
618	index += 1
619
620	if ( verbose ): print '\n'
621
622	# vspaces array
623	index = 0
624	for vspace in self.vspaces:
625	byte_stream += vspace.cbin( self, verbose, index )
626	index += 1
627
628	if ( verbose ): print '\n'
629
630	# vsegs array
631	index = 0
632	for vseg in self.globs:
633	byte_stream += vseg.cbin( self, verbose, index )
634	index += 1
635	for vspace in self.vspaces:
636	for vseg in vspace.vsegs:
637	byte_stream += vseg.cbin( self, verbose, index )
638	index += 1
639
640	if ( verbose ): print '\n'
641
642	# vobjs array
643	index = 0
644	for vseg in self.globs:
645	for vobj in vseg.vobjs:
646	byte_stream += vobj.cbin( self, verbose, index )
647	index += 1
648	for vspace in self.vspaces:
649	for vseg in vspace.vsegs:
650	for vobj in vseg.vobjs:
651	byte_stream += vobj.cbin( self, verbose, index )
652	index += 1
653
654	if ( verbose ): print '\n'
655
656	# tasks array
657	index = 0
658	for vspace in self.vspaces:
659	for task in vspace.tasks:
660	byte_stream += task.cbin( self, verbose, index, vspace )
661	index += 1
662
663	if ( verbose ): print '\n'
664
665	# procs array
666	index = 0
667	for cluster in self.clusters:
668	for proc in cluster.procs:
669	byte_stream += proc.cbin( self, verbose, index )
670	index += 1
671
672	if ( verbose ): print '\n'
673
674	# irqs array
675	index = 0
676	for cluster in self.clusters:
677	for periph in cluster.periphs:
678	for irq in periph.irqs:
679	byte_stream += irq.cbin( self, verbose, index )
680	index += 1
681
682	if ( verbose ): print '\n'
683
684	# coprocs array
685	index = 0
686	for cluster in self.clusters:
687	for coproc in cluster.coprocs:
688	byte_stream += coproc.cbin( self, verbose, index )
689	index += 1
690
691	if ( verbose ): print '\n'
692
693	# cpports array
694	index = 0
695	for cluster in self.clusters:
696	for coproc in cluster.coprocs:
697	for port in coproc.ports:
698	byte_stream += port.cbin( self, verbose, index )
699	index += 1
700
701	if ( verbose ): print '\n'
702
703	# periphs array
704	index = 0
705	for cluster in self.clusters:
706	for periph in cluster.periphs:
707	byte_stream += periph.cbin( self, verbose, index )
708	index += 1
709
710	return byte_stream
711	# end of cbin()
712
713	#######################
714	def giet_vsegs( self ): # compute string for giet_vsegs.ld file
715	# required by giet_vm compilation
716
717	# search the vsegs required for the giet_vsegs.ld
718	boot_code_found = False
719	boot_data_found = False
720	kernel_uncdata_found = False
721	kernel_data_found = False
722	kernel_code_found = False
723	kernel_init_found = False
724	for vseg in self.globs:
725	if ( vseg.name == 'seg_boot_code' ):
726	boot_code_vbase = vseg.vbase
727	boot_code_size = vseg.vobjs[0].length
728	boot_code_found = True
729
730	if ( vseg.name == 'seg_boot_data' ):
731	boot_data_vbase = vseg.vbase
732	boot_data_size = vseg.vobjs[0].length
733	boot_data_found = True
734
735	if ( vseg.name == 'seg_kernel_uncdata' ):
736	kernel_uncdata_vbase = vseg.vbase
737	kernel_uncdata_size = vseg.vobjs[0].length
738	kernel_uncdata_found = True
739
740	if ( vseg.name == 'seg_kernel_data' ):
741	kernel_data_vbase = vseg.vbase
742	kernel_data_size = vseg.vobjs[0].length
743	kernel_data_found = True
744
745	if ( vseg.name == 'seg_kernel_code' ):
746	kernel_code_vbase = vseg.vbase
747	kernel_code_size = vseg.vobjs[0].length
748	kernel_code_found = True
749
750	if ( vseg.name == 'seg_kernel_init' ):
751	kernel_init_vbase = vseg.vbase
752	kernel_init_size = vseg.vobjs[0].length
753	kernel_init_found = True
754
755	# check if all required vsegs have been found
756	if ( boot_code_found == False ):
757	print 'error in giet_vsegs() : seg_boot_code vseg missing'
758	sys.exit()
759
760	if ( boot_data_found == False ):
761	print 'error in giet_vsegs() : seg_boot_data vseg missing'
762	sys.exit()
763
764	if ( kernel_data_found == False ):
765	print 'error in giet_vsegs() : seg_kernel_data vseg missing'
766	sys.exit()
767
768	if ( kernel_uncdata_found == False ):
769	print 'error in giet_vsegs() : seg_kernel_uncdata vseg missing'
770	sys.exit()
771
772	if ( kernel_code_found == False ):
773	print 'error in giet_vsegs() : seg_kernel_data vseg missing'
774	sys.exit()
775
776	if ( kernel_init_found == False ):
777	print 'error in giet_vsegs() : seg_kernel_init vseg missing'
778	sys.exit()
779
780	# build string
781	s = '/* Generated by tsarmap for %s */\n' % self.name
782	s += '\n'
783
784	s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase
785	s += 'boot_code_size = 0x%x;\n' % boot_code_size
786	s += '\n'
787	s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase
788	s += 'boot_data_size = 0x%x;\n' % boot_data_size
789	s += '\n'
790	s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase
791	s += 'kernel_code_size = 0x%x;\n' % kernel_code_size
792	s += '\n'
793	s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase
794	s += 'kernel_data_size = 0x%x;\n' % kernel_data_size
795	s += '\n'
796	s += 'kernel_uncdata_vbase = 0x%x;\n' % kernel_uncdata_vbase
797	s += 'kernel_uncdata_size = 0x%x;\n' % kernel_uncdata_size
798	s += '\n'
799	s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase
800	s += 'kernel_init_size = 0x%x;\n' % kernel_init_size
801	s += '\n'
802
803	return s
804
805	########################
806	def hard_config( self ): # compute string for hard_config.h file required by
807	# - top.cpp compilation
808	# - giet_vm compilation
809	# - tsar_preloader compilation
810
811	nb_total_procs = 0
812
813	# for each peripheral type, define default values
814	# for pbase address, size, number of components, and channels
815	nb_cma = 0
816	cma_channels = 0
817	seg_cma_base = 0xFFFFFFFF
818	seg_cma_size = 0
819
820	nb_dma = 0
821	dma_channels = 0
822	seg_dma_base = 0xFFFFFFFF
823	seg_dma_size = 0
824
825	nb_fbf = 0
826	fbf_channels = 0
827	seg_fbf_base = 0xFFFFFFFF
828	seg_fbf_size = 0
829
830	nb_icu = 0
831	icu_channels = 0
832	seg_icu_base = 0xFFFFFFFF
833	seg_icu_size = 0
834
835	nb_iob = 0
836	iob_channels = 0
837	seg_iob_base = 0xFFFFFFFF
838	seg_iob_size = 0
839
840	nb_ioc = 0
841	ioc_channels = 0
842	seg_ioc_base = 0xFFFFFFFF
843	seg_ioc_size = 0
844
845	nb_mmc = 0
846	mmc_channels = 0
847	seg_mmc_base = 0xFFFFFFFF
848	seg_mmc_size = 0
849
850	nb_mwr = 0
851	mwr_channels = 0
852	seg_mwr_base = 0xFFFFFFFF
853	seg_mwr_size = 0
854
855	nb_nic = 0
856	nic_channels = 0
857	seg_nic_base = 0xFFFFFFFF
858	seg_nic_size = 0
859
860	nb_pic = 0
861	pic_channels = 0
862	seg_pic_base = 0xFFFFFFFF
863	seg_pic_size = 0
864
865	nb_rom = 0
866	rom_channels = 0
867	seg_rom_base = 0xFFFFFFFF
868	seg_rom_size = 0
869
870	nb_sim = 0
871	sim_channels = 0
872	seg_sim_base = 0xFFFFFFFF
873	seg_sim_size = 0
874
875	nb_tim = 0
876	tim_channels = 0
877	seg_tim_base = 0xFFFFFFFF
878	seg_tim_size = 0
879
880	nb_tty = 0
881	tty_channels = 0
882	seg_tty_base = 0xFFFFFFFF
883	seg_tty_size = 0
884
885	nb_xcu = 0
886	xcu_channels = 0
887	seg_xcu_base = 0xFFFFFFFF
888	seg_xcu_size = 0
889
890	use_bdv = False
891	use_spi = False
892	use_hba = False
893
894	# get peripherals attributes
895	for cluster in self.clusters:
896	for periph in cluster.periphs:
897	if ( periph.ptype == 'CMA' ):
898	seg_cma_base = periph.pseg.base & 0xFFFFFFFF
899	seg_cma_size = periph.pseg.size
900	cma_channels = periph.channels
901	nb_cma +=1
902
903	elif ( periph.ptype == 'DMA' ):
904	seg_dma_base = periph.pseg.base & 0xFFFFFFFF
905	seg_dma_size = periph.pseg.size
906	dma_channels = periph.channels
907	nb_dma +=1
908
909	elif ( periph.ptype == 'FBF' ):
910	seg_fbf_base = periph.pseg.base & 0xFFFFFFFF
911	seg_fbf_size = periph.pseg.size
912	fbf_channels = periph.channels
913	nb_fbf +=1
914
915	elif ( periph.ptype == 'ICU' ):
916	seg_icu_base = periph.pseg.base & 0xFFFFFFFF
917	seg_icu_size = periph.pseg.size
918	icu_channels = periph.channels
919	nb_icu +=1
920
921	elif ( periph.ptype == 'IOB' ):
922	seg_iob_base = periph.pseg.base & 0xFFFFFFFF
923	seg_iob_size = periph.pseg.size
924	iob_channels = periph.channels
925	nb_iob +=1
926
927	elif ( periph.ptype == 'IOC' ):
928	seg_ioc_base = periph.pseg.base & 0xFFFFFFFF
929	seg_ioc_size = periph.pseg.size
930	ioc_channels = periph.channels
931	nb_ioc += 1
932	if ( periph.subtype == 'BDV' ): use_bdv = True
933	elif ( periph.subtype == 'HBA' ): use_hba = True
934	elif ( periph.subtype == 'SPI' ): use_spi = True
935
936	elif ( periph.ptype == 'MMC' ):
937	seg_mmc_base = periph.pseg.base & 0xFFFFFFFF
938	seg_mmc_size = periph.pseg.size
939	mmc_channels = periph.channels
940	nb_mmc +=1
941
942	elif ( periph.ptype == 'MWR' ):
943	seg_mwr_base = periph.pseg.base & 0xFFFFFFFF
944	seg_wmr_size = periph.pseg.size
945	mwr_channels = periph.channels
946	nb_mwr +=1
947
948	elif ( periph.ptype == 'ROM' ):
949	seg_rom_base = periph.pseg.base & 0xFFFFFFFF
950	seg_rom_size = periph.pseg.size
951	rom_channels = periph.channels
952	nb_rom +=1
953
954	elif ( periph.ptype == 'SIM' ):
955	seg_sim_base = periph.pseg.base & 0xFFFFFFFF
956	seg_sim_size = periph.pseg.size
957	sim_channels = periph.channels
958	nb_sim +=1
959
960	elif ( periph.ptype == 'NIC' ):
961	seg_nic_base = periph.pseg.base & 0xFFFFFFFF
962	seg_nic_size = periph.pseg.size
963	nic_channels = periph.channels
964	nb_nic +=1
965
966	elif ( periph.ptype == 'PIC' ):
967	seg_pic_base = periph.pseg.base & 0xFFFFFFFF
968	seg_pic_size = periph.pseg.size
969	pic_channels = periph.channels
970	nb_pic +=1
971
972	elif ( periph.ptype == 'TIM' ):
973	seg_tim_base = periph.pseg.base & 0xFFFFFFFF
974	seg_tim_size = periph.pseg.size
975	tim_channels = periph.channels
976	nb_tim +=1
977
978	elif ( periph.ptype == 'TTY' ):
979	seg_tty_base = periph.pseg.base & 0xFFFFFFFF
980	seg_tty_size = periph.pseg.size
981	tty_channels = periph.channels
982	nb_tty +=1
983
984	elif ( periph.ptype == 'XCU' ):
985	seg_xcu_base = periph.pseg.base & 0xFFFFFFFF
986	seg_xcu_size = periph.pseg.size
987	xcu_channels = periph.channels
988	nb_xcu +=1
989
990	# don't mix ICU and XCU
991	assert ( nb_icu*nb_xcu == 0 )
992
993	# no more than two access to external peripherals
994	assert ( nb_fbf <= 2 )
995	assert ( nb_cma <= 2 )
996	assert ( nb_ioc <= 2 )
997	assert ( nb_nic <= 2 )
998	assert ( nb_tim <= 2 )
999	assert ( nb_tty <= 2 )
1000	assert ( nb_pic <= 2 )
1001
1002	# one and only one type of IOC controller
1003	assert ( use_hba or use_bdv or use_spi )
1004	assert ( (use_hba and use_bdv) == False )
1005	assert ( (use_hba and use_spi) == False )
1006	assert ( (use_bdv and use_spi) == False )
1007
1008	# Compute total number of processors
1009	for cluster in self.clusters:
1010	nb_total_procs += len( cluster.procs )
1011
1012	# Compute physical addresses for BOOT vsegs
1013	boot_mapping_found = False
1014	boot_code_found = False
1015	boot_data_found = False
1016	boot_buffer_found = False
1017	boot_stack_found = False
1018
1019	for vseg in self.globs:
1020	if ( vseg.name == 'seg_boot_mapping' ):
1021	boot_mapping_base = vseg.vbase
1022	boot_mapping_size = vseg.vobjs[0].length
1023	boot_mapping_ident = vseg.ident
1024	boot_mapping_found = True
1025
1026	if ( vseg.name == 'seg_boot_code' ):
1027	boot_code_base = vseg.vbase
1028	boot_code_size = vseg.vobjs[0].length
1029	boot_code_ident = vseg.ident
1030	boot_code_found = True
1031
1032	if ( vseg.name == 'seg_boot_data' ):
1033	boot_data_base = vseg.vbase
1034	boot_data_size = vseg.vobjs[0].length
1035	boot_data_ident = vseg.ident
1036	boot_data_found = True
1037
1038	if ( vseg.name == 'seg_boot_buffer' ):
1039	boot_buffer_base = vseg.vbase
1040	boot_buffer_size = vseg.vobjs[0].length
1041	boot_buffer_ident = vseg.ident
1042	boot_buffer_found = True
1043
1044	if ( vseg.name == 'seg_boot_stack' ):
1045	boot_stack_base = vseg.vbase
1046	boot_stack_size = vseg.vobjs[0].length
1047	boot_stack_ident = vseg.ident
1048	boot_stack_found = True
1049
1050	# check all BOOT vsegs are found and identity mapping
1051	if ( (boot_mapping_found == False) or (boot_mapping_ident == False) ):
1052	print 'error in hard_config() : seg_boot_mapping missing or not ident'
1053	sys.exit()
1054
1055	if ( (boot_code_found == False) or (boot_code_ident == False) ):
1056	print 'error in hard_config() : seg_boot_code missing or not ident'
1057	sys.exit()
1058
1059	if ( (boot_data_found == False) or (boot_data_ident == False) ):
1060	print 'error in hard_config() : seg_boot_data missing or not ident'
1061	sys.exit()
1062
1063	if ( (boot_buffer_found == False) or (boot_buffer_ident == False) ):
1064	print 'error in hard_config() : seg_boot_buffer missing or not ident'
1065	sys.exit()
1066
1067	if ( (boot_stack_found == False) or (boot_stack_ident == False) ):
1068	print 'error in giet_vsegs() : seg_boot_stack missing or not ident'
1069	sys.exit()
1070
1071	# Search RAMDISK global vseg if required
1072	seg_rdk_base = 0xFFFFFFFF
1073	seg_rdk_size = 0
1074	seg_rdk_found = False
1075
1076	if self.use_ramdisk:
1077	for vseg in self.globs:
1078	if ( vseg.name == 'seg_ramdisk' ):
1079	seg_rdk_base = vseg.vbase
1080	seg_rdk_size = vseg.vobjs[0].length
1081	seg_rdk_found = True
1082
1083	if ( seg_rdk_found == False ):
1084	print 'Error in hard_config() "seg_ramdisk" not found'
1085	sys.exit(1)
1086
1087	# build string
1088	s = '/* Generated by tsarmap for %s */\n' % self.name
1089	s += '\n'
1090	s += '#ifndef HARD_CONFIG_H\n'
1091	s += '#define HARD_CONFIG_H\n'
1092	s += '\n'
1093
1094	s += '/* General platform parameters */\n'
1095	s += '\n'
1096	s += '#define X_SIZE %d\n' % self.x_size
1097	s += '#define Y_SIZE %d\n' % self.y_size
1098	s += '#define X_WIDTH %d\n' % self.x_width
1099	s += '#define Y_WIDTH %d\n' % self.y_width
1100	s += '#define X_IO %d\n' % self.x_io
1101	s += '#define Y_IO %d\n' % self.y_io
1102	s += '#define NB_PROCS_MAX %d\n' % self.procs_max
1103	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc
1104	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
1105	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs
1106	s += '\n'
1107
1108	s += '/* Peripherals */\n'
1109	s += '\n'
1110	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
1111	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
1112	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
1113	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
1114	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
1115	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
1116	s += '\n'
1117	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
1118	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
1119	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
1120	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
1121	s += '\n'
1122	s += '#define USE_IOC_BDV %d\n' % use_bdv
1123	s += '#define USE_IOC_SPI %d\n' % use_spi
1124	s += '#define USE_IOC_HBA %d\n' % use_hba
1125	s += '\n'
1126	s += '#define USE_RAMDISK %d\n' % self.use_ramdisk
1127	s += '\n'
1128
1129	s += '/* physical base addresses for peripherals */\n'
1130	s += '\n'
1131	s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base
1132	s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size
1133	s += '\n'
1134	s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base
1135	s += '#define SEG_DMA_SIZE 0x%x\n' % seg_cma_size
1136	s += '\n'
1137	s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base
1138	s += '#define SEG_FBF_SIZE 0x%x\n' % seg_cma_size
1139	s += '\n'
1140	s += '#define SEG_ICU_BASE 0x%x\n' % seg_icu_base
1141	s += '#define SEG_ICU_SIZE 0x%x\n' % seg_cma_size
1142	s += '\n'
1143	s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base
1144	s += '#define SEG_IOB_SIZE 0x%x\n' % seg_cma_size
1145	s += '\n'
1146	s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base
1147	s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size
1148	s += '\n'
1149	s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base
1150	s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size
1151	s += '\n'
1152	s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base
1153	s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size
1154	s += '\n'
1155	s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base
1156	s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size
1157	s += '\n'
1158	s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base
1159	s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size
1160	s += '\n'
1161	s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base
1162	s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size
1163	s += '\n'
1164	s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base
1165	s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size
1166	s += '\n'
1167	s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base
1168	s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size
1169	s += '\n'
1170	s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base
1171	s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size
1172	s += '\n'
1173	s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base
1174	s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size
1175	s += '\n'
1176	s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base
1177	s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size
1178	s += '\n'
1179	s += '#define VSEG_CLUSTER_INCREMENT 0x%x\n' % self.vseg_increment
1180	s += '\n'
1181
1182	s += '/* physical base addresses for identity mapped vsegs */\n'
1183	s += '/* used by the GietVM OS */\n'
1184	s += '\n'
1185	s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base
1186	s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size
1187	s += '\n'
1188	s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base
1189	s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size
1190	s += '\n'
1191	s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base
1192	s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size
1193	s += '\n'
1194	s += '#define SEG_BOOT_BUFFER_BASE 0x%x\n' % boot_buffer_base
1195	s += '#define SEG_BOOT_BUFFER_SIZE 0x%x\n' % boot_buffer_size
1196	s += '\n'
1197	s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base
1198	s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size
1199	s += '#endif\n'
1200
1201	return s
1202
1203	# end of hard_config()
1204
1205	#######################
1206	def netbsd_dts( self ): # compute string for netbsd.dts file generation,
1207	# used for netbsd configuration
1208	# header
1209	s = '/dts-v1/;\n'
1210	s += '\n'
1211	s += '/{\n'
1212	s += ' #address-cells = <2>;\n'
1213	s += ' #size-cells = <1>;\n'
1214
1215	# cpus (for each cluster)
1216	s += ' cpus {\n'
1217	s += ' #address-cells = <1>;\n'
1218	s += ' #size-cells = <0>;\n'
1219
1220	for cluster in self.clusters:
1221	for proc in cluster.procs:
1222	proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + proc.lpid
1223
1224	s += ' Mips,32@0x%x {\n' % proc_id
1225	s += ' device_type = "cpu";\n'
1226	s += ' icudev_type = "cpu:mips";\n'
1227	s += ' name = "Mips,32";\n'
1228	s += ' reg = <0x%x>;\n' % proc_id
1229	s += ' };\n'
1230	s += '\n'
1231
1232	s += ' };\n'
1233
1234	# rams (for each cluster)
1235	for cluster in self.clusters:
1236	for pseg in cluster.psegs:
1237
1238	if ( pseg.segtype == 'RAM' ):
1239	msb = pseg.base >> 32
1240	lsb = pseg.base & 0xFFFFFFFF
1241	size = pseg.size
1242
1243	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
1244	s += ' cached = <1>;\n'
1245	s += ' device_type = "memory";\n'
1246	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1247	s += ' };\n'
1248
1249	# peripherals (for each cluster)
1250	for cluster in self.clusters:
1251
1252	# research XCU component
1253	found_xcu = False
1254	for periph in cluster.periphs:
1255	if ( (periph.ptype == 'XCU') ):
1256	found_xcu = True
1257	xcu = periph
1258	msb = periph.pseg.base >> 32
1259	lsb = periph.pseg.base & 0xFFFFFFFF
1260	size = periph.pseg.size
1261
1262	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1263	s += ' device_type = "soclib:xicu:root";\n'
1264	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1265	s += ' input_lines = <%d>;\n' % periph.arg1
1266	s += ' ipis = <%d>;\n' % periph.arg2
1267	s += ' timers = <%d>;\n' % periph.arg3
1268
1269	output_id = 0 # output index from XCU
1270	for lpid in xrange ( len(cluster.procs) ): # destination processor index
1271	for itid in xrange ( self.irq_per_proc ): # input irq index on processor
1272	proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + lpid
1273	s += ' out@%d {\n' % output_id
1274	s += ' device_type = "soclib:xicu:filter";\n'
1275	s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid)
1276	s += ' output_line = <%d>;\n' % output_id
1277	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1278	s += ' };\n'
1279
1280	output_id += 1
1281
1282	s += ' };\n'
1283
1284	# research PIC component
1285	found_pic = False
1286	for periph in cluster.periphs:
1287	if ( periph.ptype == 'PIC' ):
1288	found_pic = True
1289	pic = periph
1290	msb = periph.pseg.base >> 32
1291	lsb = periph.pseg.base & 0xFFFFFFFF
1292	size = periph.pseg.size
1293
1294	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1295	s += ' device_type = "soclib:pic:root";\n'
1296	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1297	s += ' input_lines = <%d>;\n' % periph.channels
1298	s += ' };\n'
1299
1300	if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ):
1301	print 'error in netbsd_dts() : No XCU/PIC in cluster(%d,%d)' % (cluster.x, cluster.y)
1302	sys.exit(1)
1303
1304	if ( found_pic == True ): irq_tgt = pic
1305	else: irq_tgt = xcu
1306
1307	# get all others peripherals in cluster
1308	for periph in cluster.periphs:
1309	msb = periph.pseg.base >> 32
1310	lsb = periph.pseg.base & 0xFFFFFFFF
1311	size = periph.pseg.size
1312
1313	# research DMA component
1314	if ( periph.ptype == 'DMA' ):
1315
1316	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1317	s += ' device_type = "soclib:dma";\n'
1318	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1319	s += ' channel_count = <%d>;\n' % periph.channels
1320
1321	# multi-channels : get HWI index (to XCU) for each channel
1322	for channel in xrange( periph.channels ):
1323	hwi_id = 0xFFFFFFFF
1324	for irq in xcu.irqs:
1325	if ( (irq.isrtype == 'ISR_DMA') and (irq.channel == channel) ):
1326	hwi_id = irq.srcid
1327	if ( hwi_id == 0xFFFFFFFF ):
1328	print 'error in netbsd.dts() ISR_DMA channel %d not found' % channel
1329	sys.exit(1)
1330
1331	name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base)
1332	s += ' irq@%d{\n' % channel
1333	s += ' device_type = "soclib:periph:irq";\n'
1334	s += ' output_line = <%d>;\n' % channel
1335	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1336	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1337	s += ' };\n'
1338
1339	s += ' };\n'
1340
1341	# research MMC component
1342	elif ( periph.ptype == 'MMC' ):
1343
1344	# get irq line index associated to MMC in XCU
1345	irq_in = 0xFFFFFFFF
1346	for irq in xcu.irqs:
1347	if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid
1348	if ( irq_in == 0xFFFFFFFF ):
1349	print 'error in netbsd.dts() ISR_MMC not found'
1350	sys.exit(1)
1351
1352	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1353	s += ' device_type = "soclib:mmc";\n'
1354	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
1355	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1356	s += ' };\n'
1357
1358	# research FBF component
1359	elif ( periph.ptype == 'FBF' ):
1360
1361	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1362	s += ' device_type = "soclib:framebuffer";\n'
1363	s += ' mode = <32>;\n' # bits par pixel
1364	s += ' width = <%d>;\n' % periph.arg1
1365	s += ' height = <%d>;\n' % periph.arg2
1366	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1367	s += ' };\n'
1368
1369	# research IOC component
1370	elif ( periph.ptype == 'IOC' ):
1371
1372	if ( periph.subtype == 'BDV' ):
1373
1374	# get irq line index associated to bdv
1375	irq_in = 0xFFFFFFFF
1376	for irq in irq_tgt.irqs:
1377	if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid
1378	if ( irq_in == 0xFFFFFFFF ):
1379	print 'error in netbsd.dts() ISR_BDV not found'
1380	sys.exit(1)
1381
1382	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1383	s += ' device_type = "soclib:blockdevice";\n'
1384	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
1385	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1386	s += ' };\n'
1387
1388	elif ( periph.subtype == 'HBA' ):
1389	print 'error in netbsd_dts() : HBA peripheral not supported by NetBSD'
1390	sys.exit(1)
1391
1392	elif ( periph.subtype == 'SPI' ):
1393
1394	# get irq line index associated to spi
1395	irq_in = 0xFFFFFFFF
1396	for irq in irq_tgt.irqs:
1397	if ( irq.isrtype == 'ISR_SPI' ): irq_in = irq.srcid
1398	if ( irq_in == 0xFFFFFFFF ):
1399	print 'error in netbsd.dts() ISR_SPI not found'
1400	sys.exit(1)
1401
1402	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1403	s += ' device_type = "soclib:spi";\n'
1404	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
1405	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1406	s += ' };\n'
1407
1408	# research ROM component
1409	elif ( periph.ptype == 'ROM' ):
1410
1411	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1412	s += ' device_type = "rom";\n'
1413	s += ' cached = <1>;\n'
1414	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1415	s += ' };\n'
1416
1417	# research SIM component
1418	elif ( periph.ptype == 'SIM' ):
1419
1420	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1421	s += ' device_type = "soclib:simhelper";\n'
1422	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1423	s += ' };\n'
1424
1425	# research TTY component
1426	elif ( periph.ptype == 'TTY' ):
1427
1428	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1429	s += ' device_type = "soclib:tty";\n'
1430	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1431	s += ' channel_count = < %d >;\n' % periph.channels
1432
1433	# multi-channels : get HWI index (to XCU or PIC) for each channel
1434	for channel in xrange( periph.channels ):
1435	hwi_id = 0xFFFFFFFF
1436	for irq in irq_tgt.irqs:
1437	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ):
1438	hwi_id = irq.srcid
1439	if ( hwi_id == 0xFFFFFFFF ):
1440	print 'error in netbsd.dts() ISR_TTY_RX channel %d not found' % channel
1441	sys.exit(1)
1442
1443	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1444	s += ' irq@%d{\n' % channel
1445	s += ' device_type = "soclib:periph:irq";\n'
1446	s += ' output_line = <%d>;\n' % channel
1447	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1448	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1449	s += ' };\n'
1450
1451	s += ' };\n'
1452
1453	# research IOB component
1454	elif ( periph.ptype == 'IOB' ):
1455
1456	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1457	s += ' device_type = "soclib:iob";\n'
1458	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1459	s += ' };\n'
1460
1461	# research NIC component
1462	elif ( periph.ptype == 'NIC' ):
1463
1464	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1465	s += ' device_type = "soclib:nic";\n'
1466	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1467	s += ' channel_count = < %d >;\n' % periph.channels
1468
1469	# multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs
1470	# RX IRQ : (2channel) / TX IRQs : (2channel + 1)
1471	for channel in xrange( periph.channels ):
1472	hwi_id = 0xFFFFFFFF
1473	for irq in irq_tgt.irqs:
1474	if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ):
1475	hwi_id = irq.srcid
1476	if ( hwi_id == 0xFFFFFFFF ):
1477	print 'error in netbsd.dts() ISR_NIC_RX channel %d not found' % channel
1478	sys.exit(1)
1479
1480	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1481	s += ' irq_rx@%d{\n' % channel
1482	s += ' device_type = "soclib:periph:irq";\n'
1483	s += ' output_line = <%d>;\n' % (2*channel)
1484	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1485	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1486	s += ' };\n'
1487
1488	hwi_id = 0xFFFFFFFF
1489	for irq in irq_tgt.irqs:
1490	if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ):
1491	hwi_id = irq.srcid
1492	if ( hwi_id == 0xFFFFFFFF ):
1493	print 'error in netbsd.dts() ISR_NIC_TX channel %d not found' % channel
1494	sys.exit(1)
1495
1496	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1497	s += ' irq_tx@%d{\n' % channel
1498	s += ' device_type = "soclib:periph:irq";\n'
1499	s += ' output_line = <%d>;\n' % (2*channel + 1)
1500	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1501	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1502	s += ' };\n'
1503
1504	s += ' };\n'
1505
1506	# research CMA component
1507	elif ( periph.ptype == 'CMA' ):
1508
1509	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1510	s += ' device_type = "soclib:cma";\n'
1511	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1512	s += ' channel_count = < %d >;\n' % periph.channels
1513
1514	# multi-channels : get HWI index (to XCU or PIC) for each channel
1515	for channel in xrange( periph.channels ):
1516	hwi_id = 0xFFFFFFFF
1517	for irq in irq_tgt.irqs:
1518	if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ):
1519	hwi_id = irq.srcid
1520	if ( hwi_id == 0xFFFFFFFF ):
1521	print 'error in netbsd.dts() ISR_CMA channel %d not found' % channel
1522	sys.exit(1)
1523
1524	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1525	s += ' irq@%d{\n' % channel
1526	s += ' device_type = "soclib:periph:irq";\n'
1527	s += ' output_line = <%d>;\n' % channel
1528	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1529	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1530	s += ' };\n'
1531
1532	s += ' };\n'
1533
1534	# research TIM component
1535	elif ( periph.ptype == 'TIM' ):
1536
1537	print 'error in netbsd_dts() : TIM peripheral not supported by NetBSD'
1538	sys.exit(1)
1539
1540	# research MWR component
1541	elif ( periph.ptype == 'MWR' ):
1542
1543	print 'error in netbsd_dts() : MWR peripheral not supported by NetBSD'
1544	sys.exit(1)
1545
1546	# research ICU component
1547	elif ( periph.ptype == 'ICU' ):
1548	print 'error in netbsd_dts() : ICU peripheral not supported by NetBSD'
1549	sys.exit(1)
1550
1551	# topology
1552	s += '\n'
1553	s += ' topology {\n'
1554	s += ' #address-cells = <2>;\n'
1555	s += ' #size-cells = <0>;\n'
1556	for cluster in self.clusters:
1557	s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y)
1558	s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y)
1559	s += ' devices = <\n'
1560
1561	offset = ((cluster.x << self.y_width) + cluster.y) * self.procs_max
1562	for proc in cluster.procs:
1563	s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid)
1564	for periph in cluster.periphs:
1565	s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base)
1566
1567	s += ' >;\n'
1568	s += ' };\n'
1569	s += ' };\n'
1570	s += '};\n'
1571
1572	return s
1573	# end netbsd_dts( )
1574
1575	###########################
1576	def almos_archinfo( self ): # compute string for arch.info file generation,
1577	# used for almos configuration
1578	# header
1579	s = '# arch.info file generated by tsarmap for %s\n' % self.name
1580	s += '\n'
1581	s += '[HEADER]\n'
1582	s += ' REVISION=1\n'
1583	s += ' ARCH=%s\n' % self.name
1584	s += ' XMAX=%d\n' % self.x_size
1585	s += ' YMAX=%d\n' % self.y_size
1586	s += ' CPU_NR=%d\n' % self.procs_max
1587	s += '\n'
1588
1589	# clusters
1590	cluster_id = 0
1591	for cluster in self.clusters:
1592
1593	ram = None
1594	nb_cpus = len( cluster.procs )
1595	nb_devs = len( cluster.periphs )
1596	if ( len( cluster.coprocs ) != 0 ):
1597	print 'Error in almos_archinfo() coprocessors not supported yet'
1598	sys.exit(1)
1599
1600	# search a RAM
1601	for pseg in cluster.psegs:
1602	if ( pseg.segtype == 'RAM' ):
1603	ram = pseg
1604	nb_devs += 1
1605
1606	# search XCU to get IRQs indexes if cluster contains peripherals
1607	if ( len( cluster.periphs ) != 0 ):
1608	tty_irq_id = None
1609	bdv_irq_id = None
1610	dma_irq_id = None
1611
1612	for periph in cluster.periphs:
1613	if ( periph.ptype == 'XCU' ):
1614	# scan irqs
1615	for irq in periph.irqs:
1616	if ( irq.isrtype == 'ISR_TTY_RX' ) : tty_irq_id = irq.srcid
1617	if ( irq.isrtype == 'ISR_BDV' ) : bdv_irq_id = irq.srcid
1618	if ( irq.isrtype == 'ISR_DMA' ) : dma_irq_id = irq.srcid
1619
1620	# Build the cluster description
1621	s += '[CLUSTER]\n'
1622	s += ' CID=%d\n' % cluster_id
1623	s += ' ARCH_CID=0x%x\n' % ((cluster.x << self.y_width) + cluster.y)
1624	s += ' CPU_NR=%d\n' % nb_cpus
1625	s += ' DEV_NR=%d\n' % nb_devs
1626
1627
1628	# Handling RAM when cluster contain a RAM
1629	if (ram != None ):
1630	base = ram.base
1631	size = ram.size
1632	irqid = -1
1633	s += ' DEVID=RAM'
1634	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1635
1636	# Handling peripherals
1637	for periph in cluster.periphs:
1638	base = periph.pseg.base
1639	size = periph.pseg.size
1640
1641	if ( periph.ptype == 'XCU' ):
1642
1643	s += ' DEVID=XICU'
1644	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1645
1646	elif ( (periph.ptype == 'TTY')
1647	and (tty_irq_id != None) ):
1648
1649	s += ' DEVID=TTY'
1650	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, tty_irq_id )
1651
1652	elif ( (periph.ptype == 'DMA')
1653	and (dma_irq_id != None) ):
1654
1655	s += ' DEVID=DMA'
1656	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, dma_irq_id )
1657
1658	elif ( periph.ptype == 'FBF' ):
1659
1660	s += ' DEVID=FB'
1661	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1662
1663	elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV')
1664	and (bdv_irq_id != None) ):
1665
1666	s += ' DEVID=BLKDEV'
1667	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, bdv_irq_id )
1668
1669	elif ( periph.ptype == 'PIC' ):
1670
1671	s += ' DEVID=IOPIC'
1672	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1673
1674	else:
1675	print '# Warning from almos_archinfo() in cluster[%d,%d]' \
1676	% (cluster.x, cluster.y)
1677	print '# peripheral type %s/%s not supported yet\n' \
1678	% ( periph.ptype, periph.subtype )
1679
1680	cluster_id += 1
1681
1682	return s
1683
1684	# end of almos_archinfo()
1685
1686
1687
1688
1689
1690
1691
1692
1693	###########################################################################################
1694	class Cluster ( object ):
1695	###########################################################################################
1696	def __init__( self,
1697	x,
1698	y ):
1699
1700	self.index = 0 # global index (set by Mapping constructor)
1701	self.x = x # x coordinate
1702	self.y = y # y coordinate
1703	self.psegs = [] # filled by addRam() or addPeriph()
1704	self.procs = [] # filled by addProc()
1705	self.coprocs = [] # filled by addCoproc()
1706	self.periphs = [] # filled by addPeriph()
1707
1708	return
1709
1710	################
1711	def xml( self ): # xml for a cluster
1712
1713	s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y)
1714	for pseg in self.psegs: s += pseg.xml()
1715	for proc in self.procs: s += proc.xml()
1716	for copr in self.coprocs: s += copr.xml()
1717	for peri in self.periphs: s += peri.xml()
1718	s += ' </cluster>\n'
1719
1720	return s
1721
1722	#############################################
1723	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
1724
1725	if ( verbose ):
1726	print '*** cbin for cluster [%d,%d]' % (self.x, self.y)
1727
1728	# check index
1729	if (self.index != expected):
1730	print 'error in Cluster.cbin() : cluster global index = %d / expected = %d' \
1731	% (self.index, expected )
1732	sys.exit(1)
1733
1734	# compute global index for first pseg
1735	if ( len(self.psegs) > 0 ):
1736	pseg_id = self.psegs[0].index
1737	else:
1738	pseg_id = 0
1739
1740	# compute global index for first proc
1741	if ( len(self.procs) > 0 ):
1742	proc_id = self.procs[0].index
1743	else:
1744	proc_id = 0
1745
1746	# compute global index for first coproc
1747	if ( len(self.coprocs) > 0 ):
1748	coproc_id = self.coprocs[0].index
1749	else:
1750	coproc_id = 0
1751
1752	# compute global index for first periph
1753	if ( len(self.periphs) > 0 ):
1754	periph_id = self.periphs[0].index
1755	else:
1756	periph_id = 0
1757
1758	byte_stream = bytearray()
1759	byte_stream += mapping.int2bytes( 4 , self.x ) # x coordinate
1760	byte_stream += mapping.int2bytes( 4 , self.y ) # x coordinate
1761	byte_stream += mapping.int2bytes( 4 , len( self.psegs ) ) # number of psegs in cluster
1762	byte_stream += mapping.int2bytes( 4 , pseg_id ) # first pseg global index
1763	byte_stream += mapping.int2bytes( 4 , len( self.procs ) ) # number of procs in cluster
1764	byte_stream += mapping.int2bytes( 4 , proc_id ) # first proc global index
1765	byte_stream += mapping.int2bytes( 4 , len( self.coprocs ) ) # number of coprocs in cluster
1766	byte_stream += mapping.int2bytes( 4 , coproc_id ) # first coproc global index
1767	byte_stream += mapping.int2bytes( 4 , len( self.periphs ) ) # number of periphs in cluster
1768	byte_stream += mapping.int2bytes( 4 , periph_id ) # first periph global index
1769
1770	if ( verbose ):
1771	print 'nb_psegs = %d' % len( self.psegs )
1772	print 'pseg_id = %d' % pseg_id
1773	print 'nb_procs = %d' % len( self.procs )
1774	print 'proc_id = %d' % proc_id
1775	print 'nb_coprocs = %d' % len( self.coprocs )
1776	print 'coproc_id = %d' % coproc_id
1777	print 'nb_periphs = %d' % len( self.periphs )
1778	print 'periph_id = %d' % periph_id
1779
1780	return byte_stream
1781
1782	###########################################################################################
1783	class Vspace( object ):
1784	###########################################################################################
1785	def __init__( self,
1786	name,
1787	startname ):
1788
1789	self.index = 0 # global index ( set by addVspace() )
1790	self.name = name # vspace name
1791	self.startname = startname # name of vobj containing the start_vector
1792	self.vsegs = []
1793	self.tasks = []
1794
1795	return
1796
1797	################
1798	def xml( self ): # xml for one vspace
1799
1800	s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname )
1801	for vseg in self.vsegs: s += vseg.xml()
1802	for task in self.tasks: s += task.xml()
1803	s += ' </vspace>\n'
1804
1805	return s
1806
1807	#############################################
1808	def cbin( self, mapping, verbose, expected ): # C binary structure for Vspace
1809
1810	if ( verbose ):
1811	print '*** cbin for vspace %s' % (self.name)
1812
1813	# check index
1814	if (self.index != expected):
1815	print 'error in Vspace.cbin() : vspace global index = %d / expected = %d' \
1816	% (self.index, expected )
1817	sys.exit(1)
1818
1819	# compute global index for vobj containing start_vector
1820	vobj_start_id = 0xFFFFFFFF
1821	for vseg in self.vsegs:
1822	if ( vseg.vobjs[0].name == self.startname ):
1823	vobj_start_id = vseg.vobjs[0].index
1824	if ( vobj_start_id == 0xFFFFFFFF ):
1825	print 'error in Vspace.cbin() : startname %s not found for vspace %s' \
1826	% ( self.startname, self.name )
1827	sys.exit(1)
1828
1829	# compute first vseg, vobj, task global index
1830	first_vseg_id = self.vsegs[0].index
1831	first_vobj_id = self.vsegs[0].vobjs[0].index
1832	first_task_id = self.tasks[0].index
1833
1834	# compute number of vobjs, tasks, vsegs
1835	nb_vsegs = len( self.vsegs )
1836	nb_tasks = len( self.tasks )
1837	nb_vobjs = 0
1838	for vseg in self.vsegs:
1839	nb_vobjs += len( vseg.vobjs )
1840
1841	byte_stream = bytearray()
1842	byte_stream += mapping.str2bytes( 32, self.name ) # vspace name
1843	byte_stream += mapping.int2bytes( 4, vobj_start_id ) # vobj start_vector
1844	byte_stream += mapping.int2bytes( 4, nb_vsegs ) # number of vsegs
1845	byte_stream += mapping.int2bytes( 4, nb_vobjs ) # number of vobjs
1846	byte_stream += mapping.int2bytes( 4, nb_tasks ) # number of tasks
1847	byte_stream += mapping.int2bytes( 4, first_vseg_id ) # first vseg global index
1848	byte_stream += mapping.int2bytes( 4, first_vobj_id ) # first vobj global index
1849	byte_stream += mapping.int2bytes( 4, first_task_id ) # first task global index
1850
1851	if ( verbose ):
1852	print 'start_id = %d' % vobj_start_id
1853	print 'nb_vsegs = %d' % nb_vsegs
1854	print 'nb_vobjs = %d' % nb_vobjs
1855	print 'nb_tasks = %d' % nb_tasks
1856	print 'vseg_id = %d' % first_vseg_id
1857	print 'vobj_id = %d' % first_vobj_id
1858	print 'task_id = %d' % first_task_id
1859
1860	return byte_stream
1861
1862	###########################################################################################
1863	class Task( object ):
1864	###########################################################################################
1865	def __init__( self,
1866	name,
1867	trdid,
1868	x,
1869	y,
1870	p,
1871	stackname,
1872	heapname,
1873	startid,
1874	usetty = False,
1875	usenic = False,
1876	usecma = False,
1877	usehba = False,
1878	usetim = False ):
1879
1880	self.index = 0 # global index value set by addTask()
1881	self.name = name # tsk name
1882	self.trdid = trdid # task index (unique in vspace)
1883	self.x = x # cluster x coordinate
1884	self.y = y # cluster y coordinate
1885	self.p = p # processor local index
1886	self.stackname = stackname # name of vobj containing the stack
1887	self.heapname = heapname # name of vobj containing the heap
1888	self.startid = startid # index in start_vector
1889	self.usetty = usetty # request a private TTY channel
1890	self.usenic = usenic # request a private NIC channel
1891	self.usecma = usecma # request a private CMA channel
1892	self.usehba = usehba # request a private HBA channel
1893	self.usetim = usetim # request a private TIM channel
1894	return
1895
1896	################
1897	def xml( self ): # xml for one task
1898
1899	s = ' <task name="%s"' % self.name
1900	s += ' trdid="%d"' % self.trdid
1901	s += ' x="%d"' % self.x
1902	s += ' y="%d"' % self.y
1903	s += ' p="%d"' % self.p
1904	s += ' stackname="%s"' % self.stackname
1905	s += ' heapname="%s"' % self.heapname
1906	s += ' startid="%d"' % self.startid
1907	if self.usetty != 0: s += ' usetty="1"'
1908	if self.usenic != 0: s += ' usenic="1"'
1909	if self.usecma != 0: s += ' usehba="1"'
1910	if self.usehba != 0: s += ' usehba="1"'
1911	if self.usetim != 0: s += ' usehba="1"'
1912	s += ' />\n'
1913
1914	return s
1915
1916	#####################################################
1917	def cbin( self, mapping, verbose, expected, vspace ): # C binary data structure for Task
1918
1919	if ( verbose ):
1920	print '*** cbin for task %s in vspace %s' % (self.name, vspace.name)
1921
1922	# check index
1923	if (self.index != expected):
1924	print 'error in Task.cbin() : task global index = %d / expected = %d' \
1925	% (self.index, expected )
1926	sys.exit(1)
1927
1928	# compute cluster global index
1929	cluster_id = (self.x * mapping.y_size) + self.y
1930
1931	# compute vobj local index for stack
1932	vobj_stack_id = 0xFFFFFFFF
1933	for vseg in vspace.vsegs:
1934	if ( vseg.vobjs[0].name == self.stackname ):
1935	vobj_stack_id = vseg.vobjs[0].index
1936	if ( vobj_stack_id == 0xFFFFFFFF ):
1937	print 'error in Task.cbin() : stackname %s not found for task %s in vspace %s' \
1938	% ( self.stackname, self.name, vspace.name )
1939	sys.exit(1)
1940
1941	# compute vobj local index for heap
1942	vobj_heap_id = 0xFFFFFFFF
1943	for vseg in vspace.vsegs:
1944	if ( vseg.vobjs[0].name == self.heapname ):
1945	vobj_heap_id = vseg.vobjs[0].index
1946	if ( vobj_heap_id == 0xFFFFFFFF ):
1947	print 'error in Task.cbin() : heapname %s not found for task %s in vspace %s' \
1948	% ( self.heapname, self.name, vspace.name )
1949	sys.exit(1)
1950
1951	byte_stream = bytearray()
1952	byte_stream += mapping.str2bytes( 32, self.name ) # task name in vspace
1953	byte_stream += mapping.int2bytes( 4, cluster_id ) # cluster global index
1954	byte_stream += mapping.int2bytes( 4, self.p ) # processor local index in cluster
1955	byte_stream += mapping.int2bytes( 4, self.trdid ) # thread local index in vspace
1956	byte_stream += mapping.int2bytes( 4, vobj_stack_id ) # stack vobj local index
1957	byte_stream += mapping.int2bytes( 4, vobj_heap_id ) # heap vobj local index
1958	byte_stream += mapping.int2bytes( 4, self.startid ) # index in start vector
1959	byte_stream += mapping.int2bytes( 4, self.usetty ) # TTY channel required
1960	byte_stream += mapping.int2bytes( 4, self.usenic ) # NIC channel required
1961	byte_stream += mapping.int2bytes( 4, self.usecma ) # CMA channel required
1962	byte_stream += mapping.int2bytes( 4, self.usehba ) # IOC channel required
1963	byte_stream += mapping.int2bytes( 4, self.usetim ) # TIM channel required
1964
1965	if ( verbose ):
1966	print 'clusterid = %d' % cluster_id
1967	print 'lpid = %d' % self.p
1968	print 'trdid = %d' % self.trdid
1969	print 'stackid = %d' % vobj_stack_id
1970	print 'heapid = %d' % vobj_heap_id
1971	print 'startid = %d' % self.startid
1972
1973	return byte_stream
1974
1975	###########################################################################################
1976	class Vseg( object ):
1977	###########################################################################################
1978	def __init__( self,
1979	name,
1980	vbase,
1981	mode,
1982	x,
1983	y,
1984	psegname,
1985	ident = False ):
1986
1987	assert mode in VSEGMODES
1988
1989	self.index = 0 # global index ( set by addVseg() )
1990	self.name = name # vseg name
1991	self.vbase = vbase & 0xFFFFFFFF # virtual base address in vspace
1992	self.mode = mode # CXWU access rights
1993	self.x = x # x coordinate of destination cluster
1994	self.y = y # y coordinate of destination cluster
1995	self.psegname = psegname # name of pseg in destination cluster
1996	self.ident = ident # identity mapping required
1997	self.vobjs = []
1998	return
1999
2000	################
2001	def xml( self ): # xml for one vseg
2002
2003	s = ' <vseg name="%s" vbase="0x%x" mode="%s" x="%d" y="%d" psegname="%s"' \
2004	% ( self.name, self.vbase, self.mode, self.x, self.y, self.psegname )
2005	if ( self.ident ): s += ' ident="1" >\n'
2006	else: s += ' >\n'
2007	for vobj in self.vobjs: s += vobj.xml()
2008	s += ' </vseg>\n'
2009
2010	return s
2011
2012	#############################################
2013	def cbin( self, mapping, verbose, expected ): # C binary structure for Vseg
2014
2015	if ( verbose ):
2016	print '*** cbin for vseg[%d] %s' % (self.index, self.name)
2017
2018	# check index
2019	if (self.index != expected):
2020	print 'error in Vseg.cbin() : vseg global index = %d / expected = %d' \
2021	% (self.index, expected )
2022	sys.exit(1)
2023
2024	# compute pseg_id
2025	pseg_id = 0xFFFFFFFF
2026	cluster_id = (self.x * mapping.y_size) + self.y
2027	cluster = mapping.clusters[cluster_id]
2028	for pseg in cluster.psegs:
2029	if (self.psegname == pseg.name):
2030	pseg_id = pseg.index
2031	if (pseg_id == 0xFFFFFFFF):
2032	print 'error in Vseg.cbin() : psegname %s not found for vseg %s in cluster %d' \
2033	% ( self.psegname, self.name, cluster_id )
2034	sys.exit(1)
2035
2036	# compute numerical value for mode
2037	mode_id = 0xFFFFFFFF
2038	for x in xrange( len(VSEGMODES) ):
2039	if ( self.mode == VSEGMODES[x] ):
2040	mode_id = x
2041	if ( mode_id == 0xFFFFFFFF ):
2042	print 'error in Vseg.cbin() : undefined vseg mode %s' % self.mode
2043	sys.exit(1)
2044
2045	# compute vobj_id
2046	vobj_id = self.vobjs[0].index
2047
2048	byte_stream = bytearray()
2049	byte_stream += mapping.str2bytes( 32, self.name ) # vseg name
2050	byte_stream += mapping.int2bytes( 4, self.vbase ) # virtual base address
2051	byte_stream += mapping.int2bytes( 8, 0 ) # physical base address
2052	byte_stream += mapping.int2bytes( 4, 0 ) # vseg size (bytes)
2053	byte_stream += mapping.int2bytes( 4, pseg_id ) # physical segment global index
2054	byte_stream += mapping.int2bytes( 4, mode_id ) # CXWU flags
2055	byte_stream += mapping.int2bytes( 4, len(self.vobjs) ) # number of vobjs in vseg
2056	byte_stream += mapping.int2bytes( 4, vobj_id ) # first vobj global index
2057	byte_stream += mapping.int2bytes( 4, 0 ) # linked list of vsegs on same pseg
2058	byte_stream += mapping.int2bytes( 1, 0 ) # mapped when non zero
2059	byte_stream += mapping.int2bytes( 1, self.ident ) # identity mapping when non zero
2060	byte_stream += mapping.int2bytes( 2, 0 ) # reserved (padding)
2061
2062	if ( verbose ):
2063	print 'vbase = %x' % self.vbase
2064	print 'pseg_id = %d' % pseg_id
2065	print 'mode = %s' % self.mode
2066	print 'nb_vobjs = %d' % len(self.vobjs)
2067	print 'vobj_id = %d' % vobj_id
2068
2069	return byte_stream
2070
2071	###########################################################################################
2072	class Vobj( object ):
2073	###########################################################################################
2074	def __init__( self,
2075	name,
2076	length,
2077	vtype,
2078	binpath = '',
2079	align = 0,
2080	init = 0 ):
2081
2082	assert vtype in ['ELF','BLOB','PTAB','PERI','MWMR','LOCK', \
2083	'BUFFER','BARRIER','CONST','MEMSPACE','SCHED']
2084
2085	assert (vtype != 'ELF') or (binpath != '')
2086
2087	self.index = 0 # global index ( set by addVobj() )
2088	self.name = name # vobj name (unique in vspace)
2089	self.vtype = vtype # vobj type (defined in mapping_info.h)
2090	self.length = length # vobj size (bytes)
2091	self.binpath = binpath # pathname for (ELF type)
2092	self.align = align # required alignment (logarithm of 2)
2093	self.init = init # initialisation value (for BARRIER or MWMR types)
2094
2095	return
2096
2097	################
2098	def xml( self ): # xml for a vobj
2099
2100	s = ' <vobj name="%s" type="%s" length="0x%x"' \
2101	% ( self.name, self.vtype, self.length )
2102	if (self.binpath != ''): s += ' binpath="%s"' % (self.binpath)
2103	if (self.align != 0 ): s += ' align="%d"' % (self.align)
2104	if (self.init != 0 ): s += ' init="%d"' % (self.init)
2105	s += ' />\n'
2106
2107	return s
2108
2109	#############################################
2110	def cbin( self, mapping, verbose, expected ): # C binary structure for Vobj
2111
2112	# check index
2113	if (self.index != expected):
2114	print 'error in Vobj.cbin() : vobj global index = %d / expected = %d' \
2115	% (self.index, expected )
2116	sys.exit(1)
2117	elif ( verbose ):
2118	print '*** cbin for vobj[%d] %s' % (self.index, self.name)
2119
2120	# compute numerical value for vtype
2121	vtype_int = 0xFFFFFFFF
2122	for x in xrange( len(VOBJTYPES) ):
2123	if ( self.vtype == VOBJTYPES[x] ):
2124	vtype_int = x
2125	if ( vtype_int == 0xFFFFFFFF ):
2126	print 'error in Vobj.cbin() : undefined vobj type %s' % self.vtype
2127	sys.exit(1)
2128
2129	byte_stream = bytearray()
2130	byte_stream += mapping.str2bytes( 32, self.name ) # vobj name
2131	byte_stream += mapping.str2bytes( 64, self.binpath ) # pathname for .elf file
2132	byte_stream += mapping.int2bytes( 4 , vtype_int ) # vobj type
2133	byte_stream += mapping.int2bytes( 4 , self.length ) # vobj size
2134	byte_stream += mapping.int2bytes( 4 , self.align ) # required alignment
2135	byte_stream += mapping.int2bytes( 4 , 0 ) # virtual base address
2136	byte_stream += mapping.int2bytes( 8 , 0 ) # physical base address
2137	byte_stream += mapping.int2bytes( 4 , self.init ) # init value
2138
2139	if ( verbose ):
2140	print 'binpath = %s' % self.binpath
2141	print 'type = %s' % self.vtype
2142	print 'length = %x' % self.length
2143
2144	return byte_stream
2145
2146	###########################################################################################
2147	class Processor ( object ):
2148	###########################################################################################
2149	def __init__( self,
2150	x,
2151	y,
2152	lpid ):
2153
2154	self.index = 0 # global index ( set by addProc() )
2155	self.x = x # x cluster coordinate
2156	self.y = y # y cluster coordinate
2157	self.lpid = lpid # processor local index
2158
2159	return
2160
2161	################
2162	def xml( self ): # xml for a processor
2163	return ' <proc index="%d" />\n' % (self.lpid)
2164
2165	#############################################
2166	def cbin( self, mapping, verbose, expected ): # C binary structure for Proc
2167
2168	if ( verbose ):
2169	print '*** cbin for proc %d in cluster (%d,%d)' % (self.lpid, self.x, self.y)
2170
2171	# check index
2172	if (self.index != expected):
2173	print 'error in Proc.cbin() : proc global index = %d / expected = %d' \
2174	% (self.index, expected )
2175	sys.exit(1)
2176
2177	byte_stream = bytearray()
2178	byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index
2179
2180	return byte_stream
2181
2182	###########################################################################################
2183	class Pseg ( object ):
2184	###########################################################################################
2185	def __init__( self,
2186	name,
2187	base,
2188	size,
2189	x,
2190	y,
2191	segtype ):
2192
2193	assert( segtype in PSEGTYPES )
2194
2195	self.index = 0 # global index ( set by addPseg() )
2196	self.name = name # pseg name (unique in cluster)
2197	self.base = base # physical base address
2198	self.size = size # segment size (bytes)
2199	self.x = x # cluster x coordinate
2200	self.y = y # cluster y coordinate
2201	self.segtype = segtype # RAM / PERI (defined in mapping_info.h)
2202
2203	return
2204
2205	################
2206	def xml( self ): # xml for a pseg
2207
2208	return ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \
2209	% (self.name, self.segtype, self.base, self.size)
2210
2211	######################################################
2212	def cbin( self, mapping, verbose, expected, cluster ): # C binary structure for Pseg
2213
2214	if ( verbose ):
2215	print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \
2216	% (self.index, self.name, cluster.x, cluster.y)
2217
2218	# check index
2219	if (self.index != expected):
2220	print 'error in Pseg.cbin() : pseg global index = %d / expected = %d' \
2221	% (self.index, expected )
2222	sys.exit(1)
2223
2224	# compute numerical value for segtype
2225	segtype_int = 0xFFFFFFFF
2226	for x in xrange( len(PSEGTYPES) ):
2227	if ( self.segtype == PSEGTYPES[x] ):
2228	segtype_int = x
2229	if ( segtype_int == 0xFFFFFFFF ):
2230	print 'error in Pseg.cbin() : undefined segment type %s' % self.segtype
2231	sys.exit(1)
2232
2233	byte_stream = bytearray()
2234	byte_stream += mapping.str2bytes( 32, self.name ) # pseg name
2235	byte_stream += mapping.int2bytes( 8 , self.base ) # physical base address
2236	byte_stream += mapping.int2bytes( 8 , self.size ) # segment length
2237	byte_stream += mapping.int2bytes( 4 , segtype_int ) # segment type
2238	byte_stream += mapping.int2bytes( 4 , cluster.index ) # cluster global index
2239	byte_stream += mapping.int2bytes( 4 , 0 ) # linked list of vsegs
2240
2241	if ( verbose ):
2242	print 'pbase = %x' % self.base
2243	print 'size = %x' % self.size
2244	print 'type = %s' % self.segtype
2245
2246	return byte_stream
2247
2248	###########################################################################################
2249	class Periph ( object ):
2250	###########################################################################################
2251	def __init__( self,
2252	pseg, # associated pseg
2253	ptype, # peripheral type
2254	subtype = 'NONE', # peripheral subtype
2255	channels = 1, # for multi-channels peripherals
2256	arg = 0 ): # optional argument (semantic depends on ptype)
2257
2258	assert ptype in PERIPHTYPES
2259
2260	assert subtype in PERIPHSUBTYPES
2261
2262	self.index = 0 # global index ( set by addPeriph() )
2263	self.channels = channels
2264	self.ptype = ptype
2265	self.subtype = subtype
2266	self.arg = arg
2267	self.pseg = pseg
2268	self.irqs = []
2269	return
2270
2271	################
2272	def xml( self ): # xml for a periph
2273
2274	s = ' <periph type="%s"' % self.ptype
2275	s += ' subtype="%s"' % self.subtype
2276	s += ' psegname="%s"' % self.pseg.name
2277	s += ' channels="%d"' % self.channels
2278	s += ' arg="%d" >\n' % self.arg
2279	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') or (self.ptype == 'ICU') ):
2280	for irq in self.irqs: s += irq.xml()
2281	s += ' </periph>\n'
2282
2283	return s
2284
2285	#############################################
2286	def cbin( self, mapping, verbose, expected ): # C binary structure for Periph
2287
2288	if ( verbose ):
2289	print '*** cbin for periph %s in cluster [%d,%d]' \
2290	% (self.ptype, self.pseg.x, self.pseg.y)
2291
2292	# check index
2293	if (self.index != expected):
2294	print 'error in Periph.cbin() : periph global index = %d / expected = %d' \
2295	% (self.index, expected )
2296	sys.exit(1)
2297
2298	# compute pseg global index
2299	pseg_id = self.pseg.index
2300
2301	# compute first irq global index
2302	if ( len(self.irqs) > 0 ):
2303	irq_id = self.irqs[0].index
2304	else:
2305	irq_id = 0
2306
2307	# compute numerical value for ptype
2308	ptype_id = 0xFFFFFFFF
2309	for x in xrange( len(PERIPHTYPES) ):
2310	if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x
2311	if ( ptype_id == 0xFFFFFFFF ):
2312	print 'error in Periph.cbin() : undefined peripheral type %s' % self.ptype
2313	sys.exit(1)
2314
2315	# compute numerical value for subtype
2316	subtype_id = 0xFFFFFFFF
2317	for x in xrange( len(PERIPHSUBTYPES) ):
2318	if ( self.subtype == PERIPHSUBTYPES[x] ): subtype_id = x
2319
2320	# compute
2321	byte_stream = bytearray()
2322	byte_stream += mapping.int2bytes( 4 , ptype_id ) # peripheral type
2323	byte_stream += mapping.int2bytes( 4 , subtype_id ) # peripheral subtype
2324	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
2325	byte_stream += mapping.int2bytes( 4 , self.channels ) # number of channels
2326	byte_stream += mapping.int2bytes( 4 , self.arg ) # optionnal argument
2327	byte_stream += mapping.int2bytes( 4 , len( self.irqs ) ) # number of input irqs
2328	byte_stream += mapping.int2bytes( 4 , irq_id ) # first irq global index
2329
2330	if ( verbose ):
2331	print 'ptype = %d' % ptype_id
2332	print 'pseg_id = %d' % pseg_id
2333	print 'nb_irqs = %d' % len( self.irqs )
2334	print 'irq_id = %d' % irq_id
2335	return byte_stream
2336
2337	###########################################################################################
2338	class Irq ( object ):
2339	###########################################################################################
2340	def __init__( self,
2341	irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only)
2342	srcid, # input IRQ index (for XCU or PIC)
2343	isrtype, # Type of ISR to be executed
2344	channel = 0 ): # channel index for multi-channel ISR
2345
2346	assert irqtype in IRQTYPES
2347	assert isrtype in ISRTYPES
2348	assert srcid < 32
2349
2350	self.index = 0 # global index ( set by addIrq() )
2351	self.irqtype = irqtype # IRQ type
2352	self.srcid = srcid # source IRQ index
2353	self.isrtype = isrtype # ISR type
2354	self.channel = channel # channel index (for multi-channels ISR)
2355	return
2356
2357	################
2358	def xml( self ): # xml for Irq
2359
2360	return ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \
2361	% ( self.irqtype, self.srcid, self.isrtype, self.channel )
2362
2363	#############################################
2364	def cbin( self, mapping, verbose, expected ): # C binary structure for Irq
2365
2366	if ( verbose ):
2367	print '*** cbin for irq[%d]' % (self.index)
2368
2369	# check index
2370	if (self.index != expected):
2371	print 'error in Irq.cbin() : irq global index = %d / expected = %d' \
2372	% (self.index, expected )
2373	sys.exit(1)
2374
2375	# compute numerical value for irqtype
2376	irqtype_id = 0xFFFFFFFF
2377	for x in xrange( len(IRQTYPES) ):
2378	if ( self.irqtype == IRQTYPES[x] ):
2379	irqtype_id = x
2380	if ( irqtype_id == 0xFFFFFFFF ):
2381	print 'error in Irq.cbin() : undefined irqtype %s' % self.irqtype
2382	sys.exit(1)
2383
2384	# compute numerical value for isrtype
2385	isrtype_id = 0xFFFFFFFF
2386	for x in xrange( len(ISRTYPES) ):
2387	if ( self.isrtype == ISRTYPES[x] ):
2388	isrtype_id = x
2389	if ( isrtype_id == 0xFFFFFFFF ):
2390	print 'error in Irq.cbin() : undefined isrtype %s' % self.isrtype
2391	sys.exit(1)
2392
2393	byte_stream = bytearray()
2394	byte_stream += mapping.int2bytes( 4, irqtype_id )
2395	byte_stream += mapping.int2bytes( 4, self.srcid )
2396	byte_stream += mapping.int2bytes( 4, isrtype_id )
2397	byte_stream += mapping.int2bytes( 4, self.channel )
2398	byte_stream += mapping.int2bytes( 4, 0 )
2399	byte_stream += mapping.int2bytes( 4, 0 )
2400
2401	if ( verbose ):
2402	print 'irqtype = %s' % self.irqtype
2403	print 'srcid = %d' % self.srcid
2404	print 'isrtype = %s' % self.isrtype
2405	print 'channel = %d' % self.channel
2406
2407	return byte_stream
2408
2409	###########################################################################################
2410	class Coproc ( object ):
2411	###########################################################################################
2412	def __init__( self,
2413	pseg ): # associated pseg
2414
2415	self.index = 0 # global index value set by addCoproc()
2416	self.pseg = pseg
2417	self.ports = []
2418
2419	return
2420
2421	################
2422	def xml( self ): # xml for Coproc
2423
2424	print 'error in Coproc.xml() : not defined yet'
2425	sys.exit(1)
2426
2427	return
2428
2429	#############################################
2430	def cbin( self, mapping, verbose, expected ): # C binary structure for Coproc
2431
2432	if ( verbose ):
2433	print '*** cbin for coproc in cluster (%d,%d)' % (self.pseg.x, self.pseg.y)
2434
2435	# check index
2436	if (self.index != expected):
2437	print 'error in Coproc.cbin() : coproc global index = %d / expected = %d' \
2438	% (self.index, expected )
2439	sys.exit(1)
2440
2441	# compute pseg global index
2442	pseg_id = self.pseg.index
2443
2444	# compute first port global index
2445	port_id = self.ports[0].index
2446
2447	byte_stream = bytearray()
2448	byte_stream += mapping.str2bytes( 32, self.pseg.name ) # probablement inutile (AG)
2449	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
2450	byte_stream += mapping.int2bytes( 4 , len( self.ports ) ) # number of input irqs
2451	byte_stream += mapping.int2bytes( 4 , port_id ) # first port global index
2452
2453	if ( verbose ):
2454	print 'irqtype = %s' % self.irqtype
2455	print 'pseg_id = %d' % pseg_id
2456	print 'nb_ports = %d' % len( self.ports )
2457	print 'port_id %d' % port_id
2458
2459	return byte_stream
2460
2461	###########################################################################################
2462	class Cpport ( object ):
2463	###########################################################################################
2464	def __init__( self,
2465	direction,
2466	vspacename,
2467	mwmrname ):
2468
2469	self.index = 0 # global index ( set by addCpport() )
2470	self.direction = direction # TO_COPROC / FROM_COPROC
2471	self.vspacename = vspacename # name of vspace containing mwmr channel
2472	self.mwmrname = mwmrname # name of vobj defining mwmr channel
2473
2474	return
2475
2476	################
2477	def xml( self ): # xml for Cpport
2478
2479	print 'error in Cpport.xml() : not defined yet'
2480	sys.exit(1)
2481
2482	return
2483
2484	#############################################
2485	def cbin( self, mapping, verbose, expected ): # C binary structure for Cpport
2486
2487	if ( verbose ):
2488	print '*** cbin for cpport[%d]' % (self.index)
2489
2490	# check index
2491	if ( self.index != expected ):
2492	print 'error in Cpport.cbin() : port global index = %d / expected = %d' \
2493	% ( self.index, expected )
2494	sys.exit(1)
2495
2496	# compute numerical value for direction
2497	if ( self.direction == 'TO_COPROC' ):
2498	dir_int = 0
2499	else:
2500	dir_int = 1
2501
2502	# compute vspace global index
2503	vspace_id = 0xFFFFFFFF
2504	for vspace in mapping.vspaces:
2505	if ( self.vspacename == vspace.name ):
2506	vspace_id = vspace.index
2507	if (vspace_id == 0xFFFFFFFF):
2508	print 'error in Cpport.cbin() : vspace name %s not found' \
2509	% ( self.vspacename )
2510	sys.exit(1)
2511
2512	# compute mwmr global index
2513	mwmr_id = 0xFFFFFFFF
2514	for vseg in mapping.vspace[vspace_id].vsegs:
2515	for vobj in vseg.vobjs:
2516	if (self.mwmrname == vobj.name):
2517	mwmr_id = vobj.index
2518	if (mwmr_id == 0xFFFFFFFF):
2519	print 'error in Cpport.cbin() : mwmr vobj name %s not found in vspace %s' \
2520	% ( self.mwmrname, self.vspacename )
2521	sys.exit(1)
2522
2523	byte_stream = bytearray()
2524	byte_stream += mapping.int2bytes( 4 , dir_int ) # pseg global index
2525	byte_stream += mapping.int2bytes( 4 , vspace_id ) # vspace global index
2526	byte_stream += mapping.int2bytes( 4 , mwmr_id ) # mwmr vobj global index
2527
2528	if ( verbose ):
2529	print 'direction = %s' % self.direction
2530	print 'vspace_id = %d' % vspace_id
2531	print 'mwmr_id = %d' % mwmr_id
2532
2533	return byte_stream
2534
2535
2536	# Local Variables:
2537	# tab-width: 4;
2538	# c-basic-offset: 4;
2539	# c-file-offsets:((innamespace . 0)(inline-open . 0));
2540	# indent-tabs-mode: nil;
2541	# End:
2542	#
2543	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
2544

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