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source: soft/giet_vm/giet_python/mapping.py @ 403

Last change on this file since 403 was 403, checked in by cfuguet, 10 years ago

mapping.py: bugfix

Consider ramdisk in the IOC controller assertion: only one IOC must be instantiated

Renaming USE_RAMDISK constant to USE_IOC_RDK which is the name used in giet_drivers/ioc_driver.[ch]

Property svn:executable set to *

File size: 102.3 KB

Line
1	#!/usr/bin/env python
2
3	import sys
4
5	##########################################################################################
6	# file : giet_mapping.py
7	# date : april 2014
8	# author : Alain Greiner
9	##########################################################################################
10	# This file contains the classes required to define a mapping for the GIET_VM.
11	# - A 'Mapping' contains a set of 'Cluster' (hardware architecture)
12	# a set of 'Vseg' (kernel virtual segments mapping)
13	# a set of 'Vspace' (several user applications).
14	# - A 'Cluster' contains a set of 'Pseg' (all physical segments in cluster)
15	# a set of 'Proc' (processors in cluster)
16	# a set of 'Periph' (peripherals in cluster)
17	# a set of 'Coproc' (coprocessors in cluster)
18	# - A 'Vspace' contains a set of 'Vseg' (user virtual segments mapping)
19	# a set of 'Task' (user tasks mapping)
20	# - A 'Vseg' contains a set of 'Vobj'
21	# - A 'Periph' contains a set of 'Irq' (only for XCU, ICU and PIC types )
22	# - A 'Coproc' contains a set of 'Cpports' (one port per MWMR channel)
23	##########################################################################################
24	# Implementation Note
25	# As described above, the various objects are distributed in the PYTHON structure:
26	# For example the psegs set is split in several subsets (one subset per cluster),
27	# or the tasks set is split in several subsets (one subset per vspace), etc...
28	# In the C binary data structure used by the giet_vm, all objects of same type
29	# are stored in a linear array (one single array for all psegs for example).
30	# For all objects, we compute and store in the PYTHON object itsel a "global index"
31	# corresponding to the index in this global array, and this index can be used as
32	# a pseudo-pointer to identify a specific object of a given type.
33	##########################################################################################
34
35	######################################################################################
36	# These global lists must be consistent with enums in mapping_info.h or irq_handler.h
37	######################################################################################
38	PERIPHTYPES = [
39	'CMA',
40	'DMA',
41	'FBF',
42	'ICU',
43	'IOB',
44	'IOC',
45	'MMC',
46	'MWR',
47	'NIC',
48	'ROM',
49	'SIM',
50	'TIM',
51	'TTY',
52	'XCU',
53	'PIC',
54	]
55
56	PERIPHSUBTYPES = [
57	'BDV',
58	'HBA',
59	'SPI',
60	'NONE',
61	]
62
63	IRQTYPES = [
64	'HWI',
65	'WTI',
66	'PTI',
67	]
68
69	ISRTYPES = [
70	'ISR_DEFAULT',
71	'ISR_TICK',
72	'ISR_TTY_RX',
73	'ISR_TTY_TX',
74	'ISR_BDV',
75	'ISR_TIMER',
76	'ISR_WAKUP',
77	'ISR_NIC_RX',
78	'ISR_NIC_TX',
79	'ISR_CMA',
80	'ISR_MMC',
81	'ISR_DMA',
82	'ISR_SPI',
83	]
84
85	VOBJTYPES = [
86	'ELF',
87	'BLOB',
88	'PTAB',
89	'PERI',
90	'MWMR',
91	'LOCK',
92	'BUFFER',
93	'BARRIER',
94	'CONST',
95	'MEMSPACE',
96	'SCHED',
97	]
98
99	VSEGMODES = [
100	'____',
101	'___U',
102	'__W_',
103	'__WU',
104	'_X__',
105	'_X_U',
106	'_XW_',
107	'_XWU',
108	'C___',
109	'C__U',
110	'C_W_',
111	'C_WU',
112	'CX__',
113	'CX_U',
114	'CXW_',
115	'CXWU',
116	]
117
118	PSEGTYPES = [
119	'RAM',
120	'ROM', # deprecated => use PERI
121	'PERI',
122	]
123
124	CP_PORT_DIRS = [
125	'TO_COPROC',
126	'FROM_COPROC',
127	]
128
129	##########################################################################################
130	class Mapping( object ):
131	##########################################################################################
132	def __init__( self,
133	name, # mapping name
134	x_size, # number of clusters in a row
135	y_size, # number of clusters in a column
136	procs_max, # max number of processors per cluster
137	x_width = 4, # number of bits encoding x coordinate
138	y_width = 4, # number of bits encoding y coordinate
139	paddr_width = 40, # number of bits for physical address
140	coherence = 1, # hardware cache coherence when non-zero
141	irq_per_proc = 1, # number or IRQs from XCU to processor
142	use_ramdisk = False, # use ramdisk when true
143	x_io = 0, # cluster_io x coordinate
144	y_io = 0, # cluster_io y coordinate
145	peri_increment = 0x10000, # address increment for globals
146	reset_address = 0xBFC00000, # Processor wired boot_address
147	ram_base = 0, # RAM physical base address in cluster[0,0]
148	ram_size = 0 ): # RAM size in each cluster (bytes)
149
150	self.signature = 0xDACE2014
151	self.name = name
152	self.paddr_width = paddr_width
153	self.coherence = coherence
154	self.x_size = x_size
155	self.y_size = y_size
156	self.x_width = x_width
157	self.y_width = y_width
158	self.irq_per_proc = irq_per_proc
159	self.procs_max = procs_max
160	self.use_ramdisk = use_ramdisk
161	self.x_io = x_io
162	self.y_io = y_io
163	self.peri_increment = peri_increment
164	self.reset_address = reset_address
165	self.ram_base = ram_base
166	self.ram_size = ram_size
167
168
169	self.total_vspaces = 0
170	self.total_globals = 0
171	self.total_psegs = 0
172	self.total_vsegs = 0
173	self.total_vobjs = 0
174	self.total_tasks = 0
175	self.total_procs = 0
176	self.total_irqs = 0
177	self.total_coprocs = 0
178	self.total_cpports = 0
179	self.total_periphs = 0
180
181	self.clusters = []
182	self.globs = []
183	self.vspaces = []
184
185	for x in xrange( self.x_size ):
186	for y in xrange( self.y_size ):
187	cluster = Cluster( x , y )
188	cluster.index = (x * self.y_size) + y
189	self.clusters.append( cluster )
190
191	return
192
193	########################## add a ram pseg in a cluster
194	def addRam( self,
195	name, # pseg name
196	base, # pseg base address
197	size ): # pseg length (bytes)
198
199	# check coordinates (obtained from the base address)
200	paddr_lsb_width = self.paddr_width - self.x_width - self.y_width
201	cluster_xy = base >> paddr_lsb_width
202	x = cluster_xy >> (self.y_width);
203	y = cluster_xy & ((1 << self.y_width) - 1)
204
205	assert (base & 0xFFF) == 0
206
207	assert (x < self.x_size) and (y < self.y_size)
208
209	assert ( (base & ((1<<paddr_lsb_width)-1)) == self.ram_base )
210
211	assert ( size == self.ram_size )
212
213	cluster_id = (x * self.y_size) + y
214
215	# add one pseg in the mapping
216	pseg = Pseg( name, base, size, x, y, 'RAM' )
217	self.clusters[cluster_id].psegs.append( pseg )
218	pseg.index = self.total_psegs
219	self.total_psegs += 1
220
221	return pseg
222
223	############################## add a peripheral and the associated pseg in a cluster
224	def addPeriph( self,
225	name, # associated pseg name
226	base, # associated pseg base address
227	size, # associated pseg length (bytes)
228	ptype, # peripheral type
229	subtype = 'NONE', # peripheral subtype
230	channels = 1, # number of channels
231	arg = 0 ): # optional argument (semantic depends on ptype)
232
233	# check cluster coordinates (obtained from the base address)
234	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
235	x = cluster_xy >> (self.y_width);
236	y = cluster_xy & ((1 << self.y_width) - 1)
237
238	assert (x < self.x_size) and (y < self.y_size)
239
240	assert (base & 0xFFF) == 0
241
242	assert ptype in PERIPHTYPES
243
244	assert subtype in PERIPHSUBTYPES
245
246	cluster_id = (x * self.y_size) + y
247
248	# add one pseg into mapping
249	pseg = Pseg( name, base, size, x, y, 'PERI' )
250	self.clusters[cluster_id].psegs.append( pseg )
251	pseg.index = self.total_psegs
252	self.total_psegs += 1
253
254	# add one periph into mapping
255	periph = Periph( pseg, ptype, subtype, channels, arg )
256	self.clusters[cluster_id].periphs.append( periph )
257	periph.index = self.total_periphs
258	self.total_periphs += 1
259
260	return periph
261
262	################################ add an IRQ in a peripheral
263	def addIrq( self,
264	periph, # peripheral containing IRQ (PIC or XCU)
265	index, # peripheral input port index
266	isrtype, # ISR type
267	channel = 0 ): # channel for multi-channels ISR
268
269	assert isrtype in ISRTYPES
270
271	assert index < 32
272
273	# add one irq into mapping
274	irq = Irq( 'HWI', index , isrtype, channel )
275	periph.irqs.append( irq )
276	irq.index = self.total_irqs
277	self.total_irqs += 1
278
279	return irq
280
281	########################## add a processor in a cluster
282	def addProc( self,
283	x, # cluster x coordinate
284	y, # cluster y coordinate
285	p ): # processor local index
286
287	assert (x < self.x_size) and (y < self.y_size)
288
289	cluster_id = (x * self.y_size) + y
290
291	# add one proc into mapping
292	proc = Processor( x, y, p )
293	self.clusters[cluster_id].procs.append( proc )
294	proc.index = self.total_procs
295	self.total_procs += 1
296
297	return proc
298
299	############################## add a coprocessor in a cluster
300	def addCoproc( self,
301	name, # associated pseg name
302	base, # associated pseg base address
303	size ): # associated pseg length
304
305	# check cluster coordinates (obtained from the base address)
306	cluster_xy = base >> (self.paddr_width - self.x_width - self.y_width)
307	x = cluster_xy >> (self.y_width);
308	y = cluster_xy & ((1 << self.y_width) - 1)
309
310	assert (x < self.x_size) and (y < self.y_size)
311
312	cluster_id = (x * self.y_size) + y
313
314	# add one pseg into mapping
315	pseg = Pseg( name, base, size, x, y, 'PERI' )
316	self.clusters[cluster_id].psegs.append( pseg )
317	pseg.index = self.total_psegs
318	self.total_psegs += 1
319
320	# add one coproc into mapping
321	periph = Coproc( pseg )
322	self.clusters[cluster_id].coprocs.append( coproc )
323	periph.index = self.total_coprocs
324	self.total_coprocs += 1
325
326	return coproc
327
328	################################## add a port in a coprocessor
329	def addPort( self,
330	coproc, # coprocessor containing the port
331	direction, # direction (TO_COPROC / FROM_COPROC)
332	vspacename, # name of vspace using the coproc
333	mwmrname ): # name of the vobj defining the MWMR channel
334
335	assert direction in CP_PORT_DIRS
336
337	# add one cpport into mapping
338	port = Cpport( direction, vspacename, mwmrname )
339	coproc.ports.append( port )
340	port.index = self.total_cpports
341	self.total_cpports += 1
342
343	return port
344
345	############################ add one (or several) global vseg into mapping
346	def addGlobal( self,
347	name, # vseg name
348	vbase, # virtual base address
349	size, # vobj length (bytes)
350	mode, # CXWU flags
351	vtype, # vobj type
352	x, # destination x coordinate
353	y, # destination y coordinate
354	pseg, # destination pseg name
355	identity = False, # identity mapping required if true
356	binpath = '', # pathname for binary code
357	local = False ): # non shared vseg when true
358
359	assert mode in VSEGMODES
360
361	assert vtype in VOBJTYPES
362
363	assert (vbase & 0xFFF) == 0
364
365	assert (x < self.x_size) and (y < self.y_size)
366
367	# add one vseg into mapping
368	vseg = Vseg( name, vbase, mode, x, y, pseg,
369	identity = identity, local = local )
370
371	self.globs.append( vseg )
372	self.total_globals += 1
373	vseg.index = self.total_vsegs
374	self.total_vsegs += 1
375
376	# add one vobj into mapping
377	vobj = Vobj( name, size, vtype, binpath, 0, 0 )
378	vseg.vobjs.append( vobj )
379	vobj.index = self.total_vobjs
380	self.total_vobjs += 1
381
382	return
383
384	################################ add a vspace into mapping
385	def addVspace( self,
386	name, # vspace name
387	startname ): # name of vobj containing start_vector
388
389	# add one vspace into mapping
390	vspace = Vspace( name, startname )
391	self.vspaces.append( vspace )
392	vspace.index = self.total_vspaces
393	self.total_vspaces += 1
394
395	return vspace
396
397	################################# add a private vseg and a vobj in a vspace
398	def addVseg( self,
399	vspace, # vspace containing the vseg
400	name, # vseg name
401	vbase, # virtual base address
402	size, # vobj length (bytes)
403	mode, # CXWU flags
404	vtype, # vobj type
405	x, # destination x coordinate
406	y, # destination y coordinate
407	pseg, # destination pseg name
408	binpath = '', # pathname for binary code
409	align = 0, # alignment required
410	init = 0, # initial value
411	local = False ): # non shared when true
412
413	assert mode in VSEGMODES
414
415	assert vtype in VOBJTYPES
416
417	assert (x < self.x_size) and (y < self.y_size)
418
419	# add one vseg into mapping
420	vseg = Vseg( name, vbase, mode, x, y, pseg, local = local )
421	vspace.vsegs.append( vseg )
422	vseg.index = self.total_vsegs
423	self.total_vsegs += 1
424
425	# add one vobj into mapping
426	vobj = Vobj( name, size, vtype, binpath, align, init )
427	vseg.vobjs.append( vobj )
428	vobj.index = self.total_vobjs
429	self.total_vobjs += 1
430
431	return vseg
432
433	################################ add a vobj in a private vseg
434	def addVobj( self,
435	vseg, # vseg containing vobj
436	name, # vobj name
437	size, # vobj length (bytes)
438	vtype, # vobj type
439	binpath = '', # pathname to binary
440	align = 0, # alignment constraint
441	init = 0 ): # initial value
442
443	assert vtype in VOBJTYPES
444
445	# add one vobj into mapping
446	vobj = Vobj( name, size, vtype, binpath, align, init )
447	vseg.vobjs.append( vobj )
448	vobj.index = self.total_vobjs
449	self.total_vobjs += 1
450
451	return vobj
452
453	################################ add a task in a vspace
454	def addTask( self,
455	vspace, # vspace containing task
456	name, # task name
457	trdid, # task index in vspace
458	x, # destination x coordinate
459	y, # destination y coordinate
460	lpid, # destination processor local index
461	stackname, # name of vobj containing stack
462	heapname, # name of vobj containing heap
463	startid, # index in start_vector
464	usetty = False, # request a private TTY channel
465	usenic = False, # request a private NIC channel
466	usecma = False, # request a private CMA channel
467	usehba = False, # request a private HBA channel
468	usetim = False ): # request a private TIM channel
469
470	assert (x < self.x_size) and (y < self.y_size)
471
472	assert lpid < self.procs_max
473
474	# add one task into mapping
475	task = Task( name, trdid, x, y, lpid, stackname, heapname, startid,
476	usetty, usenic, usecma, usehba, usetim )
477	vspace.tasks.append( task )
478	task.index = self.total_tasks
479	self.total_tasks += 1
480
481	return task
482
483	#################################
484	def str2bytes( self, nbytes, s ): # string => nbytes_packed byte array
485
486	byte_stream = bytearray()
487	length = len( s )
488	if length < (nbytes - 1):
489	for b in s:
490	byte_stream.append( b )
491	for x in xrange(nbytes-length):
492	byte_stream.append( '\0' )
493	else:
494	print '[genmap error] in str2bytes() : string %s too long' % s
495	sys.exit(1)
496
497	return byte_stream
498
499	###################################
500	def int2bytes( self, nbytes, val ): # integer => nbytes litle endian byte array
501
502	byte_stream = bytearray()
503	for n in xrange( nbytes ):
504	byte_stream.append( (val >> (n<<3)) & 0xFF )
505
506	return byte_stream
507
508	################
509	def xml( self ): # xml file generation for mapping
510
511	s = '<?xml version="1.0"?>\n\n'
512	s += '<mapping_info signature = "0x%x"\n' % (self.signature)
513	s += ' name = "%s"\n' % (self.name)
514	s += ' x_size = "%d"\n' % (self.x_size)
515	s += ' y_size = "%d"\n' % (self.y_size)
516	s += ' x_width = "%d"\n' % (self.x_width)
517	s += ' y_width = "%d"\n' % (self.y_width)
518	s += ' irq_per_proc = "%d"\n' % (self.irq_per_proc)
519	s += ' use_ramdisk = "%d"\n' % (self.use_ramdisk)
520	s += ' x_io = "%d"\n' % (self.x_io)
521	s += ' y_io = "%d" >\n' % (self.y_io)
522	s += '\n'
523
524	s += ' <clusterset>\n'
525	for x in xrange ( self.x_size ):
526	for y in xrange ( self.y_size ):
527	cluster_id = (x * self.y_size) + y
528	s += self.clusters[cluster_id].xml()
529	s += ' </clusterset>\n'
530	s += '\n'
531
532	s += ' <globalset>\n'
533	for vseg in self.globs: s += vseg.xml()
534	s += ' </globalset>\n'
535	s += '\n'
536
537	s += ' <vspaceset>\n'
538	for vspace in self.vspaces: s += vspace.xml()
539	s += ' </vspaceset>\n'
540
541	s += '</mapping_info>\n'
542	return s
543
544	#########################
545	def cbin( self, verbose ): # C binary structure generation for mapping
546
547	byte_stream = bytearray()
548
549	# header
550	byte_stream += self.int2bytes(4, self.signature)
551	byte_stream += self.int2bytes(4, self.x_size)
552	byte_stream += self.int2bytes(4, self.y_size)
553	byte_stream += self.int2bytes(4, self.x_width)
554	byte_stream += self.int2bytes(4, self.y_width)
555	byte_stream += self.int2bytes(4, self.x_io)
556	byte_stream += self.int2bytes(4, self.y_io)
557	byte_stream += self.int2bytes(4, self.irq_per_proc)
558	byte_stream += self.int2bytes(4, self.use_ramdisk)
559	byte_stream += self.int2bytes(4, self.total_globals)
560	byte_stream += self.int2bytes(4, self.total_vspaces)
561	byte_stream += self.int2bytes(4, self.total_psegs)
562	byte_stream += self.int2bytes(4, self.total_vsegs)
563	byte_stream += self.int2bytes(4, self.total_vobjs)
564	byte_stream += self.int2bytes(4, self.total_tasks)
565	byte_stream += self.int2bytes(4, self.total_procs)
566	byte_stream += self.int2bytes(4, self.total_irqs)
567	byte_stream += self.int2bytes(4, self.total_coprocs)
568	byte_stream += self.int2bytes(4, self.total_cpports)
569	byte_stream += self.int2bytes(4, self.total_periphs)
570	byte_stream += self.str2bytes(32, self.name)
571
572	if ( verbose ):
573	print '\n'
574	print 'name = %s' % self.name
575	print 'signature = %x' % self.signature
576	print 'x_size = %d' % self.x_size
577	print 'y_size = %d' % self.y_size
578	print 'x_width = %d' % self.x_width
579	print 'y_width = %d' % self.y_width
580	print 'x_io = %d' % self.x_io
581	print 'y_io = %d' % self.y_io
582	print 'irq_per_proc = %d' % self.irq_per_proc
583	print 'use_ramdisk = %d' % self.use_ramdisk
584	print 'total_globals = %d' % self.total_globals
585	print 'total_psegs = %d' % self.total_psegs
586	print 'total_vsegs = %d' % self.total_vsegs
587	print 'total_vobjs = %d' % self.total_vobjs
588	print 'total_tasks = %d' % self.total_tasks
589	print 'total_procs = %d' % self.total_procs
590	print 'total_irqs = %d' % self.total_irqs
591	print 'total_coprocs = %d' % self.total_coprocs
592	print 'total_cpports = %d' % self.total_cpports
593	print 'total_periphs = %d' % self.total_periphs
594	print '\n'
595
596	# clusters array
597	index = 0
598	for cluster in self.clusters:
599	byte_stream += cluster.cbin( self, verbose, index )
600	index += 1
601
602	if ( verbose ): print '\n'
603
604	# psegs array
605	index = 0
606	for cluster in self.clusters:
607	for pseg in cluster.psegs:
608	byte_stream += pseg.cbin( self, verbose, index, cluster )
609	index += 1
610
611	if ( verbose ): print '\n'
612
613	# vspaces array
614	index = 0
615	for vspace in self.vspaces:
616	byte_stream += vspace.cbin( self, verbose, index )
617	index += 1
618
619	if ( verbose ): print '\n'
620
621	# vsegs array
622	index = 0
623	for vseg in self.globs:
624	byte_stream += vseg.cbin( self, verbose, index )
625	index += 1
626	for vspace in self.vspaces:
627	for vseg in vspace.vsegs:
628	byte_stream += vseg.cbin( self, verbose, index )
629	index += 1
630
631	if ( verbose ): print '\n'
632
633	# vobjs array
634	index = 0
635	for vseg in self.globs:
636	for vobj in vseg.vobjs:
637	byte_stream += vobj.cbin( self, verbose, index )
638	index += 1
639	for vspace in self.vspaces:
640	for vseg in vspace.vsegs:
641	for vobj in vseg.vobjs:
642	byte_stream += vobj.cbin( self, verbose, index )
643	index += 1
644
645	if ( verbose ): print '\n'
646
647	# tasks array
648	index = 0
649	for vspace in self.vspaces:
650	for task in vspace.tasks:
651	byte_stream += task.cbin( self, verbose, index, vspace )
652	index += 1
653
654	if ( verbose ): print '\n'
655
656	# procs array
657	index = 0
658	for cluster in self.clusters:
659	for proc in cluster.procs:
660	byte_stream += proc.cbin( self, verbose, index )
661	index += 1
662
663	if ( verbose ): print '\n'
664
665	# irqs array
666	index = 0
667	for cluster in self.clusters:
668	for periph in cluster.periphs:
669	for irq in periph.irqs:
670	byte_stream += irq.cbin( self, verbose, index )
671	index += 1
672
673	if ( verbose ): print '\n'
674
675	# coprocs array
676	index = 0
677	for cluster in self.clusters:
678	for coproc in cluster.coprocs:
679	byte_stream += coproc.cbin( self, verbose, index )
680	index += 1
681
682	if ( verbose ): print '\n'
683
684	# cpports array
685	index = 0
686	for cluster in self.clusters:
687	for coproc in cluster.coprocs:
688	for port in coproc.ports:
689	byte_stream += port.cbin( self, verbose, index )
690	index += 1
691
692	if ( verbose ): print '\n'
693
694	# periphs array
695	index = 0
696	for cluster in self.clusters:
697	for periph in cluster.periphs:
698	byte_stream += periph.cbin( self, verbose, index )
699	index += 1
700
701	return byte_stream
702	# end of cbin()
703
704	#######################
705	def giet_vsegs( self ): # compute string for giet_vsegs.ld file
706	# required by giet_vm compilation
707
708	# search the vsegs required for the giet_vsegs.ld
709	boot_code_found = False
710	boot_data_found = False
711	kernel_uncdata_found = False
712	kernel_data_found = False
713	kernel_code_found = False
714	kernel_init_found = False
715	for vseg in self.globs:
716
717	if ( vseg.name == 'seg_boot_code' ):
718	boot_code_vbase = vseg.vbase
719	boot_code_size = vseg.vobjs[0].length
720	boot_code_found = True
721
722	if ( vseg.name == 'seg_boot_data' ):
723	boot_data_vbase = vseg.vbase
724	boot_data_size = vseg.vobjs[0].length
725	boot_data_found = True
726
727	if ( vseg.name == 'seg_kernel_uncdata' ):
728	kernel_uncdata_vbase = vseg.vbase
729	kernel_uncdata_size = vseg.vobjs[0].length
730	kernel_uncdata_found = True
731
732	if ( vseg.name == 'seg_kernel_data' ):
733	kernel_data_vbase = vseg.vbase
734	kernel_data_size = vseg.vobjs[0].length
735	kernel_data_found = True
736
737	if ( vseg.name == 'seg_kernel_code' ):
738	kernel_code_vbase = vseg.vbase
739	kernel_code_size = vseg.vobjs[0].length
740	kernel_code_found = True
741
742	if ( vseg.name == 'seg_kernel_init' ):
743	kernel_init_vbase = vseg.vbase
744	kernel_init_size = vseg.vobjs[0].length
745	kernel_init_found = True
746
747	# check if all required vsegs have been found
748	if ( boot_code_found == False ):
749	print '[genmap error] in giet_vsegs() : seg_boot_code vseg missing'
750	sys.exit()
751
752	if ( boot_data_found == False ):
753	print '[genmap error] in giet_vsegs() : seg_boot_data vseg missing'
754	sys.exit()
755
756	if ( kernel_data_found == False ):
757	print '[genmap error] in giet_vsegs() : seg_kernel_data vseg missing'
758	sys.exit()
759
760	if ( kernel_uncdata_found == False ):
761	print '[genmap error] in giet_vsegs() : seg_kernel_uncdata vseg missing'
762	sys.exit()
763
764	if ( kernel_code_found == False ):
765	print '[genmap error] in giet_vsegs() : seg_kernel_code vseg missing'
766	sys.exit()
767
768	if ( kernel_init_found == False ):
769	print '[genmap error] in giet_vsegs() : seg_kernel_init vseg missing'
770	sys.exit()
771
772	# build string
773	s = '/* Generated by genmap for %s */\n' % self.name
774	s += '\n'
775
776	s += 'boot_code_vbase = 0x%x;\n' % boot_code_vbase
777	s += 'boot_code_size = 0x%x;\n' % boot_code_size
778	s += '\n'
779	s += 'boot_data_vbase = 0x%x;\n' % boot_data_vbase
780	s += 'boot_data_size = 0x%x;\n' % boot_data_size
781	s += '\n'
782	s += 'kernel_code_vbase = 0x%x;\n' % kernel_code_vbase
783	s += 'kernel_code_size = 0x%x;\n' % kernel_code_size
784	s += '\n'
785	s += 'kernel_data_vbase = 0x%x;\n' % kernel_data_vbase
786	s += 'kernel_data_size = 0x%x;\n' % kernel_data_size
787	s += '\n'
788	s += 'kernel_uncdata_vbase = 0x%x;\n' % kernel_uncdata_vbase
789	s += 'kernel_uncdata_size = 0x%x;\n' % kernel_uncdata_size
790	s += '\n'
791	s += 'kernel_init_vbase = 0x%x;\n' % kernel_init_vbase
792	s += 'kernel_init_size = 0x%x;\n' % kernel_init_size
793	s += '\n'
794
795	return s
796
797	########################
798	def hard_config( self ): # compute string for hard_config.h file required by
799	# - top.cpp compilation
800	# - giet_vm compilation
801	# - tsar_preloader compilation
802
803	nb_total_procs = 0
804
805	# for each peripheral type, define default values
806	# for pbase address, size, number of components, and channels
807	nb_cma = 0
808	cma_channels = 0
809	seg_cma_base = 0xFFFFFFFF
810	seg_cma_size = 0
811
812	nb_dma = 0
813	dma_channels = 0
814	seg_dma_base = 0xFFFFFFFF
815	seg_dma_size = 0
816
817	nb_fbf = 0
818	fbf_channels = 0
819	fbf_arg = 0
820	seg_fbf_base = 0xFFFFFFFF
821	seg_fbf_size = 0
822
823	nb_icu = 0
824	icu_channels = 0
825	seg_icu_base = 0xFFFFFFFF
826	seg_icu_size = 0
827
828	nb_iob = 0
829	iob_channels = 0
830	seg_iob_base = 0xFFFFFFFF
831	seg_iob_size = 0
832
833	nb_ioc = 0
834	ioc_channels = 0
835	seg_ioc_base = 0xFFFFFFFF
836	seg_ioc_size = 0
837
838	nb_mmc = 0
839	mmc_channels = 0
840	seg_mmc_base = 0xFFFFFFFF
841	seg_mmc_size = 0
842
843	nb_mwr = 0
844	mwr_channels = 0
845	seg_mwr_base = 0xFFFFFFFF
846	seg_mwr_size = 0
847
848	nb_nic = 0
849	nic_channels = 0
850	seg_nic_base = 0xFFFFFFFF
851	seg_nic_size = 0
852
853	nb_pic = 0
854	pic_channels = 0
855	seg_pic_base = 0xFFFFFFFF
856	seg_pic_size = 0
857
858	nb_rom = 0
859	rom_channels = 0
860	seg_rom_base = 0xFFFFFFFF
861	seg_rom_size = 0
862
863	nb_sim = 0
864	sim_channels = 0
865	seg_sim_base = 0xFFFFFFFF
866	seg_sim_size = 0
867
868	nb_tim = 0
869	tim_channels = 0
870	seg_tim_base = 0xFFFFFFFF
871	seg_tim_size = 0
872
873	nb_tty = 0
874	tty_channels = 0
875	seg_tty_base = 0xFFFFFFFF
876	seg_tty_size = 0
877
878	nb_xcu = 0
879	xcu_channels = 0
880	xcu_arg = 0
881	seg_xcu_base = 0xFFFFFFFF
882	seg_xcu_size = 0
883
884	use_bdv = False
885	use_spi = False
886	use_hba = False
887
888	# get peripherals attributes
889	for cluster in self.clusters:
890	for periph in cluster.periphs:
891	if ( periph.ptype == 'CMA' ):
892	seg_cma_base = periph.pseg.base & 0xFFFFFFFF
893	seg_cma_size = periph.pseg.size
894	cma_channels = periph.channels
895	nb_cma +=1
896
897	elif ( periph.ptype == 'DMA' ):
898	seg_dma_base = periph.pseg.base & 0xFFFFFFFF
899	seg_dma_size = periph.pseg.size
900	dma_channels = periph.channels
901	nb_dma +=1
902
903	elif ( periph.ptype == 'FBF' ):
904	seg_fbf_base = periph.pseg.base & 0xFFFFFFFF
905	seg_fbf_size = periph.pseg.size
906	fbf_channels = periph.channels
907	fbf_arg = periph.arg
908	nb_fbf +=1
909
910	elif ( periph.ptype == 'ICU' ):
911	seg_icu_base = periph.pseg.base & 0xFFFFFFFF
912	seg_icu_size = periph.pseg.size
913	icu_channels = periph.channels
914	nb_icu +=1
915
916	elif ( periph.ptype == 'IOB' ):
917	seg_iob_base = periph.pseg.base & 0xFFFFFFFF
918	seg_iob_size = periph.pseg.size
919	iob_channels = periph.channels
920	nb_iob +=1
921
922	elif ( periph.ptype == 'IOC' ):
923	seg_ioc_base = periph.pseg.base & 0xFFFFFFFF
924	seg_ioc_size = periph.pseg.size
925	ioc_channels = periph.channels
926	nb_ioc += 1
927	if ( periph.subtype == 'BDV' ): use_bdv = True
928	elif ( periph.subtype == 'HBA' ): use_hba = True
929	elif ( periph.subtype == 'SPI' ): use_spi = True
930
931	elif ( periph.ptype == 'MMC' ):
932	seg_mmc_base = periph.pseg.base & 0xFFFFFFFF
933	seg_mmc_size = periph.pseg.size
934	mmc_channels = periph.channels
935	nb_mmc +=1
936
937	elif ( periph.ptype == 'MWR' ):
938	seg_mwr_base = periph.pseg.base & 0xFFFFFFFF
939	seg_wmr_size = periph.pseg.size
940	mwr_channels = periph.channels
941	nb_mwr +=1
942
943	elif ( periph.ptype == 'ROM' ):
944	seg_rom_base = periph.pseg.base & 0xFFFFFFFF
945	seg_rom_size = periph.pseg.size
946	rom_channels = periph.channels
947	nb_rom +=1
948
949	elif ( periph.ptype == 'SIM' ):
950	seg_sim_base = periph.pseg.base & 0xFFFFFFFF
951	seg_sim_size = periph.pseg.size
952	sim_channels = periph.channels
953	nb_sim +=1
954
955	elif ( periph.ptype == 'NIC' ):
956	seg_nic_base = periph.pseg.base & 0xFFFFFFFF
957	seg_nic_size = periph.pseg.size
958	nic_channels = periph.channels
959	nb_nic +=1
960
961	elif ( periph.ptype == 'PIC' ):
962	seg_pic_base = periph.pseg.base & 0xFFFFFFFF
963	seg_pic_size = periph.pseg.size
964	pic_channels = periph.channels
965	nb_pic +=1
966
967	elif ( periph.ptype == 'TIM' ):
968	seg_tim_base = periph.pseg.base & 0xFFFFFFFF
969	seg_tim_size = periph.pseg.size
970	tim_channels = periph.channels
971	nb_tim +=1
972
973	elif ( periph.ptype == 'TTY' ):
974	seg_tty_base = periph.pseg.base & 0xFFFFFFFF
975	seg_tty_size = periph.pseg.size
976	tty_channels = periph.channels
977	nb_tty +=1
978
979	elif ( periph.ptype == 'XCU' ):
980	seg_xcu_base = periph.pseg.base & 0xFFFFFFFF
981	seg_xcu_size = periph.pseg.size
982	xcu_channels = periph.channels
983	xcu_arg = periph.arg
984	nb_xcu +=1
985
986	# don't mix ICU and XCU
987	assert ( nb_icu*nb_xcu == 0 )
988
989	# no more than two access to external peripherals
990	assert ( nb_fbf <= 2 )
991	assert ( nb_cma <= 2 )
992	assert ( nb_ioc <= 2 )
993	assert ( nb_nic <= 2 )
994	assert ( nb_tim <= 2 )
995	assert ( nb_tty <= 2 )
996	assert ( nb_pic <= 2 )
997
998	# one and only one type of IOC controller
999	nb_iocs = 0
1000	if use_hba : nb_iocs += 1
1001	if use_bdv : nb_iocs += 1
1002	if use_spi : nb_iocs += 1
1003	if self.use_ramdisk: nb_iocs += 1
1004	assert ( nb_iocs == 1 )
1005
1006	# Compute total number of processors
1007	for cluster in self.clusters:
1008	nb_total_procs += len( cluster.procs )
1009
1010	# Compute physical addresses for BOOT vsegs
1011	boot_mapping_found = False
1012	boot_code_found = False
1013	boot_data_found = False
1014	boot_stack_found = False
1015
1016	for vseg in self.globs:
1017	if ( vseg.name == 'seg_boot_mapping' ):
1018	boot_mapping_base = vseg.vbase
1019	boot_mapping_size = vseg.vobjs[0].length
1020	boot_mapping_identity = vseg.identity
1021	boot_mapping_found = True
1022
1023	if ( vseg.name == 'seg_boot_code' ):
1024	boot_code_base = vseg.vbase
1025	boot_code_size = vseg.vobjs[0].length
1026	boot_code_identity = vseg.identity
1027	boot_code_found = True
1028
1029	if ( vseg.name == 'seg_boot_data' ):
1030	boot_data_base = vseg.vbase
1031	boot_data_size = vseg.vobjs[0].length
1032	boot_data_identity = vseg.identity
1033	boot_data_found = True
1034
1035	if ( vseg.name == 'seg_boot_stack' ):
1036	boot_stack_base = vseg.vbase
1037	boot_stack_size = vseg.vobjs[0].length
1038	boot_stack_identity = vseg.identity
1039	boot_stack_found = True
1040
1041	# check that BOOT vsegs are found and identity mapping
1042	if ( (boot_mapping_found == False) or (boot_mapping_identity == False) ):
1043	print '[genmap error] in hard_config() : seg_boot_mapping missing or not ident'
1044	sys.exit()
1045
1046	if ( (boot_code_found == False) or (boot_code_identity == False) ):
1047	print '[genmap error] in hard_config() : seg_boot_code missing or not ident'
1048	sys.exit()
1049
1050	if ( (boot_data_found == False) or (boot_data_identity == False) ):
1051	print '[genmap error] in hard_config() : seg_boot_data missing or not ident'
1052	sys.exit()
1053
1054	if ( (boot_stack_found == False) or (boot_stack_identity == False) ):
1055	print '[genmap error] in giet_vsegs() : seg_boot_stack missing or not ident'
1056	sys.exit()
1057
1058	# Search RAMDISK global vseg if required
1059	seg_rdk_base = 0xFFFFFFFF
1060	seg_rdk_size = 0
1061	seg_rdk_found = False
1062
1063	if self.use_ramdisk:
1064	for vseg in self.globs:
1065	if ( vseg.name == 'seg_ramdisk' ):
1066	seg_rdk_base = vseg.vbase
1067	seg_rdk_size = vseg.vobjs[0].length
1068	seg_rdk_found = True
1069
1070	if ( seg_rdk_found == False ):
1071	print 'Error in hard_config() "seg_ramdisk" not found'
1072	sys.exit(1)
1073
1074	# build string
1075	s = '/* Generated by genmap for %s */\n' % self.name
1076	s += '\n'
1077	s += '#ifndef HARD_CONFIG_H\n'
1078	s += '#define HARD_CONFIG_H\n'
1079	s += '\n'
1080
1081	s += '/* General platform parameters */\n'
1082	s += '\n'
1083	s += '#define X_SIZE %d\n' % self.x_size
1084	s += '#define Y_SIZE %d\n' % self.y_size
1085	s += '#define X_WIDTH %d\n' % self.x_width
1086	s += '#define Y_WIDTH %d\n' % self.y_width
1087	s += '#define X_IO %d\n' % self.x_io
1088	s += '#define Y_IO %d\n' % self.y_io
1089	s += '#define NB_PROCS_MAX %d\n' % self.procs_max
1090	s += '#define IRQ_PER_PROCESSOR %d\n' % self.irq_per_proc
1091	s += '#define RESET_ADDRESS 0x%x\n' % self.reset_address
1092	s += '#define NB_TOTAL_PROCS %d\n' % nb_total_procs
1093	s += '\n'
1094
1095	s += '/* Peripherals */\n'
1096	s += '\n'
1097	s += '#define NB_TTY_CHANNELS %d\n' % tty_channels
1098	s += '#define NB_IOC_CHANNELS %d\n' % ioc_channels
1099	s += '#define NB_NIC_CHANNELS %d\n' % nic_channels
1100	s += '#define NB_CMA_CHANNELS %d\n' % cma_channels
1101	s += '#define NB_TIM_CHANNELS %d\n' % tim_channels
1102	s += '#define NB_DMA_CHANNELS %d\n' % dma_channels
1103	s += '\n'
1104	s += '#define USE_XCU %d\n' % ( nb_xcu != 0 )
1105	s += '#define USE_IOB %d\n' % ( nb_iob != 0 )
1106	s += '#define USE_PIC %d\n' % ( nb_pic != 0 )
1107	s += '#define USE_FBF %d\n' % ( nb_fbf != 0 )
1108	s += '\n'
1109	s += '#define USE_IOC_BDV %d\n' % use_bdv
1110	s += '#define USE_IOC_SPI %d\n' % use_spi
1111	s += '#define USE_IOC_HBA %d\n' % use_hba
1112	s += '#define USE_IOC_RDK %d\n' % self.use_ramdisk
1113	s += '\n'
1114	s += '#define FBUF_X_SIZE %d\n' % fbf_arg
1115	s += '#define FBUF_Y_SIZE %d\n' % fbf_arg
1116	s += '\n'
1117	s += '#define XCU_NB_INPUTS %d\n' % xcu_arg
1118	s += '\n'
1119
1120	s += '/* base addresses and sizes for physical segments */\n'
1121	s += '\n'
1122	s += '#define SEG_RAM_BASE 0x%x\n' % self.ram_base
1123	s += '#define SEG_RAM_SIZE 0x%x\n' % self.ram_size
1124	s += '\n'
1125	s += '#define SEG_CMA_BASE 0x%x\n' % seg_cma_base
1126	s += '#define SEG_CMA_SIZE 0x%x\n' % seg_cma_size
1127	s += '\n'
1128	s += '#define SEG_DMA_BASE 0x%x\n' % seg_dma_base
1129	s += '#define SEG_DMA_SIZE 0x%x\n' % seg_dma_size
1130	s += '\n'
1131	s += '#define SEG_FBF_BASE 0x%x\n' % seg_fbf_base
1132	s += '#define SEG_FBF_SIZE 0x%x\n' % seg_fbf_size
1133	s += '\n'
1134	s += '#define SEG_ICU_BASE 0x%x\n' % seg_icu_base
1135	s += '#define SEG_ICU_SIZE 0x%x\n' % seg_icu_size
1136	s += '\n'
1137	s += '#define SEG_IOB_BASE 0x%x\n' % seg_iob_base
1138	s += '#define SEG_IOB_SIZE 0x%x\n' % seg_iob_size
1139	s += '\n'
1140	s += '#define SEG_IOC_BASE 0x%x\n' % seg_ioc_base
1141	s += '#define SEG_IOC_SIZE 0x%x\n' % seg_ioc_size
1142	s += '\n'
1143	s += '#define SEG_MMC_BASE 0x%x\n' % seg_mmc_base
1144	s += '#define SEG_MMC_SIZE 0x%x\n' % seg_mmc_size
1145	s += '\n'
1146	s += '#define SEG_MWR_BASE 0x%x\n' % seg_mwr_base
1147	s += '#define SEG_MWR_SIZE 0x%x\n' % seg_mwr_size
1148	s += '\n'
1149	s += '#define SEG_ROM_BASE 0x%x\n' % seg_rom_base
1150	s += '#define SEG_ROM_SIZE 0x%x\n' % seg_rom_size
1151	s += '\n'
1152	s += '#define SEG_SIM_BASE 0x%x\n' % seg_sim_base
1153	s += '#define SEG_SIM_SIZE 0x%x\n' % seg_sim_size
1154	s += '\n'
1155	s += '#define SEG_NIC_BASE 0x%x\n' % seg_nic_base
1156	s += '#define SEG_NIC_SIZE 0x%x\n' % seg_nic_size
1157	s += '\n'
1158	s += '#define SEG_PIC_BASE 0x%x\n' % seg_pic_base
1159	s += '#define SEG_PIC_SIZE 0x%x\n' % seg_pic_size
1160	s += '\n'
1161	s += '#define SEG_TIM_BASE 0x%x\n' % seg_tim_base
1162	s += '#define SEG_TIM_SIZE 0x%x\n' % seg_tim_size
1163	s += '\n'
1164	s += '#define SEG_TTY_BASE 0x%x\n' % seg_tty_base
1165	s += '#define SEG_TTY_SIZE 0x%x\n' % seg_tty_size
1166	s += '\n'
1167	s += '#define SEG_XCU_BASE 0x%x\n' % seg_xcu_base
1168	s += '#define SEG_XCU_SIZE 0x%x\n' % seg_xcu_size
1169	s += '\n'
1170	s += '#define SEG_RDK_BASE 0x%x\n' % seg_rdk_base
1171	s += '#define SEG_RDK_SIZE 0x%x\n' % seg_rdk_size
1172	s += '\n'
1173	s += '#define PERI_CLUSTER_INCREMENT 0x%x\n' % self.peri_increment
1174	s += '\n'
1175
1176	s += '/* physical base addresses for identity mapped vsegs */\n'
1177	s += '/* used by the GietVM OS */\n'
1178	s += '\n'
1179	s += '#define SEG_BOOT_MAPPING_BASE 0x%x\n' % boot_mapping_base
1180	s += '#define SEG_BOOT_MAPPING_SIZE 0x%x\n' % boot_mapping_size
1181	s += '\n'
1182	s += '#define SEG_BOOT_CODE_BASE 0x%x\n' % boot_code_base
1183	s += '#define SEG_BOOT_CODE_SIZE 0x%x\n' % boot_code_size
1184	s += '\n'
1185	s += '#define SEG_BOOT_DATA_BASE 0x%x\n' % boot_data_base
1186	s += '#define SEG_BOOT_DATA_SIZE 0x%x\n' % boot_data_size
1187	s += '\n'
1188	s += '#define SEG_BOOT_STACK_BASE 0x%x\n' % boot_stack_base
1189	s += '#define SEG_BOOT_STACK_SIZE 0x%x\n' % boot_stack_size
1190	s += '#endif\n'
1191
1192	return s
1193
1194	# end of hard_config()
1195
1196	#######################
1197	def netbsd_dts( self ): # compute string for netbsd.dts file generation,
1198	# used for netbsd configuration
1199	# header
1200	s = '/dts-v1/;\n'
1201	s += '\n'
1202	s += '/{\n'
1203	s += ' #address-cells = <2>;\n'
1204	s += ' #size-cells = <1>;\n'
1205
1206	# cpus (for each cluster)
1207	s += ' cpus {\n'
1208	s += ' #address-cells = <1>;\n'
1209	s += ' #size-cells = <0>;\n'
1210
1211	for cluster in self.clusters:
1212	for proc in cluster.procs:
1213	proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + proc.lpid
1214
1215	s += ' Mips,32@0x%x {\n' % proc_id
1216	s += ' device_type = "cpu";\n'
1217	s += ' icudev_type = "cpu:mips";\n'
1218	s += ' name = "Mips,32";\n'
1219	s += ' reg = <0x%x>;\n' % proc_id
1220	s += ' };\n'
1221	s += '\n'
1222
1223	s += ' };\n'
1224
1225	# rams (for each cluster)
1226	for cluster in self.clusters:
1227	for pseg in cluster.psegs:
1228
1229	if ( pseg.segtype == 'RAM' ):
1230	msb = pseg.base >> 32
1231	lsb = pseg.base & 0xFFFFFFFF
1232	size = pseg.size
1233
1234	s += ' %s@0x%x {\n' % (pseg.name, pseg.base)
1235	s += ' cached = <1>;\n'
1236	s += ' device_type = "memory";\n'
1237	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1238	s += ' };\n'
1239
1240	# peripherals (for each cluster)
1241	for cluster in self.clusters:
1242
1243	# research XCU component
1244	found_xcu = False
1245	for periph in cluster.periphs:
1246	if ( (periph.ptype == 'XCU') ):
1247	found_xcu = True
1248	xcu = periph
1249	msb = periph.pseg.base >> 32
1250	lsb = periph.pseg.base & 0xFFFFFFFF
1251	size = periph.pseg.size
1252
1253	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1254	s += ' device_type = "soclib:xicu:root";\n'
1255	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1256	s += ' input_lines = <%d>;\n' % periph.arg
1257	s += ' ipis = <%d>;\n' % periph.arg
1258	s += ' timers = <%d>;\n' % periph.arg
1259
1260	output_id = 0 # output index from XCU
1261	for lpid in xrange ( len(cluster.procs) ): # destination processor index
1262	for itid in xrange ( self.irq_per_proc ): # input irq index on processor
1263	proc_id = (((cluster.x << self.y_width) + cluster.y) * self.procs_max) + lpid
1264	s += ' out@%d {\n' % output_id
1265	s += ' device_type = "soclib:xicu:filter";\n'
1266	s += ' irq = <&{/cpus/Mips,32@0x%x} %d>;\n' % (proc_id, itid)
1267	s += ' output_line = <%d>;\n' % output_id
1268	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1269	s += ' };\n'
1270
1271	output_id += 1
1272
1273	s += ' };\n'
1274
1275	# research PIC component
1276	found_pic = False
1277	for periph in cluster.periphs:
1278	if ( periph.ptype == 'PIC' ):
1279	found_pic = True
1280	pic = periph
1281	msb = periph.pseg.base >> 32
1282	lsb = periph.pseg.base & 0xFFFFFFFF
1283	size = periph.pseg.size
1284
1285	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1286	s += ' device_type = "soclib:pic:root";\n'
1287	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1288	s += ' input_lines = <%d>;\n' % periph.channels
1289	s += ' };\n'
1290
1291	if ( (found_xcu == False) and (found_pic == False) and (len(cluster.periphs) > 0) ):
1292	print '[genmap error] in netbsd_dts() : No XCU/PIC in cluster(%d,%d)' % (cluster.x, cluster.y)
1293	sys.exit(1)
1294
1295	if ( found_pic == True ): irq_tgt = pic
1296	else: irq_tgt = xcu
1297
1298	# get all others peripherals in cluster
1299	for periph in cluster.periphs:
1300	msb = periph.pseg.base >> 32
1301	lsb = periph.pseg.base & 0xFFFFFFFF
1302	size = periph.pseg.size
1303
1304	# research DMA component
1305	if ( periph.ptype == 'DMA' ):
1306
1307	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1308	s += ' device_type = "soclib:dma";\n'
1309	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1310	s += ' channel_count = <%d>;\n' % periph.channels
1311
1312	# multi-channels : get HWI index (to XCU) for each channel
1313	for channel in xrange( periph.channels ):
1314	hwi_id = 0xFFFFFFFF
1315	for irq in xcu.irqs:
1316	if ( (irq.isrtype == 'ISR_DMA') and (irq.channel == channel) ):
1317	hwi_id = irq.srcid
1318	if ( hwi_id == 0xFFFFFFFF ):
1319	print '[genmap error] in netbsd.dts() ISR_DMA channel %d not found' % channel
1320	sys.exit(1)
1321
1322	name = '%s@0x%x' % (xcu.pseg.name, xcu.pseg.base)
1323	s += ' irq@%d{\n' % channel
1324	s += ' device_type = "soclib:periph:irq";\n'
1325	s += ' output_line = <%d>;\n' % channel
1326	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1327	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1328	s += ' };\n'
1329
1330	s += ' };\n'
1331
1332	# research MMC component
1333	elif ( periph.ptype == 'MMC' ):
1334
1335	# get irq line index associated to MMC in XCU
1336	irq_in = 0xFFFFFFFF
1337	for irq in xcu.irqs:
1338	if ( irq.isrtype == 'ISR_MMC' ): irq_in = irq.srcid
1339	if ( irq_in == 0xFFFFFFFF ):
1340	print '[genmap error] in netbsd.dts() ISR_MMC not found'
1341	sys.exit(1)
1342
1343	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1344	s += ' device_type = "soclib:mmc";\n'
1345	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
1346	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1347	s += ' };\n'
1348
1349	# research FBF component
1350	elif ( periph.ptype == 'FBF' ):
1351
1352	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1353	s += ' device_type = "soclib:framebuffer";\n'
1354	s += ' mode = <32>;\n' # bits par pixel
1355	s += ' width = <%d>;\n' % periph.arg
1356	s += ' height = <%d>;\n' % periph.arg
1357	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1358	s += ' };\n'
1359
1360	# research IOC component
1361	elif ( periph.ptype == 'IOC' ):
1362
1363	if ( periph.subtype == 'BDV' ):
1364
1365	# get irq line index associated to bdv
1366	irq_in = 0xFFFFFFFF
1367	for irq in irq_tgt.irqs:
1368	if ( irq.isrtype == 'ISR_BDV' ): irq_in = irq.srcid
1369	if ( irq_in == 0xFFFFFFFF ):
1370	print '[genmap error] in netbsd.dts() ISR_BDV not found'
1371	sys.exit(1)
1372
1373	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1374	s += ' device_type = "soclib:blockdevice";\n'
1375	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
1376	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1377	s += ' };\n'
1378
1379	elif ( periph.subtype == 'HBA' ):
1380	print '[genmap error] in netbsd_dts() : HBA peripheral not supported by NetBSD'
1381	sys.exit(1)
1382
1383	elif ( periph.subtype == 'SPI' ):
1384
1385	# get irq line index associated to spi
1386	irq_in = 0xFFFFFFFF
1387	for irq in irq_tgt.irqs:
1388	if ( irq.isrtype == 'ISR_SPI' ): irq_in = irq.srcid
1389	if ( irq_in == 0xFFFFFFFF ):
1390	print '[genmap error] in netbsd.dts() ISR_SPI not found'
1391	sys.exit(1)
1392
1393	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1394	s += ' device_type = "soclib:spi";\n'
1395	s += ' irq = <&{/%s@0x%x} %d>;\n' % (irq_tgt.pseg.name, irq_tgt.pseg.base, irq_in)
1396	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1397	s += ' };\n'
1398
1399	# research ROM component
1400	elif ( periph.ptype == 'ROM' ):
1401
1402	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1403	s += ' device_type = "rom";\n'
1404	s += ' cached = <1>;\n'
1405	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1406	s += ' };\n'
1407
1408	# research SIM component
1409	elif ( periph.ptype == 'SIM' ):
1410
1411	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1412	s += ' device_type = "soclib:simhelper";\n'
1413	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1414	s += ' };\n'
1415
1416	# research TTY component
1417	elif ( periph.ptype == 'TTY' ):
1418
1419	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1420	s += ' device_type = "soclib:tty";\n'
1421	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1422	s += ' channel_count = < %d >;\n' % periph.channels
1423
1424	# multi-channels : get HWI index (to XCU or PIC) for each channel
1425	for channel in xrange( periph.channels ):
1426	hwi_id = 0xFFFFFFFF
1427	for irq in irq_tgt.irqs:
1428	if ( (irq.isrtype == 'ISR_TTY_RX') and (irq.channel == channel) ):
1429	hwi_id = irq.srcid
1430	if ( hwi_id == 0xFFFFFFFF ):
1431	print '[genmap error] in netbsd.dts() ISR_TTY_RX channel %d not found' % channel
1432	sys.exit(1)
1433
1434	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1435	s += ' irq@%d{\n' % channel
1436	s += ' device_type = "soclib:periph:irq";\n'
1437	s += ' output_line = <%d>;\n' % channel
1438	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1439	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1440	s += ' };\n'
1441
1442	s += ' };\n'
1443
1444	# research IOB component
1445	elif ( periph.ptype == 'IOB' ):
1446
1447	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1448	s += ' device_type = "soclib:iob";\n'
1449	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1450	s += ' };\n'
1451
1452	# research NIC component
1453	elif ( periph.ptype == 'NIC' ):
1454
1455	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1456	s += ' device_type = "soclib:nic";\n'
1457	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1458	s += ' channel_count = < %d >;\n' % periph.channels
1459
1460	# multi-channels : get HWI index (to XCU or PIC) for RX & TX IRQs
1461	# RX IRQ : (2channel) / TX IRQs : (2channel + 1)
1462	for channel in xrange( periph.channels ):
1463	hwi_id = 0xFFFFFFFF
1464	for irq in irq_tgt.irqs:
1465	if ( (irq.isrtype == 'ISR_NIC_RX') and (irq.channel == channel) ):
1466	hwi_id = irq.srcid
1467	if ( hwi_id == 0xFFFFFFFF ):
1468	print '[genmap error] in netbsd.dts() ISR_NIC_RX channel %d not found' % channel
1469	sys.exit(1)
1470
1471	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1472	s += ' irq_rx@%d{\n' % channel
1473	s += ' device_type = "soclib:periph:irq";\n'
1474	s += ' output_line = <%d>;\n' % (2*channel)
1475	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1476	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1477	s += ' };\n'
1478
1479	hwi_id = 0xFFFFFFFF
1480	for irq in irq_tgt.irqs:
1481	if ( (irq.isrtype == 'ISR_NIC_TX') and (irq.channel == channel) ):
1482	hwi_id = irq.srcid
1483	if ( hwi_id == 0xFFFFFFFF ):
1484	print '[genmap error] in netbsd.dts() ISR_NIC_TX channel %d not found' % channel
1485	sys.exit(1)
1486
1487	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1488	s += ' irq_tx@%d{\n' % channel
1489	s += ' device_type = "soclib:periph:irq";\n'
1490	s += ' output_line = <%d>;\n' % (2*channel + 1)
1491	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1492	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1493	s += ' };\n'
1494
1495	s += ' };\n'
1496
1497	# research CMA component
1498	elif ( periph.ptype == 'CMA' ):
1499
1500	s += ' %s@0x%x {\n' % (periph.pseg.name, periph.pseg.base)
1501	s += ' device_type = "soclib:cma";\n'
1502	s += ' reg = <0x%x 0x%x 0x%x>;\n' % (msb, lsb, size)
1503	s += ' channel_count = < %d >;\n' % periph.channels
1504
1505	# multi-channels : get HWI index (to XCU or PIC) for each channel
1506	for channel in xrange( periph.channels ):
1507	hwi_id = 0xFFFFFFFF
1508	for irq in irq_tgt.irqs:
1509	if ( (irq.isrtype == 'ISR_CMA') and (irq.channel == channel) ):
1510	hwi_id = irq.srcid
1511	if ( hwi_id == 0xFFFFFFFF ):
1512	print '[genmap error] in netbsd.dts() ISR_CMA channel %d not found' % channel
1513	sys.exit(1)
1514
1515	name = '%s@0x%x' % (irq_tgt.pseg.name, irq_tgt.pseg.base)
1516	s += ' irq@%d{\n' % channel
1517	s += ' device_type = "soclib:periph:irq";\n'
1518	s += ' output_line = <%d>;\n' % channel
1519	s += ' irq = <&{/%s} %d>;\n' % (name, hwi_id)
1520	s += ' parent = <&{/%s@0x%x}>;\n' % (periph.pseg.name, periph.pseg.base)
1521	s += ' };\n'
1522
1523	s += ' };\n'
1524
1525	# research TIM component
1526	elif ( periph.ptype == 'TIM' ):
1527
1528	print '[genmap error] in netbsd_dts() : TIM peripheral not supported by NetBSD'
1529	sys.exit(1)
1530
1531	# research MWR component
1532	elif ( periph.ptype == 'MWR' ):
1533
1534	print '[genmap error] in netbsd_dts() : MWR peripheral not supported by NetBSD'
1535	sys.exit(1)
1536
1537	# research ICU component
1538	elif ( periph.ptype == 'ICU' ):
1539	print '[genmap error] in netbsd_dts() : ICU peripheral not supported by NetBSD'
1540	sys.exit(1)
1541
1542	# topology
1543	s += '\n'
1544	s += ' topology {\n'
1545	s += ' #address-cells = <2>;\n'
1546	s += ' #size-cells = <0>;\n'
1547	for cluster in self.clusters:
1548	s += ' cluster@%d,%d {\n' % (cluster.x, cluster.y)
1549	s += ' reg = <%d %d>;\n' % (cluster.x, cluster.y)
1550	s += ' devices = <\n'
1551
1552	offset = ((cluster.x << self.y_width) + cluster.y) * self.procs_max
1553	for proc in cluster.procs:
1554	s += ' &{/cpus/Mips,32@0x%x}\n' % (offset + proc.lpid)
1555	for periph in cluster.periphs:
1556	s += ' &{/%s@0x%x}\n' % (periph.pseg.name, periph.pseg.base)
1557
1558	s += ' >;\n'
1559	s += ' };\n'
1560	s += ' };\n'
1561	s += '};\n'
1562
1563	return s
1564	# end netbsd_dts( )
1565
1566	###########################
1567	def almos_archinfo( self ): # compute string for arch.info file generation,
1568	# used for almos configuration
1569	# header
1570	s = '# arch.info file generated by genmap for %s\n' % self.name
1571	s += '\n'
1572	s += '[HEADER]\n'
1573	s += ' REVISION=1\n'
1574	s += ' ARCH=%s\n' % self.name
1575	s += ' XMAX=%d\n' % self.x_size
1576	s += ' YMAX=%d\n' % self.y_size
1577	s += ' CPU_NR=%d\n' % self.procs_max
1578	s += '\n'
1579
1580	# clusters
1581	cluster_id = 0
1582	for cluster in self.clusters:
1583
1584	ram = None
1585	nb_cpus = len( cluster.procs )
1586	nb_devs = len( cluster.periphs )
1587	if ( len( cluster.coprocs ) != 0 ):
1588	print 'Error in almos_archinfo() coprocessors not supported yet'
1589	sys.exit(1)
1590
1591	# search a RAM
1592	for pseg in cluster.psegs:
1593	if ( pseg.segtype == 'RAM' ):
1594	ram = pseg
1595	nb_devs += 1
1596
1597	# search XCU to get IRQs indexes if cluster contains peripherals
1598	if ( len( cluster.periphs ) != 0 ):
1599	tty_irq_id = None
1600	bdv_irq_id = None
1601	dma_irq_id = None
1602
1603	for periph in cluster.periphs:
1604	if ( periph.ptype == 'XCU' ):
1605	# scan irqs
1606	for irq in periph.irqs:
1607	if ( irq.isrtype == 'ISR_TTY_RX' ) : tty_irq_id = irq.srcid
1608	if ( irq.isrtype == 'ISR_BDV' ) : bdv_irq_id = irq.srcid
1609	if ( irq.isrtype == 'ISR_DMA' ) : dma_irq_id = irq.srcid
1610
1611	# Build the cluster description
1612	s += '[CLUSTER]\n'
1613	s += ' CID=%d\n' % cluster_id
1614	s += ' ARCH_CID=0x%x\n' % ((cluster.x << self.y_width) + cluster.y)
1615	s += ' CPU_NR=%d\n' % nb_cpus
1616	s += ' DEV_NR=%d\n' % nb_devs
1617
1618
1619	# Handling RAM when cluster contain a RAM
1620	if (ram != None ):
1621	base = ram.base
1622	size = ram.size
1623	irqid = -1
1624	s += ' DEVID=RAM'
1625	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1626
1627	# Handling peripherals
1628	for periph in cluster.periphs:
1629	base = periph.pseg.base
1630	size = periph.pseg.size
1631
1632	if ( periph.ptype == 'XCU' ):
1633
1634	s += ' DEVID=XICU'
1635	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1636
1637	elif ( (periph.ptype == 'TTY')
1638	and (tty_irq_id != None) ):
1639
1640	s += ' DEVID=TTY'
1641	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, tty_irq_id )
1642
1643	elif ( (periph.ptype == 'DMA')
1644	and (dma_irq_id != None) ):
1645
1646	s += ' DEVID=DMA'
1647	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, dma_irq_id )
1648
1649	elif ( periph.ptype == 'FBF' ):
1650
1651	s += ' DEVID=FB'
1652	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1653
1654	elif ( (periph.ptype == 'IOC') and (periph.subtype == 'BDV')
1655	and (bdv_irq_id != None) ):
1656
1657	s += ' DEVID=BLKDEV'
1658	s += ' BASE=0x%x SIZE=0x%x IRQ=%d\n' % ( base, size, bdv_irq_id )
1659
1660	elif ( periph.ptype == 'PIC' ):
1661
1662	s += ' DEVID=IOPIC'
1663	s += ' BASE=0x%x SIZE=0x%x IRQ=-1\n' % ( base, size )
1664
1665	else:
1666	print '# Warning from almos_archinfo() in cluster[%d,%d]' \
1667	% (cluster.x, cluster.y)
1668	print '# peripheral type %s/%s not supported yet\n' \
1669	% ( periph.ptype, periph.subtype )
1670
1671	cluster_id += 1
1672
1673	return s
1674
1675	# end of almos_archinfo()
1676
1677
1678
1679
1680
1681
1682
1683
1684	###########################################################################################
1685	class Cluster ( object ):
1686	###########################################################################################
1687	def __init__( self,
1688	x,
1689	y ):
1690
1691	self.index = 0 # global index (set by Mapping constructor)
1692	self.x = x # x coordinate
1693	self.y = y # y coordinate
1694	self.psegs = [] # filled by addRam() or addPeriph()
1695	self.procs = [] # filled by addProc()
1696	self.coprocs = [] # filled by addCoproc()
1697	self.periphs = [] # filled by addPeriph()
1698
1699	return
1700
1701	################
1702	def xml( self ): # xml for a cluster
1703
1704	s = ' <cluster x="%d" y="%d" >\n' % (self.x, self.y)
1705	for pseg in self.psegs: s += pseg.xml()
1706	for proc in self.procs: s += proc.xml()
1707	for copr in self.coprocs: s += copr.xml()
1708	for peri in self.periphs: s += peri.xml()
1709	s += ' </cluster>\n'
1710
1711	return s
1712
1713	#############################################
1714	def cbin( self, mapping, verbose, expected ): # C binary structure for Cluster
1715
1716	if ( verbose ):
1717	print '*** cbin for cluster [%d,%d]' % (self.x, self.y)
1718
1719	# check index
1720	if (self.index != expected):
1721	print '[genmap error] in Cluster.cbin() : cluster global index = %d / expected = %d' \
1722	% (self.index, expected )
1723	sys.exit(1)
1724
1725	# compute global index for first pseg
1726	if ( len(self.psegs) > 0 ):
1727	pseg_id = self.psegs[0].index
1728	else:
1729	pseg_id = 0
1730
1731	# compute global index for first proc
1732	if ( len(self.procs) > 0 ):
1733	proc_id = self.procs[0].index
1734	else:
1735	proc_id = 0
1736
1737	# compute global index for first coproc
1738	if ( len(self.coprocs) > 0 ):
1739	coproc_id = self.coprocs[0].index
1740	else:
1741	coproc_id = 0
1742
1743	# compute global index for first periph
1744	if ( len(self.periphs) > 0 ):
1745	periph_id = self.periphs[0].index
1746	else:
1747	periph_id = 0
1748
1749	byte_stream = bytearray()
1750	byte_stream += mapping.int2bytes( 4 , self.x ) # x coordinate
1751	byte_stream += mapping.int2bytes( 4 , self.y ) # x coordinate
1752	byte_stream += mapping.int2bytes( 4 , len( self.psegs ) ) # number of psegs in cluster
1753	byte_stream += mapping.int2bytes( 4 , pseg_id ) # first pseg global index
1754	byte_stream += mapping.int2bytes( 4 , len( self.procs ) ) # number of procs in cluster
1755	byte_stream += mapping.int2bytes( 4 , proc_id ) # first proc global index
1756	byte_stream += mapping.int2bytes( 4 , len( self.coprocs ) ) # number of coprocs in cluster
1757	byte_stream += mapping.int2bytes( 4 , coproc_id ) # first coproc global index
1758	byte_stream += mapping.int2bytes( 4 , len( self.periphs ) ) # number of periphs in cluster
1759	byte_stream += mapping.int2bytes( 4 , periph_id ) # first periph global index
1760
1761	if ( verbose ):
1762	print 'nb_psegs = %d' % len( self.psegs )
1763	print 'pseg_id = %d' % pseg_id
1764	print 'nb_procs = %d' % len( self.procs )
1765	print 'proc_id = %d' % proc_id
1766	print 'nb_coprocs = %d' % len( self.coprocs )
1767	print 'coproc_id = %d' % coproc_id
1768	print 'nb_periphs = %d' % len( self.periphs )
1769	print 'periph_id = %d' % periph_id
1770
1771	return byte_stream
1772
1773	###########################################################################################
1774	class Vspace( object ):
1775	###########################################################################################
1776	def __init__( self,
1777	name,
1778	startname ):
1779
1780	self.index = 0 # global index ( set by addVspace() )
1781	self.name = name # vspace name
1782	self.startname = startname # name of vobj containing the start_vector
1783	self.vsegs = []
1784	self.tasks = []
1785
1786	return
1787
1788	################
1789	def xml( self ): # xml for one vspace
1790
1791	s = ' <vspace name="%s" startname="%s" >\n' % ( self.name, self.startname )
1792	for vseg in self.vsegs: s += vseg.xml()
1793	for task in self.tasks: s += task.xml()
1794	s += ' </vspace>\n'
1795
1796	return s
1797
1798	#############################################
1799	def cbin( self, mapping, verbose, expected ): # C binary structure for Vspace
1800
1801	if ( verbose ):
1802	print '*** cbin for vspace %s' % (self.name)
1803
1804	# check index
1805	if (self.index != expected):
1806	print '[genmap error] in Vspace.cbin() : vspace global index = %d / expected = %d' \
1807	% (self.index, expected )
1808	sys.exit(1)
1809
1810	# compute global index for vobj containing start_vector
1811	vobj_start_id = 0xFFFFFFFF
1812	for vseg in self.vsegs:
1813	if ( vseg.vobjs[0].name == self.startname ):
1814	vobj_start_id = vseg.vobjs[0].index
1815	if ( vobj_start_id == 0xFFFFFFFF ):
1816	print '[genmap error] in Vspace.cbin() : startname %s not found for vspace %s' \
1817	% ( self.startname, self.name )
1818	sys.exit(1)
1819
1820	# compute first vseg, vobj, task global index
1821	first_vseg_id = self.vsegs[0].index
1822	first_vobj_id = self.vsegs[0].vobjs[0].index
1823	first_task_id = self.tasks[0].index
1824
1825	# compute number of vobjs, tasks, vsegs
1826	nb_vsegs = len( self.vsegs )
1827	nb_tasks = len( self.tasks )
1828	nb_vobjs = 0
1829	for vseg in self.vsegs:
1830	nb_vobjs += len( vseg.vobjs )
1831
1832	byte_stream = bytearray()
1833	byte_stream += mapping.str2bytes( 32, self.name ) # vspace name
1834	byte_stream += mapping.int2bytes( 4, vobj_start_id ) # vobj start_vector
1835	byte_stream += mapping.int2bytes( 4, nb_vsegs ) # number of vsegs
1836	byte_stream += mapping.int2bytes( 4, nb_vobjs ) # number of vobjs
1837	byte_stream += mapping.int2bytes( 4, nb_tasks ) # number of tasks
1838	byte_stream += mapping.int2bytes( 4, first_vseg_id ) # first vseg global index
1839	byte_stream += mapping.int2bytes( 4, first_vobj_id ) # first vobj global index
1840	byte_stream += mapping.int2bytes( 4, first_task_id ) # first task global index
1841
1842	if ( verbose ):
1843	print 'start_id = %d' % vobj_start_id
1844	print 'nb_vsegs = %d' % nb_vsegs
1845	print 'nb_vobjs = %d' % nb_vobjs
1846	print 'nb_tasks = %d' % nb_tasks
1847	print 'vseg_id = %d' % first_vseg_id
1848	print 'vobj_id = %d' % first_vobj_id
1849	print 'task_id = %d' % first_task_id
1850
1851	return byte_stream
1852
1853	###########################################################################################
1854	class Task( object ):
1855	###########################################################################################
1856	def __init__( self,
1857	name,
1858	trdid,
1859	x,
1860	y,
1861	p,
1862	stackname,
1863	heapname,
1864	startid,
1865	usetty = False,
1866	usenic = False,
1867	usecma = False,
1868	usehba = False,
1869	usetim = False ):
1870
1871	self.index = 0 # global index value set by addTask()
1872	self.name = name # tsk name
1873	self.trdid = trdid # task index (unique in vspace)
1874	self.x = x # cluster x coordinate
1875	self.y = y # cluster y coordinate
1876	self.p = p # processor local index
1877	self.stackname = stackname # name of vobj containing the stack
1878	self.heapname = heapname # name of vobj containing the heap
1879	self.startid = startid # index in start_vector
1880	self.usetty = usetty # request a private TTY channel
1881	self.usenic = usenic # request a private NIC channel
1882	self.usecma = usecma # request a private CMA channel
1883	self.usehba = usehba # request a private HBA channel
1884	self.usetim = usetim # request a private TIM channel
1885	return
1886
1887	################
1888	def xml( self ): # xml for one task
1889
1890	s = ' <task name="%s"' % self.name
1891	s += ' trdid="%d"' % self.trdid
1892	s += ' x="%d"' % self.x
1893	s += ' y="%d"' % self.y
1894	s += ' p="%d"' % self.p
1895	s += ' stackname="%s"' % self.stackname
1896	s += ' heapname="%s"' % self.heapname
1897	s += ' startid="%d"' % self.startid
1898	if self.usetty != 0: s += ' usetty="1"'
1899	if self.usenic != 0: s += ' usenic="1"'
1900	if self.usecma != 0: s += ' usehba="1"'
1901	if self.usehba != 0: s += ' usehba="1"'
1902	if self.usetim != 0: s += ' usehba="1"'
1903	s += ' />\n'
1904
1905	return s
1906
1907	#####################################################
1908	def cbin( self, mapping, verbose, expected, vspace ): # C binary data structure for Task
1909
1910	if ( verbose ):
1911	print '*** cbin for task %s in vspace %s' % (self.name, vspace.name)
1912
1913	# check index
1914	if (self.index != expected):
1915	print '[genmap error] in Task.cbin() : task global index = %d / expected = %d' \
1916	% (self.index, expected )
1917	sys.exit(1)
1918
1919	# compute cluster global index
1920	cluster_id = (self.x * mapping.y_size) + self.y
1921
1922	# compute vobj local index for stack
1923	vobj_stack_id = 0xFFFFFFFF
1924	for vseg in vspace.vsegs:
1925	if ( vseg.vobjs[0].name == self.stackname ):
1926	vobj_stack_id = vseg.vobjs[0].index
1927	if ( vobj_stack_id == 0xFFFFFFFF ):
1928	print '[genmap error] in Task.cbin() : stackname %s not found for task %s in vspace %s' \
1929	% ( self.stackname, self.name, vspace.name )
1930	sys.exit(1)
1931
1932	# compute vobj local index for heap
1933	vobj_heap_id = 0xFFFFFFFF
1934	for vseg in vspace.vsegs:
1935	if ( vseg.vobjs[0].name == self.heapname ):
1936	vobj_heap_id = vseg.vobjs[0].index
1937	if ( vobj_heap_id == 0xFFFFFFFF ):
1938	print '[genmap error] in Task.cbin() : heapname %s not found for task %s in vspace %s' \
1939	% ( self.heapname, self.name, vspace.name )
1940	sys.exit(1)
1941
1942	byte_stream = bytearray()
1943	byte_stream += mapping.str2bytes( 32, self.name ) # task name in vspace
1944	byte_stream += mapping.int2bytes( 4, cluster_id ) # cluster global index
1945	byte_stream += mapping.int2bytes( 4, self.p ) # processor local index in cluster
1946	byte_stream += mapping.int2bytes( 4, self.trdid ) # thread local index in vspace
1947	byte_stream += mapping.int2bytes( 4, vobj_stack_id ) # stack vobj local index
1948	byte_stream += mapping.int2bytes( 4, vobj_heap_id ) # heap vobj local index
1949	byte_stream += mapping.int2bytes( 4, self.startid ) # index in start vector
1950	byte_stream += mapping.int2bytes( 4, self.usetty ) # TTY channel required
1951	byte_stream += mapping.int2bytes( 4, self.usenic ) # NIC channel required
1952	byte_stream += mapping.int2bytes( 4, self.usecma ) # CMA channel required
1953	byte_stream += mapping.int2bytes( 4, self.usehba ) # IOC channel required
1954	byte_stream += mapping.int2bytes( 4, self.usetim ) # TIM channel required
1955
1956	if ( verbose ):
1957	print 'clusterid = %d' % cluster_id
1958	print 'lpid = %d' % self.p
1959	print 'trdid = %d' % self.trdid
1960	print 'stackid = %d' % vobj_stack_id
1961	print 'heapid = %d' % vobj_heap_id
1962	print 'startid = %d' % self.startid
1963
1964	return byte_stream
1965
1966	###########################################################################################
1967	class Vseg( object ):
1968	###########################################################################################
1969	def __init__( self,
1970	name,
1971	vbase,
1972	mode,
1973	x,
1974	y,
1975	psegname,
1976	identity = False,
1977	local = False ):
1978
1979	assert mode in VSEGMODES
1980
1981	self.index = 0 # global index ( set by addVseg() )
1982	self.name = name # vseg name
1983	self.vbase = vbase & 0xFFFFFFFF # virtual base address in vspace
1984	self.mode = mode # CXWU access rights
1985	self.x = x # x coordinate of destination cluster
1986	self.y = y # y coordinate of destination cluster
1987	self.psegname = psegname # name of pseg in destination cluster
1988	self.identity = identity # identity mapping required
1989	self.local = local # one copy per cluster
1990	self.vobjs = []
1991	return
1992
1993	################
1994	def xml( self ): # xml for one vseg
1995
1996	s = ' <vseg name="%s" vbase="0x%x" mode="%s" x="%d" y="%d" psegname="%s"' \
1997	% ( self.name, self.vbase, self.mode, self.x, self.y, self.psegname )
1998	if ( self.identity ): s += ' ident="1"'
1999	if ( self.local ): s += ' local="1"'
2000	s += ' >\n'
2001	for vobj in self.vobjs: s += vobj.xml()
2002	s += ' </vseg>\n'
2003
2004	return s
2005
2006	#############################################
2007	def cbin( self, mapping, verbose, expected ): # C binary structure for Vseg
2008
2009	if ( verbose ):
2010	print '*** cbin for vseg[%d] %s' % (self.index, self.name)
2011
2012	# check index
2013	if (self.index != expected):
2014	print '[genmap error] in Vseg.cbin() : vseg global index = %d / expected = %d' \
2015	% (self.index, expected )
2016	sys.exit(1)
2017
2018	# compute pseg_id
2019	pseg_id = 0xFFFFFFFF
2020	cluster_id = (self.x * mapping.y_size) + self.y
2021	cluster = mapping.clusters[cluster_id]
2022	for pseg in cluster.psegs:
2023	if (self.psegname == pseg.name):
2024	pseg_id = pseg.index
2025	if (pseg_id == 0xFFFFFFFF):
2026	print '[genmap error] in Vseg.cbin() : psegname %s not found for vseg %s in cluster %d' \
2027	% ( self.psegname, self.name, cluster_id )
2028	sys.exit(1)
2029
2030	# compute numerical value for mode
2031	mode_id = 0xFFFFFFFF
2032	for x in xrange( len(VSEGMODES) ):
2033	if ( self.mode == VSEGMODES[x] ):
2034	mode_id = x
2035	if ( mode_id == 0xFFFFFFFF ):
2036	print '[genmap error] in Vseg.cbin() : undefined vseg mode %s' % self.mode
2037	sys.exit(1)
2038
2039	# compute vobj_id
2040	vobj_id = self.vobjs[0].index
2041
2042	byte_stream = bytearray()
2043	byte_stream += mapping.str2bytes( 32, self.name ) # vseg name
2044	byte_stream += mapping.int2bytes( 4, self.vbase ) # virtual base address
2045	byte_stream += mapping.int2bytes( 8, 0 ) # physical base address
2046	byte_stream += mapping.int2bytes( 4, 0 ) # vseg size (bytes)
2047	byte_stream += mapping.int2bytes( 4, pseg_id ) # physical segment global index
2048	byte_stream += mapping.int2bytes( 4, mode_id ) # CXWU flags
2049	byte_stream += mapping.int2bytes( 4, len(self.vobjs) ) # number of vobjs in vseg
2050	byte_stream += mapping.int2bytes( 4, vobj_id ) # first vobj global index
2051	byte_stream += mapping.int2bytes( 4, 0 ) # linked list of vsegs on same pseg
2052	byte_stream += mapping.int2bytes( 1, 0 ) # mapped when non zero
2053	byte_stream += mapping.int2bytes( 1, self.identity ) # identity mapping when non zero
2054	byte_stream += mapping.int2bytes( 1, self.local ) # non shared if non zero
2055	byte_stream += mapping.int2bytes( 1, 0 ) # reserved (padding)
2056
2057	if ( verbose ):
2058	print 'vbase = %x' % self.vbase
2059	print 'pseg_id = %d' % pseg_id
2060	print 'mode = %s' % self.mode
2061	print 'nb_vobjs = %d' % len(self.vobjs)
2062	print 'vobj_id = %d' % vobj_id
2063
2064	return byte_stream
2065
2066	###########################################################################################
2067	class Vobj( object ):
2068	###########################################################################################
2069	def __init__( self,
2070	name,
2071	length,
2072	vtype,
2073	binpath = '',
2074	align = 0,
2075	init = 0 ):
2076
2077	assert vtype in ['ELF','BLOB','PTAB','PERI','MWMR','LOCK', \
2078	'BUFFER','BARRIER','CONST','MEMSPACE','SCHED']
2079
2080	assert (vtype != 'ELF') or (binpath != '')
2081
2082	self.index = 0 # global index ( set by addVobj() )
2083	self.name = name # vobj name (unique in vspace)
2084	self.vtype = vtype # vobj type (defined in mapping_info.h)
2085	self.length = length # vobj size (bytes)
2086	self.binpath = binpath # pathname for (ELF type)
2087	self.align = align # required alignment (logarithm of 2)
2088	self.init = init # initialisation value (for BARRIER or MWMR types)
2089
2090	return
2091
2092	################
2093	def xml( self ): # xml for a vobj
2094
2095	s = ' <vobj name="%s" type="%s" length="0x%x"' \
2096	% ( self.name, self.vtype, self.length )
2097	if (self.binpath != ''): s += ' binpath="%s"' % (self.binpath)
2098	if (self.align != 0 ): s += ' align="%d"' % (self.align)
2099	if (self.init != 0 ): s += ' init="%d"' % (self.init)
2100	s += ' />\n'
2101
2102	return s
2103
2104	#############################################
2105	def cbin( self, mapping, verbose, expected ): # C binary structure for Vobj
2106
2107	# check index
2108	if (self.index != expected):
2109	print '[genmap error] in Vobj.cbin() : vobj global index = %d / expected = %d' \
2110	% (self.index, expected )
2111	sys.exit(1)
2112	elif ( verbose ):
2113	print '*** cbin for vobj[%d] %s' % (self.index, self.name)
2114
2115	# compute numerical value for vtype
2116	vtype_int = 0xFFFFFFFF
2117	for x in xrange( len(VOBJTYPES) ):
2118	if ( self.vtype == VOBJTYPES[x] ):
2119	vtype_int = x
2120	if ( vtype_int == 0xFFFFFFFF ):
2121	print '[genmap error] in Vobj.cbin() : undefined vobj type %s' % self.vtype
2122	sys.exit(1)
2123
2124	byte_stream = bytearray()
2125	byte_stream += mapping.str2bytes( 32, self.name ) # vobj name
2126	byte_stream += mapping.str2bytes( 64, self.binpath ) # pathname for .elf file
2127	byte_stream += mapping.int2bytes( 4 , vtype_int ) # vobj type
2128	byte_stream += mapping.int2bytes( 4 , self.length ) # vobj size
2129	byte_stream += mapping.int2bytes( 4 , self.align ) # required alignment
2130	byte_stream += mapping.int2bytes( 4 , 0 ) # virtual base address
2131	byte_stream += mapping.int2bytes( 8 , 0 ) # physical base address
2132	byte_stream += mapping.int2bytes( 4 , self.init ) # init value
2133
2134	if ( verbose ):
2135	print 'binpath = %s' % self.binpath
2136	print 'type = %s' % self.vtype
2137	print 'length = %x' % self.length
2138
2139	return byte_stream
2140
2141	###########################################################################################
2142	class Processor ( object ):
2143	###########################################################################################
2144	def __init__( self,
2145	x,
2146	y,
2147	lpid ):
2148
2149	self.index = 0 # global index ( set by addProc() )
2150	self.x = x # x cluster coordinate
2151	self.y = y # y cluster coordinate
2152	self.lpid = lpid # processor local index
2153
2154	return
2155
2156	################
2157	def xml( self ): # xml for a processor
2158	return ' <proc index="%d" />\n' % (self.lpid)
2159
2160	#############################################
2161	def cbin( self, mapping, verbose, expected ): # C binary structure for Proc
2162
2163	if ( verbose ):
2164	print '*** cbin for proc %d in cluster (%d,%d)' % (self.lpid, self.x, self.y)
2165
2166	# check index
2167	if (self.index != expected):
2168	print '[genmap error] in Proc.cbin() : proc global index = %d / expected = %d' \
2169	% (self.index, expected )
2170	sys.exit(1)
2171
2172	byte_stream = bytearray()
2173	byte_stream += mapping.int2bytes( 4 , self.lpid ) # local index
2174
2175	return byte_stream
2176
2177	###########################################################################################
2178	class Pseg ( object ):
2179	###########################################################################################
2180	def __init__( self,
2181	name,
2182	base,
2183	size,
2184	x,
2185	y,
2186	segtype ):
2187
2188	assert( segtype in PSEGTYPES )
2189
2190	self.index = 0 # global index ( set by addPseg() )
2191	self.name = name # pseg name (unique in cluster)
2192	self.base = base # physical base address
2193	self.size = size # segment size (bytes)
2194	self.x = x # cluster x coordinate
2195	self.y = y # cluster y coordinate
2196	self.segtype = segtype # RAM / PERI (defined in mapping_info.h)
2197
2198	return
2199
2200	################
2201	def xml( self ): # xml for a pseg
2202
2203	return ' <pseg name="%s" type="%s" base="0x%x" length="0x%x" />\n' \
2204	% (self.name, self.segtype, self.base, self.size)
2205
2206	######################################################
2207	def cbin( self, mapping, verbose, expected, cluster ): # C binary structure for Pseg
2208
2209	if ( verbose ):
2210	print '*** cbin for pseg[%d] %s in cluster[%d,%d]' \
2211	% (self.index, self.name, cluster.x, cluster.y)
2212
2213	# check index
2214	if (self.index != expected):
2215	print '[genmap error] in Pseg.cbin() : pseg global index = %d / expected = %d' \
2216	% (self.index, expected )
2217	sys.exit(1)
2218
2219	# compute numerical value for segtype
2220	segtype_int = 0xFFFFFFFF
2221	for x in xrange( len(PSEGTYPES) ):
2222	if ( self.segtype == PSEGTYPES[x] ):
2223	segtype_int = x
2224	if ( segtype_int == 0xFFFFFFFF ):
2225	print '[genmap error] in Pseg.cbin() : undefined segment type %s' % self.segtype
2226	sys.exit(1)
2227
2228	byte_stream = bytearray()
2229	byte_stream += mapping.str2bytes( 32, self.name ) # pseg name
2230	byte_stream += mapping.int2bytes( 8 , self.base ) # physical base address
2231	byte_stream += mapping.int2bytes( 8 , self.size ) # segment length
2232	byte_stream += mapping.int2bytes( 4 , segtype_int ) # segment type
2233	byte_stream += mapping.int2bytes( 4 , cluster.index ) # cluster global index
2234	byte_stream += mapping.int2bytes( 4 , 0 ) # linked list of vsegs
2235
2236	if ( verbose ):
2237	print 'pbase = %x' % self.base
2238	print 'size = %x' % self.size
2239	print 'type = %s' % self.segtype
2240
2241	return byte_stream
2242
2243	###########################################################################################
2244	class Periph ( object ):
2245	###########################################################################################
2246	def __init__( self,
2247	pseg, # associated pseg
2248	ptype, # peripheral type
2249	subtype = 'NONE', # peripheral subtype
2250	channels = 1, # for multi-channels peripherals
2251	arg = 0 ): # optional argument (semantic depends on ptype)
2252
2253	assert ptype in PERIPHTYPES
2254
2255	assert subtype in PERIPHSUBTYPES
2256
2257	self.index = 0 # global index ( set by addPeriph() )
2258	self.channels = channels
2259	self.ptype = ptype
2260	self.subtype = subtype
2261	self.arg = arg
2262	self.pseg = pseg
2263	self.irqs = []
2264	return
2265
2266	################
2267	def xml( self ): # xml for a periph
2268
2269	s = ' <periph type="%s"' % self.ptype
2270	s += ' subtype="%s"' % self.subtype
2271	s += ' psegname="%s"' % self.pseg.name
2272	s += ' channels="%d"' % self.channels
2273	s += ' arg="%d" >\n' % self.arg
2274	if ( (self.ptype == 'PIC') or (self.ptype == 'XCU') or (self.ptype == 'ICU') ):
2275	for irq in self.irqs: s += irq.xml()
2276	s += ' </periph>\n'
2277
2278	return s
2279
2280	#############################################
2281	def cbin( self, mapping, verbose, expected ): # C binary structure for Periph
2282
2283	if ( verbose ):
2284	print '*** cbin for periph %s in cluster [%d,%d]' \
2285	% (self.ptype, self.pseg.x, self.pseg.y)
2286
2287	# check index
2288	if (self.index != expected):
2289	print '[genmap error] in Periph.cbin() : periph global index = %d / expected = %d' \
2290	% (self.index, expected )
2291	sys.exit(1)
2292
2293	# compute pseg global index
2294	pseg_id = self.pseg.index
2295
2296	# compute first irq global index
2297	if ( len(self.irqs) > 0 ):
2298	irq_id = self.irqs[0].index
2299	else:
2300	irq_id = 0
2301
2302	# compute numerical value for ptype
2303	ptype_id = 0xFFFFFFFF
2304	for x in xrange( len(PERIPHTYPES) ):
2305	if ( self.ptype == PERIPHTYPES[x] ): ptype_id = x
2306	if ( ptype_id == 0xFFFFFFFF ):
2307	print '[genmap error] in Periph.cbin() : undefined peripheral type %s' % self.ptype
2308	sys.exit(1)
2309
2310	# compute numerical value for subtype
2311	subtype_id = 0xFFFFFFFF
2312	for x in xrange( len(PERIPHSUBTYPES) ):
2313	if ( self.subtype == PERIPHSUBTYPES[x] ): subtype_id = x
2314
2315	# compute
2316	byte_stream = bytearray()
2317	byte_stream += mapping.int2bytes( 4 , ptype_id ) # peripheral type
2318	byte_stream += mapping.int2bytes( 4 , subtype_id ) # peripheral subtype
2319	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
2320	byte_stream += mapping.int2bytes( 4 , self.channels ) # number of channels
2321	byte_stream += mapping.int2bytes( 4 , self.arg ) # optionnal argument
2322	byte_stream += mapping.int2bytes( 4 , len( self.irqs ) ) # number of input irqs
2323	byte_stream += mapping.int2bytes( 4 , irq_id ) # first irq global index
2324
2325	if ( verbose ):
2326	print 'ptype = %d' % ptype_id
2327	print 'pseg_id = %d' % pseg_id
2328	print 'nb_irqs = %d' % len( self.irqs )
2329	print 'irq_id = %d' % irq_id
2330	return byte_stream
2331
2332	###########################################################################################
2333	class Irq ( object ):
2334	###########################################################################################
2335	def __init__( self,
2336	irqtype, # input IRQ type : HWI / WTI / PTI (for XCU only)
2337	srcid, # input IRQ index (for XCU or PIC)
2338	isrtype, # Type of ISR to be executed
2339	channel = 0 ): # channel index for multi-channel ISR
2340
2341	assert irqtype in IRQTYPES
2342	assert isrtype in ISRTYPES
2343	assert srcid < 32
2344
2345	self.index = 0 # global index ( set by addIrq() )
2346	self.irqtype = irqtype # IRQ type
2347	self.srcid = srcid # source IRQ index
2348	self.isrtype = isrtype # ISR type
2349	self.channel = channel # channel index (for multi-channels ISR)
2350	return
2351
2352	################
2353	def xml( self ): # xml for Irq
2354
2355	return ' <irq srctype="%s" srcid="%d" isr="%s" channel="%d" />\n' \
2356	% ( self.irqtype, self.srcid, self.isrtype, self.channel )
2357
2358	#############################################
2359	def cbin( self, mapping, verbose, expected ): # C binary structure for Irq
2360
2361	if ( verbose ):
2362	print '*** cbin for irq[%d]' % (self.index)
2363
2364	# check index
2365	if (self.index != expected):
2366	print '[genmap error] in Irq.cbin() : irq global index = %d / expected = %d' \
2367	% (self.index, expected )
2368	sys.exit(1)
2369
2370	# compute numerical value for irqtype
2371	irqtype_id = 0xFFFFFFFF
2372	for x in xrange( len(IRQTYPES) ):
2373	if ( self.irqtype == IRQTYPES[x] ):
2374	irqtype_id = x
2375	if ( irqtype_id == 0xFFFFFFFF ):
2376	print '[genmap error] in Irq.cbin() : undefined irqtype %s' % self.irqtype
2377	sys.exit(1)
2378
2379	# compute numerical value for isrtype
2380	isrtype_id = 0xFFFFFFFF
2381	for x in xrange( len(ISRTYPES) ):
2382	if ( self.isrtype == ISRTYPES[x] ):
2383	isrtype_id = x
2384	if ( isrtype_id == 0xFFFFFFFF ):
2385	print '[genmap error] in Irq.cbin() : undefined isrtype %s' % self.isrtype
2386	sys.exit(1)
2387
2388	byte_stream = bytearray()
2389	byte_stream += mapping.int2bytes( 4, irqtype_id )
2390	byte_stream += mapping.int2bytes( 4, self.srcid )
2391	byte_stream += mapping.int2bytes( 4, isrtype_id )
2392	byte_stream += mapping.int2bytes( 4, self.channel )
2393	byte_stream += mapping.int2bytes( 4, 0 )
2394	byte_stream += mapping.int2bytes( 4, 0 )
2395
2396	if ( verbose ):
2397	print 'irqtype = %s' % self.irqtype
2398	print 'srcid = %d' % self.srcid
2399	print 'isrtype = %s' % self.isrtype
2400	print 'channel = %d' % self.channel
2401
2402	return byte_stream
2403
2404	###########################################################################################
2405	class Coproc ( object ):
2406	###########################################################################################
2407	def __init__( self,
2408	pseg ): # associated pseg
2409
2410	self.index = 0 # global index value set by addCoproc()
2411	self.pseg = pseg
2412	self.ports = []
2413
2414	return
2415
2416	################
2417	def xml( self ): # xml for Coproc
2418
2419	print '[genmap error] in Coproc.xml() : not defined yet'
2420	sys.exit(1)
2421
2422	return
2423
2424	#############################################
2425	def cbin( self, mapping, verbose, expected ): # C binary structure for Coproc
2426
2427	if ( verbose ):
2428	print '*** cbin for coproc in cluster (%d,%d)' % (self.pseg.x, self.pseg.y)
2429
2430	# check index
2431	if (self.index != expected):
2432	print '[genmap error] in Coproc.cbin() : coproc global index = %d / expected = %d' \
2433	% (self.index, expected )
2434	sys.exit(1)
2435
2436	# compute pseg global index
2437	pseg_id = self.pseg.index
2438
2439	# compute first port global index
2440	port_id = self.ports[0].index
2441
2442	byte_stream = bytearray()
2443	byte_stream += mapping.str2bytes( 32, self.pseg.name ) # probablement inutile (AG)
2444	byte_stream += mapping.int2bytes( 4 , pseg_id ) # pseg global index
2445	byte_stream += mapping.int2bytes( 4 , len( self.ports ) ) # number of input irqs
2446	byte_stream += mapping.int2bytes( 4 , port_id ) # first port global index
2447
2448	if ( verbose ):
2449	print 'irqtype = %s' % self.irqtype
2450	print 'pseg_id = %d' % pseg_id
2451	print 'nb_ports = %d' % len( self.ports )
2452	print 'port_id %d' % port_id
2453
2454	return byte_stream
2455
2456	###########################################################################################
2457	class Cpport ( object ):
2458	###########################################################################################
2459	def __init__( self,
2460	direction,
2461	vspacename,
2462	mwmrname ):
2463
2464	self.index = 0 # global index ( set by addCpport() )
2465	self.direction = direction # TO_COPROC / FROM_COPROC
2466	self.vspacename = vspacename # name of vspace containing mwmr channel
2467	self.mwmrname = mwmrname # name of vobj defining mwmr channel
2468
2469	return
2470
2471	################
2472	def xml( self ): # xml for Cpport
2473
2474	print '[genmap error] in Cpport.xml() : not defined yet'
2475	sys.exit(1)
2476
2477	return
2478
2479	#############################################
2480	def cbin( self, mapping, verbose, expected ): # C binary structure for Cpport
2481
2482	if ( verbose ):
2483	print '*** cbin for cpport[%d]' % (self.index)
2484
2485	# check index
2486	if ( self.index != expected ):
2487	print '[genmap error] in Cpport.cbin() : port global index = %d / expected = %d' \
2488	% ( self.index, expected )
2489	sys.exit(1)
2490
2491	# compute numerical value for direction
2492	if ( self.direction == 'TO_COPROC' ):
2493	dir_int = 0
2494	else:
2495	dir_int = 1
2496
2497	# compute vspace global index
2498	vspace_id = 0xFFFFFFFF
2499	for vspace in mapping.vspaces:
2500	if ( self.vspacename == vspace.name ):
2501	vspace_id = vspace.index
2502	if (vspace_id == 0xFFFFFFFF):
2503	print '[genmap error] in Cpport.cbin() : vspace name %s not found' \
2504	% ( self.vspacename )
2505	sys.exit(1)
2506
2507	# compute mwmr global index
2508	mwmr_id = 0xFFFFFFFF
2509	for vseg in mapping.vspace[vspace_id].vsegs:
2510	for vobj in vseg.vobjs:
2511	if (self.mwmrname == vobj.name):
2512	mwmr_id = vobj.index
2513	if (mwmr_id == 0xFFFFFFFF):
2514	print '[genmap error] in Cpport.cbin() : mwmr vobj name %s not found in vspace %s' \
2515	% ( self.mwmrname, self.vspacename )
2516	sys.exit(1)
2517
2518	byte_stream = bytearray()
2519	byte_stream += mapping.int2bytes( 4 , dir_int ) # pseg global index
2520	byte_stream += mapping.int2bytes( 4 , vspace_id ) # vspace global index
2521	byte_stream += mapping.int2bytes( 4 , mwmr_id ) # mwmr vobj global index
2522
2523	if ( verbose ):
2524	print 'direction = %s' % self.direction
2525	print 'vspace_id = %d' % vspace_id
2526	print 'mwmr_id = %d' % mwmr_id
2527
2528	return byte_stream
2529
2530
2531	# Local Variables:
2532	# tab-width: 4;
2533	# c-basic-offset: 4;
2534	# c-file-offsets:((innamespace . 0)(inline-open . 0));
2535	# indent-tabs-mode: nil;
2536	# End:
2537	#
2538	# vim: filetype=python:expandtab:shiftwidth=4:tabstop=4:softtabstop=4
2539

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