Changes between Version 17 and Version 18 of kernel_interrupts

Timestamp:

Mar 22, 2015, 6:15:06 PM (9 years ago)

Author:

alain

Comment:

--

kernel_interrupts

@@ -19 +19 @@
  1. The GIET-VM uses only one XCU output IRQ per processor  (with index = lpid * IRQ_PER_PROCESSOR), even if the hardware platform contains more than one IRQ_PER_PROCESSOR.
 
- 2. In each cluster the local '''HWI'''  generated by the local peripherals are ''statically'' allocated to local processors.
+ 2. In each cluster the local '''HWI'''  generated by the local peripherals are ''statically'' allocated and distributed to local processors, to share the load between all processors).
 
- 3. In each cluster, one '''PTI''' is statically allocated to each processor for context switch (pti_id = lpid). The TICK period is defined by the GIET_TICK_VALUE parameter in the giet_config.h file. The associated _isr_tick() interrupt service routine forces a context switch on the target processor.
+ 3. In each cluster, one '''PTI''' is statically allocated to each processor for context switch (pti_id = lpid). The TICK period is defined by the GIET_TICK_VALUE parameter in the giet_config.h file. The associated '''_isr_tick()''' interrupt service routine forces a context switch on the target processor.
 
  4. In each cluster, 4 '''WTI''' mailbox (called WAKE_UP, EXT_IRQ_ONE, EXT_IRQ_TWO, EXT_IRQ_TER) are statically allocated to each processor. The first one is used by the GIET_VM boot-loader for processor wakup, and is used by the kernel for inter-processor interrupts.  
 
- 5. The isr_wakup() interrupt service routine is associated to the WAKE_UP interrupt. When the destination processor is not in wait state (low-power mode), the ISR is executed. If the processor executing the idle_task, or if the value written in the WTI mailbox is non zero, this ISR force a context switch on the target processor.
+ 5. The '''isr_wakup()''' interrupt service routine is associated to the WAKE_UP interrupt. When the destination processor is not in wait state (low-power mode), the ISR is executed. If the processor executing the idle_task, or if the value written in the WTI mailbox is non zero, this ISR force a context switch on the target processor.
 
  6. The three EXT_IRQ_ONE, EXT_IRQ_TWO and EXT_IRQ_TER interrupts are dynamically allocated to external IRQS generated by the external peripherals (through the IOPIC component), in order to route the external IRQ to the processor that launched the I/O operation.