Changes between Version 7 and Version 8 of kernel_interrupts

Timestamp:

Mar 12, 2015, 5:45:49 PM (9 years ago)

Author:

alain

Comment:

--

kernel_interrupts

@@ -6 +6 @@
 [[PageOutline]]
 
-The GIET_VM interrupt handler supports only the SOCLIB ''vci_xcu'' interrupt controler, and does not support the ''vci_icu'' interrupt controler. In a multi-cluster architectures, it must exist one XCU controller in all clusters containing processors. 
+The GIET_VM interrupt handler supports only the SOCLIB XCU interrupt controler. In a multi-cluster architectures, it must exist one XCU controller in all clusters containing processors. 
 
-Each multi-channel XCU component in a given cluster must contain as many channels as the number of processors in the cluster (one output IRQ per processor).
+Each multi-channel XCU component in a given cluster must contain (NB_PROCS_MAX * IRQ_PER_PROCESSOR) channels  (one channel = one output IRQ).
 
-There is three interrupt vectors per processor (stored in each processor's scheduler) for the three HWI, PTI, and WTI interrupts types. Each interrupt vector entry contains three bits fields:
+There is three interrupt vectors per processor (stored in each processor's scheduler) for the three HWI (Hardware Interrupt), PTI (Programmable Timer Interrupt), and WTI (Write Triggered Interrupt) interrupts types. Each interrupt vector entry contains two fields:
 ||isr_id         ||bits[15:0]    || defines the type of ISR to be executed ||
-||channel_id ||bits[30:16]  || defines the channel for multi-channels peripherals ||
-||valid          || bit [31]       || valid interrupt vector entry ||
+||channel_id ||bits[31:16]  || defines the channel for multi-channels ISR ||
 
-If the peripheral is replicated in clusters, the channel_id is a global index : 
-channel_id = cluster_xy * NB_CHANNELS_MAX + loc_id   
+Regarding the allocation of interrupts to processors (IRQ routing using the XCU_MASK registers), the GIET-VM implement the following policy:
+ * The GIET-VM uses only one XCU output IRQ per processor  (index = lpid * IRQ_PER_PROCESSOR), even if the hardware platform contains more than one IRQ_PER_PROCESSOR.
+ * In each cluster the HWI (hardwareinterrupts generated by the local peripherals) are ''statically'' allocated to local processors.
+ * In each cluster, one PTI (timer interrupt) is statically allocated to each processor for TICK context switch.
+ * In each cluster, 4 WTI (mailbox interrupts) are allocated to each processor. For each processor, the first WTI mailbox is statically allocated to WAKUP (inter processor interrupt). The three other WTI mailbox are dynamically allocated to external IRQS generated by the external peripherals through the IOPIC component.
+All XCU masks for all processors are statically defined in the boot phase. 
 
+ == __Functions used for all HWI / PTI / WTI interrupts__ ==
 
  === void '''_irq_demux'''() ===
@@ -46 +50 @@
  === void '''_isr_default'''() ===
 This default ISR is called  when the interrupt handler is called, and there is no active IRQ. It simply displays a warning message on the kernel TTY[0].
+
+ == __Functions used for dynamic allocation of external IRQs__ ==
+
+ === void '''_ext_irq_init'''() ===
+This function is only used when the architecture contains an external IOPIC component. It initializes the _ext_irq_index[isr][channel] array,
+defining the IRQ index associated to (isr_type/isr_channel) couple, as specified in the mapping.
+This array is used by the kernel for dynamic routing of an external IRQ signaling completion to  the processor that launched the I/O operation.
+
+ === void '''_ext_irq_alloc( unsigned int isr_type , unsigned int isr_channel , unsigned int* wti_index ) ===
+This function is used when the architecture contains an external IOPIC component. It dynamically routes an external IRQ signaling completion of an I/O operation to the processor P[x,y,p] running the calling task. The two (isr_type, isr_channel) arguments define actually the external IRQ to be routed.
+ * '''isr_type''' : type of ISR to be executed
+ * '''isr_channel''' : ISR channel (for multi-channels peripherals)
+ * '''wti_index''' : return value defining the index of the WTI mailbox allocated to P[x,y,p]
+This function does three things: 
+ 1. it allocates a WTI mailbox in the XCU of cluster[x,y] to the requesting processor ( index is in [4*p+1, 4*p+2, 4*p+3] ) ; 
+ 2. it initialises the IOPIC entry associated to the (isr_type/isr_channel) IRQ.
+ 3. it initializes the proper entry in the WTI interrupt vector associated to processor P[x,y,p].
+
+ === void '''_ext_irq_release( unsigned int isr_type , unsigned int isr_channel , unsigned int* wti_index ) ===
+This function is used when the architecture contains an external IOPIC component. It desallocates the ressources allocated by the  previous _ext_irq_alloc() function to the calling processor. The two (isr_type, isr_channel) arguments define actually the external IRQ to be released.
+ * '''isr_type''' : type of ISR to be executed
+ * '''isr_channel''' : ISR channel (for multi-channels peripherals)
+ * '''wti_index''' :  index of the WTI mailbox allocated to P[x,y,p]
+This function does only two things: 
+ 1.  it desactivates the PIC entry associated to the (isr_type/isr_channel) IRQ.
+ 2. it releases the WTI mailbox allocated to P[x,y,p].
+ 3. The WTI interrupt vector is NOT modified
+