47 | | The GIET_VM allows user applications to use hardware coprocessors. These coprocessors can be distributed in the architecture, |
48 | | but there is at most one coprocessor per cluster. To be supported by the GIET_VM, a coprocessor must use the ''vci_mwmr_dma'' component, that is a multi-channels DMA controller. |
49 | | |
50 | | On the coprocessor side, it provides TO_COPROC and FROM_COPROC ports, that implement FIFO interfaces. Coprocessor can request to read (or write) one or several bursts of 32 bits words on a TO_COPROC port (FROM_COPROC for a write), without address. The burst size (generally a cache line) is a global hardware parameter. The number of TO_COPROC and FROM_COPROC ports, and the number of bursts for a given port depends on each coprocessor implementation. Each port define a private communication channel |
51 | | to a memory buffer. The total number of channels cannot be larger than 16. A channel is identified by an index, and the TO_COPROC channels have the smallest indexes. |
| 47 | The GIET_VM allows user applications to use hardware accelerators, called coprocessors. These coprocessors can be distributed in the architecture, but there is at most one coprocessor per cluster. To be supported by the GIET_VM, a coprocessor must use the ''vci_mwmr_dma'' component, that is a multi-channels DMA controller. |
| 48 | |
| 49 | On the coprocessor side, it provides TO_COPROC and FROM_COPROC ports, that implement FIFO interfaces. Coprocessor can request to read (or write) one or several bursts of 32 bits words on a TO_COPROC port (FROM_COPROC port for a write), without address. The burst size (generally a cache line) is a global hardware parameter. The number of TO_COPROC and FROM_COPROC ports, and the number of bursts for a given port depends on each coprocessor implementation. Each port define a private communication channel |
| 50 | between the coprocessor and an user memory buffer. The total number of channels cannot be larger than 16. A channel is identified by an index, and the TO_COPROC channels have the smallest indexes. |
60 | | Several channels can simultaneously run in different modes, and the various VCI transactions corresponding to different channels are interleaved and parallelized on the VCI network. The maximum number of simultaneous VCI transactions is equal to the number of channels. |
61 | | |
62 | | Besides these communication channels |
63 | | |
64 | | The list of supported coprocessors and their characteristics is defined below: |
| 59 | Several channels can simultaneously run in different modes, and the various VCI transactions corresponding to different channels are interleaved and parallelized on the VCI network. |
| 60 | |
| 61 | Besides these communication channels, the ''vci_mwmr_dma component support up to 16 coprocessor-specific configurarion/status registers. The ''configuration'' registers are Read/Write. The ''status'' registers are Read-Only. |
| 62 | |
| 63 | |
| 64 | The list of supported coprocessors and their characteristics are defined below: |