Changes between Version 50 and Version 51 of library_stdio


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Timestamp:
Mar 1, 2015, 10:38:18 PM (9 years ago)
Author:
alain
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  • library_stdio

    v50 v51  
    4545 ==  Coprocessors related system calls ==
    4646
    47 The GIET_VM allows user applications to use hardware coprocessors. These coprocessors can be distributed in the architecture,
    48 but there is at most one coprocessor per cluster. To be supported by the GIET_VM, a coprocessor must use the ''vci_mwmr_dma'' component, that is a multi-channels DMA controller.
    49 
    50 On the coprocessor side, it provides TO_COPROC and FROM_COPROC ports, that implement FIFO interfaces. Coprocessor can request to read (or write) one or several bursts of 32 bits words on a TO_COPROC port (FROM_COPROC for a write), without address. The burst size (generally a cache line) is a global hardware parameter. The number of TO_COPROC and FROM_COPROC ports, and the number of bursts for a given port depends on each coprocessor implementation. Each port define a private communication channel
    51 to a memory buffer. The total number of channels cannot be larger than 16. A channel is identified by an index, and the TO_COPROC channels have the smallest indexes.
     47The GIET_VM allows user applications to use hardware accelerators, called coprocessors. These coprocessors can be distributed in the architecture, but there is at most one coprocessor per cluster. To be supported by the GIET_VM, a coprocessor must use the ''vci_mwmr_dma'' component, that is a multi-channels DMA controller.
     48
     49On the coprocessor side, it provides TO_COPROC and FROM_COPROC ports, that implement FIFO interfaces. Coprocessor can request to read (or write) one or several bursts of 32 bits words on a TO_COPROC port (FROM_COPROC port for a write), without address. The burst size (generally a cache line) is a global hardware parameter. The number of TO_COPROC and FROM_COPROC ports, and the number of bursts for a given port depends on each coprocessor implementation. Each port define a private communication channel
     50between the coprocessor and an user memory buffer. The total number of channels cannot be larger than 16. A channel is identified by an index, and the TO_COPROC channels have the smallest indexes.
    5251
    5352Each channel implements three transfer modes that can be defined by software:
    5453 * In '''MODE_MWMR''', the channel transfer an "infinite" data stream, between the coprocessor port and a MWMR software FIFO in memory. The MWMR_DMA controller  implements the 7 steps MWMR protocol.
    5554 * In '''MODE_DMA_IRQ''', the channel transfer a single buffer between the memory and the coprocessor port. The number of VCI burst for a given channel depends on the memory buffer size, and the MWMR_DMA controller signals the transfer completion with an interrupt.
    56  * The '''MODE_DMA_NO_IRQ''', is similar to the previous one, but the the channel stops when the transfer is completed, without rising an interrupt.
     55 * The '''MODE_DMA_NO_IRQ''', is similar to the previous one, but the channel stops when the transfer is completed, without rising an interrupt.
    5756
    5857'''WARNING''' : For all channels, the memory buffer address and size  must be multiple of the burst size.
    5958
    60 Several channels can simultaneously run in different modes, and the various VCI transactions corresponding to different channels are interleaved and parallelized on the VCI network. The maximum number of simultaneous VCI transactions is equal to the number of channels.
    61 
    62 Besides these communication channels
    63 
    64 The list of supported coprocessors and their characteristics is defined below:
     59Several channels can simultaneously run in different modes, and the various VCI transactions corresponding to different channels are interleaved and parallelized on the VCI network.
     60
     61Besides these communication channels, the ''vci_mwmr_dma component support up to 16 coprocessor-specific configurarion/status registers. The ''configuration'' registers are Read/Write. The ''status'' registers are Read-Only.
     62
     63
     64The list of supported coprocessors and their characteristics are defined below:
    6565||  coproc_type            || nb_to_coproc || nb_from_coproc || nb_config  || nb_status || 
    6666|| COPROC_TYPE_GCD ||     2                ||         1               ||       1         ||       0        ||