Changes between Version 53 and Version 54 of library_stdio

Timestamp:

Mar 2, 2015, 1:30:09 PM (9 years ago)

Author:

alain

Comment:

--

library_stdio

@@ -28 +28 @@
 No error possible, as the return value is always between 0 & 65535.
 
- == __Task related system calls__ ==
+ == __User task related system calls__ ==
 
  === 1) unsigned int '''giet_proc_task_id'''() ===
@@ -45 +45 @@
  ==  __Coprocessors related system calls__ ==
 
-The GIET_VM allows user applications to use hardware accelerators, called coprocessors. These coprocessors can be distributed in the architecture, but there is at most one coprocessor per cluster, and a coprocessor is identified by the (x,y) coordinares. To be supported by the GIET_VM, a coprocessor must use the ''vci_mwmr_dma'' component, that is a multi-channels DMA controller.
-
-On the coprocessor side, it provides ''TO_COPROC'' or ''FROM_COPROC'' ports, that implement FIFO interfaces. Coprocessor can request to read (or write) one or several bursts of 32 bits words on a TO_COPROC port (FROM_COPROC port for a write), without address. The burst size (generally a cache line) is a global hardware parameter. The number of TO_COPROC and FROM_COPROC ports, and the number of bursts for a given port depends on each coprocessor implementation. Each port define a private communication channel between the coprocessor and a user memory buffer. The total number of channels cannot be larger than 16. A channel is identified by an index, and the TO_COPROC channels have the smallest indexes.
-
-Each channel implements three transfer modes that can be defined by software:
+The GIET_VM allows user applications to use hardware accelerators (called coprocessors). These coprocessors can be distributed in the architecture, but there is at most one coprocessor per cluster, identified by the cluster (x,y) coordinares. To be supported by the GIET_VM, a coprocessor must use the ''vci_mwmr_dma'' component, that is a multi-channels DMA controller.
+
+On the coprocessor side, it provides TO_COPROC or FROM_COPROC ports, that implement FIFO interfaces. Coprocessor can request to transfer one or several bursts of 32 bits words on a TO_COPROC or FROM_COPROC port, without address. The burst size (generally a cache line), the number of TO_COPROC and FROM_COPROC ports, and the number of bursts for a given port are hardware parameters. Each port define a private communication channel between the coprocessor and a user memory buffer. The total number of channels cannot be larger than 16. A channel is identified by an index, and the TO_COPROC channels have the smallest indexes.
+
+Each communication channel implements three transfer modes that can be configured by software:
  * In '''MODE_MWMR''', the channel transfer an "infinite" data stream, between the coprocessor port and a MWMR software FIFO in memory. The MWMR_DMA controller  implements the 7 steps MWMR protocol.
- * In '''MODE_DMA_IRQ''', the channel transfer a single buffer between the memory and the coprocessor port. The number of VCI burst for a given channel depends on the memory buffer size, and the MWMR_DMA controller signals the transfer completion with an interrupt. 
+ * In '''MODE_DMA_IRQ''', the channel transfer a single buffer between the coprocessor port and the memory. The number of VCI burst for a given channel depends on the memory buffer size, and the MWMR_DMA controller signals the transfer completion with an interrupt. 
  * The '''MODE_DMA_NO_IRQ''', is similar to the previous one, but the channel stops when the transfer is completed, without rising an interrupt.
 
-'''WARNING''' : For all channels, the memory buffer address and size  must be multiple of the burst size.
-
-Several channels can simultaneously run in different modes, and the various VCI transactions corresponding to different channels are interleaved and parallelized on the VCI network. 
+'''WARNING''' : For all channels, the memory buffer address and size  must be multiple of the hardware burst size.
+
+Several channels can simultaneously run in different modes. The VCI transactions corresponding to different channels are interleaved and parallelized on the VCI network. 
 
 Besides these communication channels, the ''vci_mwmr_dma component support up to 16 coprocessor-specific configurarion/status registers. The ''configuration'' registers are Read/Write. The ''status'' registers are Read-Only.
@@ -233 +233 @@
 This function display on kernel TTY0 the content of the instrumentation registers associated to the RX channels.
 
- === 11) void '''giet_nic_tx_stats( unsigned int channel ) ===
+ === 12) void '''giet_nic_tx_stats( unsigned int channel ) ===
 This function display on kernel TTY0 the content of the instrumentation registers associated to the TX channels.