Changes between Version 2 and Version 3 of mmc_driver

Timestamp:

Jan 20, 2015, 7:05:11 PM (9 years ago)

Author:

alain

Comment:

--

mmc_driver

@@ -7 +7 @@
 
 The ''vci_mem_cache'' component is a L2 cache controller specifically designed for the TSAR architecture.
-It contains several addressable registers that can be used to support software based cache coherence between L2 and L3 caches. 
+It contains 3 types of addressable registers:
+ * '''configuration registers''' support software based cache coherence between L2 and L3 caches. 
+ * '''instrumentation registers''' define various hardware event counters
+ * '''error report registers''' contains various informations on address errors reported by the L2 cache.
 
 The MMC component is a replicated peripheral, as it exist one MMC component per cluster.
@@ -18 +21 @@
 The addressable registers map and command codes are defined [source:soft/giet_vm/giet_drivers/mmc_driver.h here].
 
+ == Configuration registers access functions ==
 
  === void '''_mmc_inval'''( unsigned long long buf_paddr,   unsigned int buf_length ) ===
@@ -25 +29 @@
 This function copies to external RAM all cache lines covering a memory buffer defined by the physical base address, and the length, if they are dirty. The buffer address MSB are used to compute the cluster index.
 
+ ==Instrumentation registers access functions ==
+
+ === unsigned int '''_mmc_get_instrument'''( unsigned int x,  unsigned int y,  unsigned int reg ) ===
+This function returns the value contained in a specific register of a specific L2 cache.
+ * '''x''' cluster X coordinate
+ * '''y''' cluster Y coordinate
+ * '''reg''' register index
+
+ == Error registers access functions ==
+
  === void '''_mmc_isr'''( unsigned int irq_type,   unsigned int irq_id,   unsigned int channel ) ===
 This Interrupt Service Routine access the vci_mem_cache component to get 
  the faulty physical address and the associated SRCID. It acknowledges the IRQ.
- Not implemented yet...
+ Not fully implemented yet...
+