Changes between Version 18 and Version 19 of user_applications

Timestamp:

Dec 9, 2015, 4:12:09 PM (8 years ago)

Author:

alain

Comment:

--

user_applications

@@ -142 +142 @@
 
 This multi-threaded application makes the decompression of a MJPEG bit-stream contained in a file, an display the stream of images on the Frame Buffer.
-It illustrates the "multi pipe-line" parallelism. It uses the message passing programming model, on top of the POSIX threads API, and the MWMR communication middleware.
+It illustrates the "multi pipe-line" parallelism: each image is decompressed by a five stages pipe-line implemented as five POSIX threads. Several images can be decomposed in parallel, as each cluster implement a complete pipe-line. It uses the message passing programming model, on top of the POSIX threads API, and the MWMR communication middleware.
 The application is described as a TCG (Task and Communication Graph), and all communications between threads uses MWMR channels.
-Each pipeline decompress one complete image, and there is one pipe-line per cluster.
-It uses the chained buffer DMA component to display the stream of decompressed images.ç!!l:=m
+It uses the chained buffer DMA component to display the stream of decompressed images.
 It contains 6 types of threads (plus the "main" thread, that makes initialisation), and 7 types of MWMR communication channels:
  * the TG thread dispatch the bit-stream to the pipeline. It is only mapped in cluster[0,0].
  * the 5 threads implementing the pipeline (DEMUX, VLD, IQZZ, IDCT, LIBU) are replicated in all clusters.
  * the 7 MWMR channels are replicated in all clusters.
-The image throughput is actually bounded by the TG task that cannot be parallelized.
+The image throughput is actually bounded by the TG thread that cannot be parallelized.
+As the MWMR communication channels support communication between software threads and hardware accelerators, the IDCT software thread can be optionally replaced by an hardware DCT coprocessor, if this component is available in the target architecture. 
 
 The hardware constraints are the following