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source: trunk/IPs/systemC/Environment/src/Environment_transition.cpp @ 101

Last change on this file since 101 was 101, checked in by rosiere, 15 years ago
1) Add soc test 2) fix bug (Pc management, Decod and execute, Update prediction ...)
Property svn:keywords set to `Id`
File size: 30.1 KB

Line
1	#include "../include/Environment.h"
2
3	#define CYCLE_MAX 0
4	#include "../../processor/Morpheo/Common/include/Test.h"
5
6	using namespace morpheo;
7
8	namespace environment {
9
10	void Environment::transition (void)
11	{
12	if (NRESET->read() == 0)
13	{
14	reset ();
15	}
16	else
17	{
18	//=============================================================================
19	//===== [ ICACHE - RESPONS ]===================================================
20	//=============================================================================
21	for (uint32_t i = 0; i < param->nb_entity; i++)
22	for (int32_t j=param->icache_dedicated_nb_port [i]-1; j>=0; j--)
23	if (icache_rsp_val [i][j] and ICACHE_RSP_ACK [i][j]->read())
24	{
25	delete component_buffer_irsp [i]->read(j)._data;
26	component_buffer_irsp [i]->pop(j);
27	}
28	//=============================================================================
29	//===== [ DCACHE - RESPONS ]===================================================
30	//=============================================================================
31	for (uint32_t i = 0; i < param->nb_entity; i++)
32	for (int32_t j=param->dcache_dedicated_nb_port [i]-1; j>=0; j--)
33	if (dcache_rsp_val [i][j] and DCACHE_RSP_ACK [i][j]->read())
34	{
35	delete component_buffer_drsp [i]->read(j)._data;
36	component_buffer_drsp [i]->pop(j);
37	}
38
39	//=============================================================================
40	//===== [ ICACHE - RESPONS ]===================================================
41	//=============================================================================
42	for (uint32_t i=0; i<param->nb_entity; i++)
43	for (uint32_t j=0; j <param->icache_dedicated_nb_port [i]; j++)
44	if (ICACHE_REQ_VAL [i][j]->read() and icache_req_ack [i][j])
45	{
46	_cout(ENVIRONMENT, "ICACHE_REQ [%d] : Transaction accepted\n",i);
47
48	Ticache_context_t context = ICACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
49	Ticache_packet_t packet = ICACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
50	Ticache_address_t address = ICACHE_REQ_ADDRESS [i][j]->read()<<2;
51	Ticache_type_t type = ICACHE_REQ_TYPE [i][j]->read();
52	uint32_t size = (param->iaccess_size_address [i]+2)/8;
53
54	_cout(ENVIRONMENT," * information\n");
55	_cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
56	_cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
57	_cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
58	_cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
59	_cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
60
61	// search the entity
62	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),size);
63
64	bool uncached ;
65	bool bus_error;
66	bool must_read = (type == ICACHE_TYPE_LOAD);
67	bool must_ack = (type == ICACHE_TYPE_LOAD);
68	bool must_ack_on_error = (type == ICACHE_TYPE_LOAD);
69
70	// Test the type of the address : if != MEMORY -> error
71	if ((entity.present == true) and
72	(entity.segment->getType() == data::TYPE_TARGET_MEMORY))
73	{
74	_cout(ENVIRONMENT," * OK !\n");
75	bus_error = false;
76	uncached = entity.segment->getUncached();
77
78	if (must_read == true) // Test if must read the ram
79	{
80	_cout(ENVIRONMENT," * must read\n");
81	// Read all instruction
82	for (unsigned int k=0; k<param->iaccess_nb_instruction[i]; k++)
83	{
84	uint32_t addr = address+k*(size);
85	_cout(ENVIRONMENT," * addr : %.8x\n",addr);
86
87	bus_error \|= !component_data->read(addr,size,read_iram[k]);
88
89	// Swap if endienness is different
90	if (endianness::isSameEndianness(context) == false)
91	{
92	read_iram[k] = endianness::swapBytes(read_iram[k],size,size);
93	}
94
95	_cout(ENVIRONMENT," * inst :");
96	for (int32_t cpt=(param->iaccess_size_instruction[context]/8)-1; cpt>=0; --cpt)
97	_cout(ENVIRONMENT, "%.2x",0xff&static_cast<uint32_t>(read_iram[k][cpt]));
98	_cout(ENVIRONMENT, "\n");
99	}
100	}
101	}
102	else
103	{
104	_cout(ENVIRONMENT, " * KO !\n");
105	_cout(ENVIRONMENT, " * present : %d\n",entity.present);
106	if (entity.present)
107	_cout(ENVIRONMENT, " * type : %d must be data::TYPE_TARGET_MEMORY (%d)\n",entity.segment->getType(), data::TYPE_TARGET_MEMORY);
108
109	// entity is not present, or is present but is not a memory : have a bus error
110	bus_error = true;
111	uncached = true;
112	}
113
114	Cache_Access cache_type = ireq_type2cache_type (type,uncached);
115	uint32_t latence = component_cache->latence(cache::INSTRUCTION_CACHE,
116	i,
117	j,
118	address,
119	context,
120	cache_type.type,
121	cache_type.direction);
122
123	_cout(ENVIRONMENT, " * latence : %d\n",latence);
124
125	// If is a respons -> compute the latence and push in the write_buffer
126	if (must_ack or (must_ack_on_error and bus_error))
127	{
128	_cout(ENVIRONMENT, " * must ack\n");
129
130	if (bus_error == true)
131	{
132	std::cout << "Icache : have a bus error" << std::endl
133	<< " * entity : " << i << std::endl
134	<< " * port : " << j << std::endl
135	<< std::hex
136	<< " * req_addr : " << address << std::endl
137	<< std::dec
138	<< " * req_trdid : " << context << std::endl
139	<< " * req_pktid : " << packet << std::endl;
140
141	// Write in instruction [0] the bad address (only 32bit ....)
142	itoa<Ticache_address_t>(address,read_iram[0],param->iaccess_size_instruction[i]/8);
143	}
144
145	// Simplification : the size of a line is a multiple of size_iword (no test)
146	_cout(ENVIRONMENT, " * push in buffer_irsp[%d]\n",i);
147
148	irsp_t * rsp = new irsp_t(context,
149	packet,
150	param->iaccess_nb_instruction[i],
151	size,
152	read_iram,
153	(bus_error==true)?ICACHE_ERROR_BUS_ERROR:ICACHE_ERROR_NONE);
154	component_buffer_irsp [i]->push(latence,rsp);
155	}
156
157	_cout(ENVIRONMENT, " * End request\n");
158	}
159
160	//=============================================================================
161	//===== [ DCACHE - REQUEST ]===================================================
162	//=============================================================================
163	for (uint32_t i=0; i<param->nb_entity; i++)
164	for (uint32_t j=0; j <param->dcache_dedicated_nb_port [i]; j++)
165	if (DCACHE_REQ_VAL [i][j]->read() and dcache_req_ack [i][j])
166	{
167	_cout(ENVIRONMENT, "DCACHE_REQ [%d] : Transaction accepted\n",i);
168
169	Tdcache_context_t context = DCACHE_REQ_CONTEXT_ID [i][j]->read();// TODO : test presence
170	Tdcache_packet_t packet = DCACHE_REQ_PACKET_ID [i][j]->read();// TODO : test presence
171	Tdcache_address_t address = DCACHE_REQ_ADDRESS [i][j]->read();
172	Tdcache_data_t wdata = DCACHE_REQ_WDATA [i][j]->read();
173	Tdcache_type_t type = DCACHE_REQ_TYPE [i][j]->read();
174	uint32_t size = param->daccess_size_data [i]/8;
175
176	_cout(ENVIRONMENT," * information\n");
177	_cout(ENVIRONMENT," * context : %d\n" ,static_cast<uint32_t>(context));
178	_cout(ENVIRONMENT," * packet : %d\n" ,static_cast<uint32_t>(packet ));
179	_cout(ENVIRONMENT," * address : %.x\n",static_cast<uint32_t>(address));
180	_cout(ENVIRONMENT," * type : %d\n" ,static_cast<uint32_t>(type ));
181	_cout(ENVIRONMENT," * size : %d\n" ,static_cast<uint32_t>(size ));
182
183	bool uncached = false;
184	bool bus_error = false;
185
186	uint32_t nb_bytes = size;
187	bool must_read ;
188	bool must_write;
189	bool must_ack ;
190	bool must_ack_on_error;
191
192	switch (type)
193	{
194	case DCACHE_TYPE_LOAD_8 :{nb_bytes=1; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
195	case DCACHE_TYPE_LOAD_16 :{nb_bytes=2; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
196	case DCACHE_TYPE_LOAD_32 :{nb_bytes=4; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
197	case DCACHE_TYPE_LOAD_64 :{nb_bytes=8; must_read=true ; must_write=false; must_ack=true ; must_ack_on_error=true ; break;}
198	case DCACHE_TYPE_LOCK :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
199	case DCACHE_TYPE_INVALIDATE :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
200	case DCACHE_TYPE_PREFETCH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
201	case DCACHE_TYPE_FLUSH :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
202	case DCACHE_TYPE_SYNCHRONIZATION :{ must_read=false; must_write=false; must_ack=true ; must_ack_on_error=false; break;}
203	case DCACHE_TYPE_STORE_8 :{nb_bytes=1; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
204	case DCACHE_TYPE_STORE_16 :{nb_bytes=2; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
205	case DCACHE_TYPE_STORE_32 :{nb_bytes=4; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
206	case DCACHE_TYPE_STORE_64 :{nb_bytes=8; must_read=false; must_write=true ; must_ack=false; must_ack_on_error=true ; break;}
207	default :{ must_read=false; must_write=false; must_ack=false; must_ack_on_error=false; break;}
208	}
209
210	// search the entity
211	data::Entity entity = component_data->entity(static_cast<uint32_t>(address),nb_bytes);
212
213	std::cout << entity << std::endl;
214
215	// Test the type of the address
216	if (entity.present == true)
217	{
218	switch (entity.segment->getType())
219	{
220	//**************************************************************
221	//***[ TTY ]************************************************
222	//**************************************************************
223	case data::TYPE_TARGET_TTY :
224	{
225	// Can't read a tty, must write
226	if (must_write == false)
227	{
228	bus_error = true;
229	break;
230	}
231
232	uint32_t num_tty = (address - entity.segment->getBase())>>4;
233	uint32_t num_print = ((address>>2) & 0x3);
234	_cout(ENVIRONMENT," * TYPE_TARGET_TTY : num_tty : %d, num_print : %d\n",num_tty, num_print);
235
236	switch (num_print)
237	{
238	case 0 : // Write TTY
239	{
240	uint32_t num_component_tty = entity.segment->getIndex();
241	char char_write = static_cast<char>(wdata&0xff);
242	bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
243	break;
244	}
245	case 1 : // STOP
246	{
247	printf("\n\t*** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
248	,static_cast<uint32_t>(sc_simulation_time())
249	,static_cast<uint32_t>(address )
250	,static_cast<uint32_t>((wdata>>24)&0xff)
251	,static_cast<uint32_t>((wdata>>16)&0xff)
252	,static_cast<uint32_t>((wdata>> 8)&0xff)
253	,static_cast<uint32_t>((wdata>> 0)&0xff)
254	);
255
256	if (wdata == 0)
257	std::cout << STR_OK << std::endl;
258	else
259	std::cout << STR_KO << std::endl;
260
261	stop (context);
262
263	break;
264	}
265	case 2 : // PRINT
266	{
267	printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
268	,static_cast<uint32_t>(sc_simulation_time())
269	,static_cast<uint32_t>(address )
270	,static_cast<uint32_t>((wdata>>24)&0xff)
271	,static_cast<uint32_t>((wdata>>16)&0xff)
272	,static_cast<uint32_t>((wdata>> 8)&0xff)
273	,static_cast<uint32_t>((wdata>> 0)&0xff)
274	);
275
276	break;
277	}
278	default :
279	{
280	printf("[address : %.8x] tty %d, reg %d don't exist\n",static_cast<uint32_t>(address),num_tty,num_print);
281	bus_error = true;
282	}
283	}
284	break;
285	}
286
287	//**************************************************************
288	//***[ MEMORY ]*********************************************
289	//**************************************************************
290	case data::TYPE_TARGET_MEMORY :
291	{
292	_cout(ENVIRONMENT,"MEMORY\n");
293	_cout(ENVIRONMENT,"access : %x\n",address);
294
295	if (must_read == true)
296	{
297	// Read
298	_cout(ENVIRONMENT," * Read (%d bytes)\n",size);
299	bus_error \|= !component_data->read(address,nb_bytes,read_dram[0]); // always read a complete word
300
301	_cout(ENVIRONMENT," * Rdata : ");
302	for (uint32_t i=0; i<nb_bytes; i++)
303	_cout(ENVIRONMENT,"%.2x",0xff&static_cast<uint32_t>(read_dram[0][i]));
304	_cout(ENVIRONMENT,".\n");
305
306	// Multiple copy
307	for (unsigned int it_size_data = nb_bytes; it_size_data < size; it_size_data+=nb_bytes)
308	memcpy(&(read_dram[0][it_size_data]),&(read_dram[0][0]),nb_bytes);
309
310	// Permutation if problem of endianness
311	if (endianness::isSameEndianness(context) == false)
312	read_dram[0] = endianness::swapBytes(read_dram[0] , size, nb_bytes);
313	}
314
315	if (must_write == true)
316	{
317	// Write
318	_cout(ENVIRONMENT," * Write (%d bytes)\n",size);
319	_cout(ENVIRONMENT," * Wdata : %x\n",wdata);
320	itoa<Tdcache_data_t>(wdata,write_dram,nb_bytes);
321
322	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < size; it_nb_bytes ++)
323	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
324	}
325
326	break;
327	}
328	//**************************************************************
329	//***[ RAMLOCK ]********************************************
330	//**************************************************************
331	case data::TYPE_TARGET_RAMLOCK :
332	{
333	// Access is on a byte, else error
334	if (nb_bytes != 1)
335	{
336	bus_error = true;
337	break;
338	}
339
340	uint32_t num_ramlock = (address - entity.segment->getBase()); // Char access
341	uint32_t num_component_ramlock = entity.segment->getIndex();
342
343	// No test : because out of range
344
345	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
346
347	// if (bus_error == true)
348	// break;
349
350	memset (read_dram[0],0,size);
351
352	if (must_read == true)
353	read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->read (num_ramlock));
354	if (must_write == true)
355	read_dram [0][0] = static_cast<char>(component_ramlock [num_component_ramlock]->write(num_ramlock));
356
357	break;
358	}
359
360	//**************************************************************
361	//***[ SIM2OS ]*********************************************
362	//**************************************************************
363	case data::TYPE_TARGET_SIM2OS :
364	{
365	// Mapping :
366	// [0] number of service - Wonly - A write in this register lunch the execution of service
367	// [1] result - Ronly - Content the result of the service
368	// [2] error - Ronly - Content the code of errno
369	// [3+] argument - Wonly - it's all argument to execute the service
370
371	uint32_t num_reg = (address - entity.segment->getBase())>>2;
372
373	switch (num_reg)
374	{
375	case 0 : // ---> number of service
376	{
377	if (must_write == false)
378	{
379	std::cerr << "<Environment::transition> SIM2OS[0] is not accessible in Read" << std::endl;
380	bus_error = true;
381	}
382	else
383	{
384	_cout(ENVIRONMENT,"<sim2os> service : %x\n",wdata);
385	component_sim2os->execute(sim2os::int2service(static_cast<uint32_t>(wdata)));
386	}
387	break;
388	}
389	case 1 : // ---> result
390	{
391	if (must_read == false)
392	{
393	std::cerr << "<Environment::transition> SIM2OS[1] is not accessible in Write" << std::endl;
394	bus_error = true;
395	}
396	else
397	{
398	// Decomposition en groupe octect
399	Tdcache_data_t result = static_cast<Tdcache_data_t>(reinterpret_cast<uint64_t>(component_sim2os->result));
400	_cout(ENVIRONMENT,"<sim2os> result : %x\n",result);
401
402	itoa<Tdcache_data_t>(result,read_dram[0],size);
403	}
404	break;
405	}
406	case 2 : // ---> error
407	{
408	if (must_read == false)
409	{
410	std::cerr << "<Environment::transition> SIM2OS[2] is not accessible in Write" << std::endl;
411	bus_error = true;
412	}
413	else
414	{
415	// Decomposition en groupe octect
416	Tdcache_data_t error = (Tdcache_data_t)component_sim2os->error;
417	_cout(ENVIRONMENT,"<sim2os> error : %x\n",error);
418
419	itoa<Tdcache_data_t>(error,read_dram[0],size);
420	}
421
422	break;
423	}
424	default : //---> argument
425	{
426	if (must_write == false)
427	{
428	std::cerr << "<Environment::transition> SIM2OS[" << num_reg << "] is not accessible in Read" << std::endl;
429	bus_error = true;
430	}
431	else
432	{
433	_cout(ENVIRONMENT,"<sim2os> argument[%d] : %x\n",num_reg-1,wdata);
434	component_sim2os->parameter(num_reg-2,(void *)wdata);
435	}
436	break;
437	}
438	}
439
440	break;
441	}
442
443	default :
444	{
445	std::cerr << "<Environment::transition> Dcache_req : Unknow type" << std::endl;
446	exit(1);
447	break;
448	}
449	}
450	uncached \|= entity.segment->getUncached();
451	}
452	else
453	{
454	// entity is not present, or is present but is not a memory : have a bus error
455	bus_error = true;
456	uncached = true;
457	}
458
459	if ((must_write == true) and (bus_error == false))
460	{
461	// Permutation if problem of endianness
462	if (endianness::isSameEndianness(context) == false)
463	write_dram = endianness::swapBytes(write_dram, size, nb_bytes);
464
465	bus_error \|= !component_data->write(address, nb_bytes, write_dram); // take the good access
466	}
467
468	// Acces at the cache !!!
469	// Cache WRITE ALLOCATE (becauce compute latence always; )
470	Cache_Access cache_type = dreq_type2cache_type (type,uncached);
471	uint32_t latence = component_cache->latence(cache::DATA_CACHE,
472	i,
473	j,
474	address,
475	context,
476	cache_type.type,
477	cache_type.direction);
478
479	// If is a respons -> compute the latence and push in the write_buffer
480	if (must_ack or (must_ack_on_error and bus_error))
481	{
482	if (bus_error == true)
483	{
484	std::cout << "Dcache : have a bus error" << std::endl
485	<< " * entity : " << i << std::endl
486	<< " * port : " << j << std::endl
487	<< std::hex
488	<< " * req_addr : 0x" << address << std::endl
489	<< std::dec
490	<< " * req_trdid : " << context << std::endl
491	<< " * req_pktid : " << packet << std::endl;
492
493	// Write in data [0] the bad address (32bit or 64bits )
494	itoa<Tdcache_data_t>(address,read_dram[0],param->daccess_size_data[i]/8);
495	}
496
497	// Simplification : the size of a line is a multiple of size_iword (no test)
498	drsp_t * rsp = new drsp_t(context,
499	packet,
500	1,
501	size,
502	read_dram,
503	(bus_error==true)?DCACHE_ERROR_BUS_ERROR:DCACHE_ERROR_NONE);
504	component_buffer_drsp [i]->push(latence,rsp);
505	}
506	}
507	//=============================================================================
508	//===== [ OTHERS ]=============================================================
509	//=============================================================================
510
511	// Transition for each component
512	component_cache -> transition();
513	for (uint32_t i=0; i<param->nb_entity; i++)
514	{
515	component_buffer_irsp [i]->transition();
516	component_buffer_drsp [i]->transition();
517	}
518	component_sim2os->transition();
519	}
520	}
521
522	// // ******************
523	// // *** DCACHE ***
524	// // ******************
525
526	// for (uint32_t j = 0; j < nb_dport [i]; j ++)
527	// {
528	// // Test if transaction
529	// // cout << "[" << i << "]"
530	// // << "[" << j << "] "
531	// // << "dreq_val : " << DCACHE [i][j].REQ_VAL.read() << " "
532	// // << "dreq_ack : " << dreq_ack [i][j] << endl;
533
534	// if ( (DCACHE [i][j].REQ_VAL.read() && dreq_ack [i][j]) == false)
535	// continue;
536
537	// entity_t entity = component_data->entity((uint32_t)DCACHE [i][j].REQ_ADDR.read(), SIZE_DDATA/8);
538
539	// bool uncached = DCACHE [i][j].REQ_UNC.read();
540	// bool bus_error = false;
541
542	// uint32_t addr = (uint32_t) DCACHE [i][j].REQ_ADDR.read();
543	// sc_uint<SIZE_DDATA> wdata = DCACHE[i][j].REQ_WDATA .read();
544	// sc_uint<3> type = DCACHE[i][j].REQ_TYPE .read();
545	// uint32_t nb_bytes = access_nb_bytes(DCACHE[i][j].REQ_ACCESS.read());
546	// // A lot of flag
547	// bool must_read = ((type == DTYPE_READ ));
548	// bool must_write = ((type == DTYPE_WRITE ) \|\|
549	// (type == DTYPE_WRITE_ACK ) );
550	// bool must_ack = ((type == DTYPE_READ ) \|\|
551	// (type == DTYPE_WRITE_ACK ) );
552
553	// // Test the type of the address
554	// if (entity.present == true)
555	// {
556	// switch (entity.segment->getType())
557	// {
558	// // ACCESS AT A RAM
559	// case data::TYPE_TARGET_MEMORY :
560	// {
561	// if (must_read == true)
562	// {
563	// // Read
564	// bus_error \|= !component_data->read(addr ,
565	// SIZE_DDATA/8 , // always read a complete word
566	// read_dram );
567
568	// for (unsigned int it_size_data = nb_bytes; it_size_data < SIZE_DDATA/8; it_size_data+=nb_bytes)
569	// memcpy(&(read_dram[it_size_data]),&(read_dram[0]),nb_bytes);
570
571	// // Permutation if problem of endianness
572	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
573	// read_dram = swapBytes(read_dram , SIZE_DDATA/8, nb_bytes);
574	// }
575
576	// if (must_write == true)
577	// {
578	// // Write
579	// for (unsigned int it_nb_bytes = 0; it_nb_bytes < SIZE_DDATA / 8; it_nb_bytes ++)
580	// write_dram [it_nb_bytes] = wdata.range(8(it_nb_bytes+1)-1,8it_nb_bytes);
581	// }
582	// break;
583	// }
584	// //ACCESS AT THE TTY
585	// case TYPE_TTY :
586	// {
587	// if (must_write == false)
588	// {
589	// bus_error = true;
590	// break;
591	// }
592	// uint32_t num_tty = (addr - entity.segment->getBase())>>4;
593	// uint32_t num_print = ((addr>>2) & 0x3);
594
595	// switch (num_print)
596	// {
597	// case 0 : // Write TTY
598	// {
599	// uint32_t num_component_tty = entity.segment->getIndex();
600	// char char_write = (char)wdata.range( 7, 0);
601	// bus_error \|= !component_tty [num_component_tty]->write(num_tty,char_write);
602	// break;
603	// }
604	// case 1 : // STOP
605	// {
606	// printf("\n\t*** [ stop ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x ***\n"
607	// ,(unsigned int)sc_simulation_time()
608	// ,(unsigned int)addr
609	// ,(unsigned int)wdata.range(31,24)
610	// ,(unsigned int)wdata.range(23,16)
611	// ,(unsigned int)wdata.range(15, 8)
612	// ,(unsigned int)wdata.range( 7, 0)
613	// );
614
615	// uint32_t trdid = (uint32_t) DCACHE[i][j].REQ_TRDID.read();
616
617	// if (context_stop [trdid] == false)
618	// {
619	// context_stop [trdid] = true;
620	// nb_context_stop ++;
621
622	// if (nb_context_stop >= nb_context)
623	// sc_stop();
624	// }
625
626	// break;
627	// }
628	// case 2 : // PRINT
629	// {
630	// printf("\n\t----- [ print ] Time : %.10d - Address : %.8x - Wdata[31:0] : %.2x%.2x%.2x%.2x -----\n"
631	// ,(unsigned int)sc_simulation_time()
632	// ,(unsigned int)addr
633	// ,(unsigned int)wdata.range(31,24)
634	// ,(unsigned int)wdata.range(23,16)
635	// ,(unsigned int)wdata.range(15, 8)
636	// ,(unsigned int)wdata.range( 7, 0)
637	// );
638
639	// break;
640	// }
641	// default :
642	// {
643	// printf("<%s> : [address : %.8x] tty %d, reg %d don't exist\n",NAME,(unsigned int)addr,num_tty,num_print);
644	// exit(1);
645	// }
646	// }
647
648	// break;
649	// }
650	// case TYPE_RAMLOCK :
651	// {
652	// // Access is on a byte, else error
653	// if (nb_bytes != 1)
654	// {
655	// bus_error = true;
656	// break;
657	// }
658	// uint32_t num_ramlock = (addr - entity.segment->getBase()); // Char access
659	// uint32_t num_component_ramlock = entity.segment->getIndex();
660	// bus_error \|= !component_ramlock [num_component_ramlock]->test(num_ramlock);
661
662	// if (bus_error == true)
663	// break;
664
665	// memset (read_dram,0,SIZE_DDATA/8);
666
667	// if (must_read == true)
668	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->read (num_ramlock);
669	// if (must_write == true)
670	// read_dram [0] = (char)component_ramlock [num_component_ramlock]->write(num_ramlock);
671
672	// /*
673	// printf("Access ramlock ( %d )\n" ,(uint32_t)sc_simulation_time());
674	// printf(" * addr : %.8x\n" ,(uint32_t)addr);
675	// printf(" * trdid : %d\n" ,(uint32_t)DCACHE[i][j].REQ_TRDID.read());
676	// printf(" * r/w : %d/%d\n",must_read,must_write);
677	// printf(" * val : %d\n" ,(uint32_t)read_dram[0]);
678	// */
679	// break;
680	// }
681	// case TYPE_SIM2OS :
682	// {
683	// // Mapping :
684	// // [0] number of service - Wonly - A write in this register lunch the execution of service
685	// // [1] result - Ronly - Content the result of the service
686	// // [2] error - Ronly - Content the code of errno
687	// // [3+] argument - Wonly - it's all argument to execute the service
688
689	// uint32_t num_reg = (addr - entity.segment->getBase())>>2;
690
691	// switch (num_reg)
692	// {
693	// case 0 : // ---> number of service
694	// {
695	// if (must_write == false)
696	// {
697	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[0] is not accessible in Read" << endl;
698	// bus_error = true;
699	// }
700	// else
701	// {
702	// printf("<sim2os> service : %.8x\n",(uint32_t)wdata);
703	// component_sim2os->execute(int2service((uint32_t)wdata));
704	// }
705	// break;
706	// }
707	// case 1 : // ---> result
708	// {
709	// if (must_read == false)
710	// {
711	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[1] is not accessible in Write" << endl;
712	// bus_error = true;
713	// }
714	// else
715	// {
716	// // Decomposition en groupe octect
717	// uint32_t result = (uint32_t) component_sim2os->result;
718	// printf("<sim2os> result : %.8x (%d)\n",result,result);
719
720	// read_dram = itoa(result,read_dram,SIZE_DDATA/8);
721	// }
722	// break;
723	// }
724	// case 2 : // ---> error
725	// {
726	// if (must_read == false)
727	// {
728	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[2] is not accessible in Write" << endl;
729	// bus_error = true;
730	// }
731	// else
732	// {
733	// // Decomposition en groupe octect
734	// uint32_t error = (uint32_t) component_sim2os->error;
735	// printf("<sim2os> error : %.8x\n",error);
736	// read_dram = itoa(error ,read_dram,SIZE_DDATA/8);
737	// }
738	// break;
739	// }
740	// default : // ---> argument
741	// {
742	// if (must_write == false)
743	// {
744	// cerr << "<" << NAME << "> {ERROR} : SIM2OS[" << num_reg << "] is not accessible in Write" << endl;
745	// bus_error = true;
746	// }
747	// else
748	// {
749	// uint32_t data = (uint32_t)wdata;
750	// printf("<sim2os> argument[%d] : %.8x\n",num_reg-1,data);
751	// component_sim2os->parameter(num_reg-2,(void *)data);
752	// }
753	// break;
754	// }
755	// }//end switch num_reg
756
757	// break;
758	// }
759	// default :
760	// {
761	// // Have a bus error
762	// bus_error = true;
763	// break;
764	// }
765	// }// switch
766	// uncached \|= entity.segment->getUncached();
767	// }
768	// else
769	// uncached = true; // If segment don't exist : it's the system bus that determine if the segment exist
770
771
772	// if ((must_write == true) && (bus_error == false))
773	// {
774	// // Permutation if problem of endianness
775	// if (isSameEndianness((uint32_t)DCACHE[i][j].REQ_TRDID.read()) == false)
776	// write_dram = swapBytes(write_dram, SIZE_DDATA/8, nb_bytes);
777
778	// bus_error \|= !component_data->write(addr ,
779	// nb_bytes, // take the good access
780	// write_dram );
781	// }
782
783
784	// // Acces at the cache !!!
785	// Cache_Access cache_type = dreq_type2cache_type (type, uncached);
786
787	// uint32_t latence = component_cache->latence(DATA_CACHE ,
788	// i ,
789	// j ,
790	// (uint32_t)DCACHE [i][j].REQ_ADDR .read() ,
791	// (uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
792	// cache_type.type ,
793	// cache_type.direction );
794
795	// // If is a respons -> compute the latence and push in the write_buffer
796	// if ( must_ack == true)
797	// {
798	// if (bus_error == true)
799	// cout << "Dcache : have a bus error" << endl;
800	// component_buffer_drsp [i]->push(latence,
801	// Entry((uint32_t)DCACHE [i][j].REQ_TRDID.read() ,
802	// (uint32_t)DCACHE [i][j].REQ_PKTID.read() ,
803	// 1 ,
804	// SIZE_DDATA/8 ,
805	// &read_dram ,
806	// (bus_error==true)?ERR_BUS:ERR_NO )
807	// );
808	// }
809	// }// dnb_port
810	// }//i
811
812
813	};

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